Commit 4e09f4a6 authored by Andrzej Hajda's avatar Andrzej Hajda Committed by Krzysztof Kozlowski

arm64: dts: exynos: configure TV path clocks for Ultra HD modes

Ultra HD modes requires clock ticking at increased rate.
Signed-off-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parent 9f6fe6f0
...@@ -217,6 +217,18 @@ &cmu_aud { ...@@ -217,6 +217,18 @@ &cmu_aud {
assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>; assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
}; };
&cmu_disp {
assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
<&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
<0>,
<&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
assigned-clock-rates = <0>, <400000000>;
};
&cmu_fsys { &cmu_fsys {
assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>, assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
<&cmu_top CLK_MOUT_SCLK_USBHOST30>, <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
......
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