Commit 4e6c2d58 authored by Chris Wilson's avatar Chris Wilson

drm/i915: Take forcewake once for the entire GMBUS transaction

As we do many register reads within a very short period of time, hold
the GMBUS powerwell from start to finish.
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: David Weinehall <david.weinehall@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20160819164503.17845-1-chris@chris-wilson.co.ukReviewed-by: default avatarDavid Weinehall <david.weinehall@linux.intel.com>
parent 637ee29e
...@@ -255,67 +255,59 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) ...@@ -255,67 +255,59 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
algo->data = bus; algo->data = bus;
} }
static int static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
u32 gmbus2_status,
u32 gmbus4_irq_en)
{ {
int i;
u32 gmbus2 = 0;
DEFINE_WAIT(wait); DEFINE_WAIT(wait);
u32 gmbus2;
if (!HAS_GMBUS_IRQ(dev_priv)) int ret;
gmbus4_irq_en = 0;
/* Important: The hw handles only the first bit, so set only one! Since /* Important: The hw handles only the first bit, so set only one! Since
* we also need to check for NAKs besides the hw ready/idle signal, we * we also need to check for NAKs besides the hw ready/idle signal, we
* need to wake up periodically and check that ourselves. */ * need to wake up periodically and check that ourselves.
I915_WRITE(GMBUS4, gmbus4_irq_en); */
if (!HAS_GMBUS_IRQ(dev_priv))
for (i = 0; i < msecs_to_jiffies_timeout(50); i++) { irq_en = 0;
prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
TASK_UNINTERRUPTIBLE);
gmbus2 = I915_READ_NOTRACE(GMBUS2); add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
if (gmbus2 & (GMBUS_SATOER | gmbus2_status)) I915_WRITE_FW(GMBUS4, irq_en);
break;
schedule_timeout(1); status |= GMBUS_SATOER;
} ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2);
finish_wait(&dev_priv->gmbus_wait_queue, &wait); if (ret)
ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50);
I915_WRITE(GMBUS4, 0); I915_WRITE_FW(GMBUS4, 0);
remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
if (gmbus2 & GMBUS_SATOER) if (gmbus2 & GMBUS_SATOER)
return -ENXIO; return -ENXIO;
if (gmbus2 & gmbus2_status)
return 0; return ret;
return -ETIMEDOUT;
} }
static int static int
gmbus_wait_idle(struct drm_i915_private *dev_priv) gmbus_wait_idle(struct drm_i915_private *dev_priv)
{ {
DEFINE_WAIT(wait);
u32 irq_enable;
int ret; int ret;
if (!HAS_GMBUS_IRQ(dev_priv))
return intel_wait_for_register(dev_priv,
GMBUS2, GMBUS_ACTIVE, 0,
10);
/* Important: The hw handles only the first bit, so set only one! */ /* Important: The hw handles only the first bit, so set only one! */
I915_WRITE(GMBUS4, GMBUS_IDLE_EN); irq_enable = 0;
if (HAS_GMBUS_IRQ(dev_priv))
irq_enable = GMBUS_IDLE_EN;
ret = wait_event_timeout(dev_priv->gmbus_wait_queue, add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
(I915_READ_NOTRACE(GMBUS2) & GMBUS_ACTIVE) == 0, I915_WRITE_FW(GMBUS4, irq_enable);
msecs_to_jiffies_timeout(10));
I915_WRITE(GMBUS4, 0); ret = intel_wait_for_register_fw(dev_priv,
GMBUS2, GMBUS_ACTIVE, 0,
10);
if (ret) I915_WRITE_FW(GMBUS4, 0);
return 0; remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
else
return -ETIMEDOUT; return ret;
} }
static int static int
...@@ -323,7 +315,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, ...@@ -323,7 +315,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
unsigned short addr, u8 *buf, unsigned int len, unsigned short addr, u8 *buf, unsigned int len,
u32 gmbus1_index) u32 gmbus1_index)
{ {
I915_WRITE(GMBUS1, I915_WRITE_FW(GMBUS1,
gmbus1_index | gmbus1_index |
GMBUS_CYCLE_WAIT | GMBUS_CYCLE_WAIT |
(len << GMBUS_BYTE_COUNT_SHIFT) | (len << GMBUS_BYTE_COUNT_SHIFT) |
...@@ -333,12 +325,11 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, ...@@ -333,12 +325,11 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
int ret; int ret;
u32 val, loop = 0; u32 val, loop = 0;
ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
GMBUS_HW_RDY_EN);
if (ret) if (ret)
return ret; return ret;
val = I915_READ(GMBUS3); val = I915_READ_FW(GMBUS3);
do { do {
*buf++ = val & 0xff; *buf++ = val & 0xff;
val >>= 8; val >>= 8;
...@@ -385,8 +376,8 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, ...@@ -385,8 +376,8 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
len -= 1; len -= 1;
} }
I915_WRITE(GMBUS3, val); I915_WRITE_FW(GMBUS3, val);
I915_WRITE(GMBUS1, I915_WRITE_FW(GMBUS1,
GMBUS_CYCLE_WAIT | GMBUS_CYCLE_WAIT |
(chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
(addr << GMBUS_SLAVE_ADDR_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) |
...@@ -399,10 +390,9 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, ...@@ -399,10 +390,9 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
val |= *buf++ << (8 * loop); val |= *buf++ << (8 * loop);
} while (--len && ++loop < 4); } while (--len && ++loop < 4);
I915_WRITE(GMBUS3, val); I915_WRITE_FW(GMBUS3, val);
ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
GMBUS_HW_RDY_EN);
if (ret) if (ret)
return ret; return ret;
} }
...@@ -460,13 +450,13 @@ gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) ...@@ -460,13 +450,13 @@ gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
/* GMBUS5 holds 16-bit index */ /* GMBUS5 holds 16-bit index */
if (gmbus5) if (gmbus5)
I915_WRITE(GMBUS5, gmbus5); I915_WRITE_FW(GMBUS5, gmbus5);
ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
/* Clear GMBUS5 after each index transfer */ /* Clear GMBUS5 after each index transfer */
if (gmbus5) if (gmbus5)
I915_WRITE(GMBUS5, 0); I915_WRITE_FW(GMBUS5, 0);
return ret; return ret;
} }
...@@ -478,11 +468,15 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) ...@@ -478,11 +468,15 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
struct intel_gmbus, struct intel_gmbus,
adapter); adapter);
struct drm_i915_private *dev_priv = bus->dev_priv; struct drm_i915_private *dev_priv = bus->dev_priv;
const unsigned int fw =
intel_uncore_forcewake_for_reg(dev_priv, GMBUS0,
FW_REG_READ | FW_REG_WRITE);
int i = 0, inc, try = 0; int i = 0, inc, try = 0;
int ret = 0; int ret = 0;
intel_uncore_forcewake_get(dev_priv, fw);
retry: retry:
I915_WRITE(GMBUS0, bus->reg0); I915_WRITE_FW(GMBUS0, bus->reg0);
for (; i < num; i += inc) { for (; i < num; i += inc) {
inc = 1; inc = 1;
...@@ -496,8 +490,8 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) ...@@ -496,8 +490,8 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
} }
if (!ret) if (!ret)
ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE, ret = gmbus_wait(dev_priv,
GMBUS_HW_WAIT_EN); GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
if (ret == -ETIMEDOUT) if (ret == -ETIMEDOUT)
goto timeout; goto timeout;
else if (ret) else if (ret)
...@@ -508,7 +502,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) ...@@ -508,7 +502,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
* a STOP on the very first cycle. To simplify the code we * a STOP on the very first cycle. To simplify the code we
* unconditionally generate the STOP condition with an additional gmbus * unconditionally generate the STOP condition with an additional gmbus
* cycle. */ * cycle. */
I915_WRITE(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
/* Mark the GMBUS interface as disabled after waiting for idle. /* Mark the GMBUS interface as disabled after waiting for idle.
* We will re-enable it at the start of the next xfer, * We will re-enable it at the start of the next xfer,
...@@ -519,7 +513,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) ...@@ -519,7 +513,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
adapter->name); adapter->name);
ret = -ETIMEDOUT; ret = -ETIMEDOUT;
} }
I915_WRITE(GMBUS0, 0); I915_WRITE_FW(GMBUS0, 0);
ret = ret ?: i; ret = ret ?: i;
goto out; goto out;
...@@ -548,9 +542,9 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) ...@@ -548,9 +542,9 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
* of resetting the GMBUS controller and so clearing the * of resetting the GMBUS controller and so clearing the
* BUS_ERROR raised by the slave's NAK. * BUS_ERROR raised by the slave's NAK.
*/ */
I915_WRITE(GMBUS1, GMBUS_SW_CLR_INT); I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT);
I915_WRITE(GMBUS1, 0); I915_WRITE_FW(GMBUS1, 0);
I915_WRITE(GMBUS0, 0); I915_WRITE_FW(GMBUS0, 0);
DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
adapter->name, msgs[i].addr, adapter->name, msgs[i].addr,
...@@ -573,7 +567,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) ...@@ -573,7 +567,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
timeout: timeout:
DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
bus->adapter.name, bus->reg0 & 0xff); bus->adapter.name, bus->reg0 & 0xff);
I915_WRITE(GMBUS0, 0); I915_WRITE_FW(GMBUS0, 0);
/* /*
* Hardware may not support GMBUS over these pins? Try GPIO bitbanging * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
...@@ -582,6 +576,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) ...@@ -582,6 +576,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
ret = -EAGAIN; ret = -EAGAIN;
out: out:
intel_uncore_forcewake_put(dev_priv, fw);
return ret; return ret;
} }
......
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