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Commit 4ec16d90 authored by James Simmons's avatar James Simmons
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Updates to SIS framebuffer driver

parent dc20135e
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Showing with 24508 additions and 17484 deletions
drivers/video/sis/300vtbl.h
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drivers/video/sis/310vtbl.h
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drivers/video/sis/325vtbl.h
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drivers/video/sis/init.c
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drivers/video/sis/init.h
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......@@ -6,222 +6,328 @@
#include "vgatypes.h"
#include "vstruct.h"
#ifdef TC
#include <stdio.h>
#include <string.h>
#include <conio.h>
#include <dos.h>
#include <stdlib.h>
#endif
#ifdef LINUX_XF86
#include "xf86.h"
#include "xf86Pci.h"
#include "xf86PciInfo.h"
#include "xf86_OSproc.h"
#include "sis.h"
#include "sis_regs.h"
#endif
#ifdef LINUX_KERNEL
#include <linux/types.h>
#include <asm/io.h>
#include <linux/sisfb.h>
#endif
#ifdef WIN2000
#include <stdio.h>
#include <string.h>
#include <miniport.h>
#include "dderror.h"
#include "devioctl.h"
#include "miniport.h"
#include "ntddvdeo.h"
#include "video.h"
#include "sisv.h"
#include "tools.h"
#endif
USHORT SiS_DRAMType[17][5] = {
{0x0C, 0x0A, 0x02, 0x40, 0x39},
{0x0D, 0x0A, 0x01, 0x40, 0x48},
{0x0C, 0x09, 0x02, 0x20, 0x35},
{0x0D, 0x09, 0x01, 0x20, 0x44},
{0x0C, 0x08, 0x02, 0x10, 0x31},
{0x0D, 0x08, 0x01, 0x10, 0x40},
{0x0C, 0x0A, 0x01, 0x20, 0x34},
{0x0C, 0x09, 0x01, 0x08, 0x32},
{0x0B, 0x08, 0x02, 0x08, 0x21},
{0x0C, 0x08, 0x01, 0x08, 0x30},
{0x0A, 0x08, 0x02, 0x04, 0x11},
{0x0B, 0x0A, 0x01, 0x10, 0x28},
{0x09, 0x08, 0x02, 0x02, 0x01},
{0x0B, 0x09, 0x01, 0x08, 0x24},
{0x0B, 0x08, 0x01, 0x04, 0x20},
{0x0A, 0x08, 0x01, 0x02, 0x10},
{0x09, 0x08, 0x01, 0x01, 0x00}
USHORT SiS_DRAMType[17][5]={
{0x0C,0x0A,0x02,0x40,0x39},
{0x0D,0x0A,0x01,0x40,0x48},
{0x0C,0x09,0x02,0x20,0x35},
{0x0D,0x09,0x01,0x20,0x44},
{0x0C,0x08,0x02,0x10,0x31},
{0x0D,0x08,0x01,0x10,0x40},
{0x0C,0x0A,0x01,0x20,0x34},
{0x0C,0x09,0x01,0x08,0x32},
{0x0B,0x08,0x02,0x08,0x21},
{0x0C,0x08,0x01,0x08,0x30},
{0x0A,0x08,0x02,0x04,0x11},
{0x0B,0x0A,0x01,0x10,0x28},
{0x09,0x08,0x02,0x02,0x01},
{0x0B,0x09,0x01,0x08,0x24},
{0x0B,0x08,0x01,0x04,0x20},
{0x0A,0x08,0x01,0x02,0x10},
{0x09,0x08,0x01,0x01,0x00}
};
USHORT SiS_SDRDRAM_TYPE[13][5] = {
{2, 12, 9, 64, 0x35},
{1, 13, 9, 64, 0x44},
{2, 12, 8, 32, 0x31},
{2, 11, 9, 32, 0x25},
{1, 12, 9, 32, 0x34},
{1, 13, 8, 32, 0x40},
{2, 11, 8, 16, 0x21},
{1, 12, 8, 16, 0x30},
{1, 11, 9, 16, 0x24},
{1, 11, 8, 8, 0x20},
{2, 9, 8, 4, 0x01},
{1, 10, 8, 4, 0x10},
{1, 9, 8, 2, 0x00}
USHORT SiS_SDRDRAM_TYPE[13][5] =
{
{ 2,12, 9,64,0x35},
{ 1,13, 9,64,0x44},
{ 2,12, 8,32,0x31},
{ 2,11, 9,32,0x25},
{ 1,12, 9,32,0x34},
{ 1,13, 8,32,0x40},
{ 2,11, 8,16,0x21},
{ 1,12, 8,16,0x30},
{ 1,11, 9,16,0x24},
{ 1,11, 8, 8,0x20},
{ 2, 9, 8, 4,0x01},
{ 1,10, 8, 4,0x10},
{ 1, 9, 8, 2,0x00}
};
USHORT SiS_DDRDRAM_TYPE[4][5] = {
{2, 12, 9, 64, 0x35},
{2, 12, 8, 32, 0x31},
{2, 11, 8, 16, 0x21},
{2, 9, 8, 4, 0x01}
USHORT SiS_DDRDRAM_TYPE[4][5] =
{
{ 2,12, 9,64,0x35},
{ 2,12, 8,32,0x31},
{ 2,11, 8,16,0x21},
{ 2, 9, 8, 4,0x01}
};
UCHAR SiS_ChannelAB, SiS_DataBusWidth;
USHORT SiS_MDA_DAC[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15,
0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15,
0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15,
0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15,
0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F
USHORT SiS_MDA_DAC[] =
{
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x15,0x15,0x15,0x15,0x15,0x15,0x15,0x15,
0x15,0x15,0x15,0x15,0x15,0x15,0x15,0x15,
0x3F,0x3F,0x3F,0x3F,0x3F,0x3F,0x3F,0x3F,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x15,0x15,0x15,0x15,0x15,0x15,0x15,0x15,
0x15,0x15,0x15,0x15,0x15,0x15,0x15,0x15,
0x3F,0x3F,0x3F,0x3F,0x3F,0x3F,0x3F,0x3F
};
USHORT SiS_CGA_DAC[] = {
0x00, 0x10, 0x04, 0x14, 0x01, 0x11, 0x09, 0x15,
0x00, 0x10, 0x04, 0x14, 0x01, 0x11, 0x09, 0x15,
0x2A, 0x3A, 0x2E, 0x3E, 0x2B, 0x3B, 0x2F, 0x3F,
0x2A, 0x3A, 0x2E, 0x3E, 0x2B, 0x3B, 0x2F, 0x3F,
0x00, 0x10, 0x04, 0x14, 0x01, 0x11, 0x09, 0x15,
0x00, 0x10, 0x04, 0x14, 0x01, 0x11, 0x09, 0x15,
0x2A, 0x3A, 0x2E, 0x3E, 0x2B, 0x3B, 0x2F, 0x3F,
0x2A, 0x3A, 0x2E, 0x3E, 0x2B, 0x3B, 0x2F, 0x3F
USHORT SiS_CGA_DAC[] =
{
0x00,0x10,0x04,0x14,0x01,0x11,0x09,0x15,
0x00,0x10,0x04,0x14,0x01,0x11,0x09,0x15,
0x2A,0x3A,0x2E,0x3E,0x2B,0x3B,0x2F,0x3F,
0x2A,0x3A,0x2E,0x3E,0x2B,0x3B,0x2F,0x3F,
0x00,0x10,0x04,0x14,0x01,0x11,0x09,0x15,
0x00,0x10,0x04,0x14,0x01,0x11,0x09,0x15,
0x2A,0x3A,0x2E,0x3E,0x2B,0x3B,0x2F,0x3F,
0x2A,0x3A,0x2E,0x3E,0x2B,0x3B,0x2F,0x3F
};
USHORT SiS_EGA_DAC[] = {
0x00, 0x10, 0x04, 0x14, 0x01, 0x11, 0x05, 0x15,
0x20, 0x30, 0x24, 0x34, 0x21, 0x31, 0x25, 0x35,
0x08, 0x18, 0x0C, 0x1C, 0x09, 0x19, 0x0D, 0x1D,
0x28, 0x38, 0x2C, 0x3C, 0x29, 0x39, 0x2D, 0x3D,
0x02, 0x12, 0x06, 0x16, 0x03, 0x13, 0x07, 0x17,
0x22, 0x32, 0x26, 0x36, 0x23, 0x33, 0x27, 0x37,
0x0A, 0x1A, 0x0E, 0x1E, 0x0B, 0x1B, 0x0F, 0x1F,
0x2A, 0x3A, 0x2E, 0x3E, 0x2B, 0x3B, 0x2F, 0x3F
USHORT SiS_EGA_DAC[] =
{
0x00,0x10,0x04,0x14,0x01,0x11,0x05,0x15,
0x20,0x30,0x24,0x34,0x21,0x31,0x25,0x35,
0x08,0x18,0x0C,0x1C,0x09,0x19,0x0D,0x1D,
0x28,0x38,0x2C,0x3C,0x29,0x39,0x2D,0x3D,
0x02,0x12,0x06,0x16,0x03,0x13,0x07,0x17,
0x22,0x32,0x26,0x36,0x23,0x33,0x27,0x37,
0x0A,0x1A,0x0E,0x1E,0x0B,0x1B,0x0F,0x1F,
0x2A,0x3A,0x2E,0x3E,0x2B,0x3B,0x2F,0x3F
};
USHORT SiS_VGA_DAC[] = {
0x00, 0x10, 0x04, 0x14, 0x01, 0x11, 0x09, 0x15,
0x2A, 0x3A, 0x2E, 0x3E, 0x2B, 0x3B, 0x2F, 0x3F,
0x00, 0x05, 0x08, 0x0B, 0x0E, 0x11, 0x14, 0x18,
0x1C, 0x20, 0x24, 0x28, 0x2D, 0x32, 0x38, 0x3F,
0x00, 0x10, 0x1F, 0x2F, 0x3F, 0x1F, 0x27, 0x2F,
0x37, 0x3F, 0x2D, 0x31, 0x36, 0x3A, 0x3F, 0x00,
0x07, 0x0E, 0x15, 0x1C, 0x0E, 0x11, 0x15, 0x18,
0x1C, 0x14, 0x16, 0x18, 0x1A, 0x1C, 0x00, 0x04,
0x08, 0x0C, 0x10, 0x08, 0x0A, 0x0C, 0x0E, 0x10,
0x0B, 0x0C, 0x0D, 0x0F, 0x10
USHORT SiS_VGA_DAC[] =
{
0x00,0x10,0x04,0x14,0x01,0x11,0x09,0x15,
0x2A,0x3A,0x2E,0x3E,0x2B,0x3B,0x2F,0x3F,
0x00,0x05,0x08,0x0B,0x0E,0x11,0x14,0x18,
0x1C,0x20,0x24,0x28,0x2D,0x32,0x38,0x3F,
0x00,0x10,0x1F,0x2F,0x3F,0x1F,0x27,0x2F,
0x37,0x3F,0x2D,0x31,0x36,0x3A,0x3F,0x00,
0x07,0x0E,0x15,0x1C,0x0E,0x11,0x15,0x18,
0x1C,0x14,0x16,0x18,0x1A,0x1C,0x00,0x04,
0x08,0x0C,0x10,0x08,0x0A,0x0C,0x0E,0x10,
0x0B,0x0C,0x0D,0x0F,0x10
};
USHORT SiS_P3c4, SiS_P3d4, SiS_P3c0, SiS_P3ce, SiS_P3c2;
USHORT SiS_P3ca, SiS_P3c6, SiS_P3c7, SiS_P3c8, SiS_P3c9, SiS_P3da;
USHORT SiS_Part1Port, SiS_Part2Port;
USHORT SiS_Part3Port, SiS_Part4Port, SiS_Part5Port;
USHORT SiS_CRT1Mode;
USHORT flag_clearbuffer; /*0: no clear frame buffer 1:clear frame buffer */
int SiS_RAMType; /*int ModeIDOffset,StandTable,CRT1Table,ScreenOffset,REFIndex; */
USHORT SiS_ModeType;
USHORT SiS_IF_DEF_LVDS, SiS_IF_DEF_TRUMPION, SiS_IF_DEF_DSTN; /*add for dstn */
USHORT SiS_IF_DEF_CH7005, SiS_IF_DEF_HiVision;
USHORT SiS_VBInfo, SiS_LCDResInfo, SiS_LCDTypeInfo, SiS_LCDInfo, SiS_VBType; /*301b */
USHORT SiS_SelectCRT2Rate;
extern USHORT SiS_SetFlag;
void SiS_SetMemoryClock (ULONG ROMAddr);
void SiS_SetDRAMModeRegister (ULONG ROMAddr);
void SiS_SetDRAMSize_310 (PSIS_HW_DEVICE_INFO);
void SiS_SetDRAMSize_300 (PSIS_HW_DEVICE_INFO HwDeviceExtension);
USHORT SiS_ChkBUSWidth_300 (ULONG FBAddress);
UCHAR SiS_Get310DRAMType (ULONG ROMAddr);
void SiS_Delay15us (ULONG);
BOOLEAN SiS_SearchModeID (ULONG ROMAddr, USHORT ModeNo, USHORT * ModeIdIndex);
BOOLEAN SiS_CheckMemorySize (ULONG ROMAddr,
PSIS_HW_DEVICE_INFO HwDeviceExtension,
USHORT ModeNo, USHORT ModeIdIndex);
UCHAR SiS_GetModePtr (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex);
void SiS_SetSeqRegs (ULONG, USHORT StandTableIndex);
void SiS_SetMiscRegs (ULONG, USHORT StandTableIndex);
void SiS_SetCRTCRegs (ULONG, PSIS_HW_DEVICE_INFO HwDeviceExtension,
USHORT StandTableIndex);
void SiS_SetATTRegs (ULONG, USHORT StandTableIndex);
void SiS_SetGRCRegs (ULONG, USHORT StandTableIndex);
void SiS_ClearExt1Regs (void);
void SiS_SetSync (ULONG ROMAddr, USHORT RefreshRateTableIndex);
void SiS_SetCRT1CRTC (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex,
USHORT RefreshRateTableIndex);
void SiS_SetCRT1VCLK (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex,
PSIS_HW_DEVICE_INFO, USHORT RefreshRateTableIndex);
void SiS_SetVCLKState (ULONG ROMAddr, PSIS_HW_DEVICE_INFO, USHORT ModeNo,
USHORT RefreshRateTableIndex);
void SiS_LoadDAC (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex);
void SiS_DisplayOn (void);
void SiS_SetCRT1ModeRegs (ULONG ROMAddr, PSIS_HW_DEVICE_INFO, USHORT ModeNo,
USHORT ModeIdIndex, USHORT RefreshRateTableIndex);
void SiS_WriteDAC (USHORT, USHORT, USHORT, USHORT);
void SiS_GetVBType (USHORT BaseAddr); /*301b */
USHORT SiS_ChkBUSWidth (ULONG);
USHORT SiS_GetModeIDLength (ULONG, USHORT);
USHORT SiS_GetRefindexLength (ULONG, USHORT);
void SiS_SetInterlace (ULONG ROMAddr, USHORT ModeNo,
USHORT RefreshRateTableIndex);
USHORT SiS_CalcDelay2 (ULONG, UCHAR);
USHORT SiS_CalcDelay (ULONG, USHORT);
void SiS_Set_LVDS_TRUMPION (PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetCRT1Offset (ULONG, USHORT, USHORT, USHORT, PSIS_HW_DEVICE_INFO);
void SiS_SetCRT1FIFO (ULONG, USHORT, PSIS_HW_DEVICE_INFO);
void SiS_SetCRT1FIFO2 (ULONG, USHORT ModeNo, PSIS_HW_DEVICE_INFO,
USHORT RefreshRateTableIndex);
void SiS_CRT2AutoThreshold (USHORT BaseAddr);
void SiS_ClearBuffer (PSIS_HW_DEVICE_INFO, USHORT ModeNo);
void SiS_SetCRT1Group (ULONG ROMAddr, PSIS_HW_DEVICE_INFO HwDeviceExtension,
USHORT ModeNo, USHORT ModeIdIndex);
void SiS_DetectMonitor (PSIS_HW_DEVICE_INFO HwDeviceExtension, USHORT BaseAddr);
void SiS_GetSenseStatus (PSIS_HW_DEVICE_INFO HwDeviceExtension, ULONG ROMAddr);
USHORT SiS_TestMonitorType (UCHAR R_DAC, UCHAR G_DAC, UCHAR B_DAC);
USHORT SiS_SenseCHTV (VOID);
BOOLEAN SiS_Sense (USHORT Part4Port, USHORT tempbx, USHORT tempcx);
BOOLEAN SiS_GetPanelID (VOID);
BOOLEAN SiS_GetLCDDDCInfo (PSIS_HW_DEVICE_INFO);
USHORT SiS_SenseLCD (PSIS_HW_DEVICE_INFO);
extern BOOLEAN SiS_SetCRT2Group301 (USHORT BaseAddr, ULONG ROMAddr,
USHORT ModeNo,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
extern void SiS_PresetScratchregister (USHORT SiS_P3d4,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
extern void SiS_UnLockCRT2 (PSIS_HW_DEVICE_INFO HwDeviceExtension,
USHORT BaseAddr);
extern void SiS_LockCRT2 (PSIS_HW_DEVICE_INFO HwDeviceExtension,
USHORT BaseAddr);
extern BOOLEAN SiS_BridgeIsOn (USHORT BaseAddr);
extern BOOLEAN SiS_BridgeIsEnable (USHORT BaseAddr, PSIS_HW_DEVICE_INFO);
extern void SiS_SetTVSystem301 (VOID);
extern BOOLEAN SiS_GetLCDDDCInfo301 (PSIS_HW_DEVICE_INFO HwDeviceExtension);
extern BOOLEAN SiS_GetSenseStatus301 (PSIS_HW_DEVICE_INFO HwDeviceExtension,
USHORT BaseAddr, ULONG ROMAddr);
extern USHORT SiS_GetVCLKLen (ULONG ROMAddr,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
extern BOOLEAN SiS_SetCRT2Group302 (USHORT BaseAddr, ULONG ROMAddr,
USHORT ModeNo,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
extern void SiS_GetVBInfo301 (USHORT BaseAddr, ULONG ROMAddr, USHORT ModeNo,
USHORT ModeIdIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
extern BOOLEAN SiS_GetLCDResInfo301 (ULONG ROMAddr, USHORT P3d4, USHORT ModeNo,
USHORT ModeIdIndex);
extern USHORT SiS_VBInfo, LCDResInfo, LCDTypeInfo, LCDInfo;
extern USHORT SiS_GetRatePtrCRT2 (ULONG ROMAddr, USHORT ModeNo,
USHORT ModeIdIndex);
extern void SiS_LongWait (VOID);
extern void SiS_SetRegANDOR (USHORT Port, USHORT Index, USHORT DataAND,
USHORT DataOR);
extern USHORT SiS_GetResInfo (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex);
extern void SiS_SetCH7005 (USHORT tempax);
extern USHORT SiS_GetCH7005 (USHORT tempax);
extern BOOLEAN SiS_GetLVDSCRT1Ptr (ULONG ROMAddr, USHORT ModeNo,
USHORT ModeIdIndex,
USHORT RefreshRateTableIndex,
USHORT * ResInfo, USHORT * DisplayType);
extern BOOLEAN SiS_GetLCDACRT1Ptr (ULONG ROMAddr, USHORT ModeNo,
USHORT ModeIdIndex,
USHORT RefreshRateTableIndex,
USHORT * ResInfo, USHORT * DisplayType);
extern USHORT SiS_GetVCLK2Ptr (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex,
USHORT RefreshRateTableIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
extern BOOLEAN SiS_Is301B (USHORT BaseAddr); /*301b */
USHORT SiS_P3c4,SiS_P3d4,SiS_P3c0,SiS_P3ce,SiS_P3c2;
USHORT SiS_P3ca,SiS_P3c6,SiS_P3c7,SiS_P3c8,SiS_P3c9,SiS_P3da;
USHORT SiS_Part1Port,SiS_Part2Port;
USHORT SiS_Part3Port,SiS_Part4Port,SiS_Part5Port;
USHORT SiS_CRT1Mode;
USHORT flag_clearbuffer;
int SiS_RAMType;
USHORT SiS_ModeType;
USHORT SiS_IF_DEF_LVDS, SiS_IF_DEF_TRUMPION, SiS_IF_DEF_DSTN, SiS_IF_DEF_FSTN;
USHORT SiS_IF_DEF_CH70xx, SiS_IF_DEF_HiVision;
USHORT SiS_Backup70xx=0xff;
USHORT SiS_VBInfo, SiS_LCDResInfo, SiS_LCDTypeInfo, SiS_LCDInfo, SiS_VBType;
USHORT SiS_VBExtInfo, SiS_HiVision;
USHORT SiS_SelectCRT2Rate;
extern USHORT SiS_SetFlag;
extern USHORT SiS_DDC_Port;
extern USHORT Panel800x600, Panel1024x768, Panel1280x1024, Panel1600x1200;
extern USHORT Panel1280x960, Panel1400x1050, Panel320x480, Panel1152x768;
extern USHORT Panel1152x864, Panel1280x768, Panel1024x600, Panel640x480;
extern USHORT PanelMinLVDS, PanelMin301, PanelMax;
extern USHORT SiS_ChrontelInit;
void SiS_SetReg1(USHORT, USHORT, USHORT);
void SiS_SetReg2(USHORT, USHORT, USHORT);
void SiS_SetReg3(USHORT, USHORT);
void SiS_SetReg4(USHORT, ULONG);
UCHAR SiS_GetReg1(USHORT, USHORT);
UCHAR SiS_GetReg2(USHORT);
ULONG SiS_GetReg3(USHORT);
void SiS_ClearDAC(ULONG);
void SiS_SetMemoryClock(UCHAR *ROMAddr,PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetDRAMModeRegister(UCHAR *ROMAddr,PSIS_HW_DEVICE_INFO HwDeviceExtension);
BOOLEAN SiS_SearchVBModeID(UCHAR *ROMAddr, USHORT *ModeNo);
void SiS_IsLowResolution(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex);
ULONG GetDRAMSize(PSIS_HW_DEVICE_INFO HwDeviceExtension);
#ifdef SIS300
void InitTo300Pointer(PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetDRAMSize_300(PSIS_HW_DEVICE_INFO HwDeviceExtension);
USHORT SiS_ChkBUSWidth_300(ULONG FBAddress);
#endif
#ifdef SIS315H
void InitTo310Pointer(PSIS_HW_DEVICE_INFO HwDeviceExtension);
UCHAR SiS_Get310DRAMType(UCHAR *ROMAddr,PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_DDR_MRS(void);
void SiS_SDR_MRS(void);
void SiS_DisableRefresh(void);
void SiS_EnableRefresh(UCHAR *ROMAddr);
void SiS_SetDRAMSize_310(PSIS_HW_DEVICE_INFO);
void SiS_DisableChannelInterleaving(int index,USHORT SiS_DDRDRAM_TYPE[][5]);
void SiS_SetDRAMSizingType(int index,USHORT DRAMTYPE_TABLE[][5]);
void SiS_CheckBusWidth_310(UCHAR *ROMAddress,ULONG FBAddress,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
int SiS_SetRank(int index,UCHAR RankNo,UCHAR SiS_ChannelAB,USHORT DRAMTYPE_TABLE[][5]);
int SiS_SetDDRChannel(int index,UCHAR ChannelNo,UCHAR SiS_ChannelAB,
USHORT DRAMTYPE_TABLE[][5]);
int SiS_CheckColumn(int index,USHORT DRAMTYPE_TABLE[][5],ULONG FBAddress);
int SiS_CheckBanks(int index,USHORT DRAMTYPE_TABLE[][5],ULONG FBAddress);
int SiS_CheckRank(int RankNo,int index,USHORT DRAMTYPE_TABLE[][5],ULONG FBAddress);
int SiS_CheckDDRRank(int RankNo,int index,USHORT DRAMTYPE_TABLE[][5],ULONG FBAddress);
int SiS_CheckRanks(int RankNo,int index,USHORT DRAMTYPE_TABLE[][5],ULONG FBAddress);
int SiS_CheckDDRRanks(int RankNo,int index,USHORT DRAMTYPE_TABLE[][5],ULONG FBAddress);
int SiS_SDRSizing(ULONG FBAddress);
int SiS_DDRSizing(ULONG FBAddress);
int Is315E(void);
void SiS_VerifyMclk(ULONG FBAddr);
#endif
void SetEnableDstn(void);
void SiS_Delay15us(ULONG);
BOOLEAN SiS_SearchModeID(UCHAR *ROMAddr, USHORT *ModeNo,USHORT *ModeIdIndex);
BOOLEAN SiS_CheckMemorySize(UCHAR *ROMAddr,PSIS_HW_DEVICE_INFO HwDeviceExtension,
USHORT ModeNo,USHORT ModeIdIndex);
UCHAR SiS_GetModePtr(UCHAR *ROMAddr, USHORT ModeNo,USHORT ModeIdIndex);
void SiS_SetSeqRegs(UCHAR *ROMAddr,USHORT StandTableIndex);
void SiS_SetMiscRegs(UCHAR *ROMAddr,USHORT StandTableIndex);
void SiS_SetCRTCRegs(UCHAR *ROMAddr,PSIS_HW_DEVICE_INFO HwDeviceExtension,
USHORT StandTableIndex);
void SiS_SetATTRegs(UCHAR *ROMAddr,USHORT StandTableIndex,USHORT ModeNo,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetGRCRegs(UCHAR *ROMAddr,USHORT StandTableIndex);
void SiS_ClearExt1Regs(PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetSync(UCHAR *ROMAddr,USHORT RefreshRateTableIndex);
void SiS_SetCRT1CRTC(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,
USHORT RefreshRateTableIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_ResetCRT1VCLK(UCHAR *ROMAddr,PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetCRT1VCLK(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,PSIS_HW_DEVICE_INFO,
USHORT RefreshRateTableIndex);
void SiS_SetVCLKState(UCHAR *ROMAddr,PSIS_HW_DEVICE_INFO, USHORT ModeNo,
USHORT RefreshRateTableIndex, USHORT ModeIdIndex);
void SiS_LoadDAC(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex);
void SiS_DisplayOn(void);
void SiS_DisplayOff(void);
void SiS_SetCRT1ModeRegs(UCHAR *ROMAddr,PSIS_HW_DEVICE_INFO,USHORT ModeNo,
USHORT ModeIdIndex,USHORT RefreshRateTableIndex);
void SiS_WriteDAC(USHORT, USHORT, USHORT, USHORT);
void SiS_GetVBType(USHORT BaseAddr,PSIS_HW_DEVICE_INFO);
USHORT SiS_ChkBUSWidth(UCHAR *ROMAddr);
USHORT SiS_GetModeIDLength(UCHAR *ROMAddr, USHORT);
USHORT SiS_GetRefindexLength(UCHAR *ROMAddr, USHORT);
void SiS_SetInterlace(UCHAR *ROMAddr,USHORT ModeNo,USHORT RefreshRateTableIndex);
USHORT SiS_CalcDelay2(UCHAR *ROMAddr, UCHAR);
USHORT SiS_CalcDelay(UCHAR *ROMAddr, USHORT);
void SiS_Set_LVDS_TRUMPION(PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetCRT1Offset(UCHAR *ROMAddr,USHORT,USHORT,USHORT,PSIS_HW_DEVICE_INFO);
#ifdef SIS315H
void SiS_SetCRT1FIFO_310(UCHAR *ROMAddr,USHORT,USHORT,PSIS_HW_DEVICE_INFO);
#endif
#ifdef SIS300
void SiS_SetCRT1FIFO_300(UCHAR *ROMAddr,USHORT ModeNo,PSIS_HW_DEVICE_INFO,
USHORT RefreshRateTableIndex);
#endif
void SiS_ClearBuffer(PSIS_HW_DEVICE_INFO,USHORT ModeNo);
void SiS_SetCRT1Group(UCHAR *ROMAddr,PSIS_HW_DEVICE_INFO HwDeviceExtension,
USHORT ModeNo,USHORT ModeIdIndex,USHORT BaseAddr);
void SiS_DetectMonitor(PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT BaseAddr);
void SiS_GetSenseStatus(PSIS_HW_DEVICE_INFO HwDeviceExtension,UCHAR *ROMAddr);
USHORT SiS_TestMonitorType(UCHAR R_DAC,UCHAR G_DAC,UCHAR B_DAC);
USHORT SiS_SenseCHTV(VOID);
BOOLEAN SiS_Sense(USHORT Part4Port,USHORT tempbx,USHORT tempcx);
BOOLEAN SiS_GetPanelID(VOID);
BOOLEAN SiS_GetLCDDDCInfo(PSIS_HW_DEVICE_INFO);
USHORT SiS_SenseLCD(PSIS_HW_DEVICE_INFO);
void SiSRegInit(USHORT BaseAddr);
void SiSInitPtr(PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiSSetLVDSetc(PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT ModeNo);
void SiSInitPCIetc(PSIS_HW_DEVICE_INFO HwDeviceExtension);
#ifdef LINUX_XF86
USHORT SiS_CalcModeIndex(ScrnInfoPtr pScrn, DisplayModePtr mode);
USHORT SiS_CheckCalcModeIndex(ScrnInfoPtr pScrn, DisplayModePtr mode, int VBFlags);
void SiS_SetPitch(ScrnInfoPtr pScrn, UShort BaseAddr);
void SiS_SetPitchCRT1(ScrnInfoPtr pScrn, UShort BaseAddr);
void SiS_SetPitchCRT2(ScrnInfoPtr pScrn, UShort BaseAddr);
unsigned char SiS_GetSetModeID(ScrnInfoPtr pScrn, unsigned char id);
#endif
extern USHORT SiS_GetOffset(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,
USHORT RefreshRateTableIndex,PSIS_HW_DEVICE_INFO HwDeviceExtension);
extern USHORT SiS_GetColorDepth(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex);
extern void SiS_DisableBridge(PSIS_HW_DEVICE_INFO HwDeviceExtension, USHORT BaseAddr);
extern BOOLEAN SiS_SetCRT2Group301(USHORT BaseAddr,UCHAR *ROMAddr,USHORT ModeNo,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
extern void SiS_PresetScratchregister(USHORT SiS_P3d4,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
extern void SiS_UnLockCRT2(PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT BaseAddr);
extern void SiS_LockCRT2(PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT BaseAddr);
extern BOOLEAN SiS_BridgeIsOn(USHORT BaseAddr);
extern BOOLEAN SiS_BridgeIsEnable(USHORT BaseAddr,PSIS_HW_DEVICE_INFO );
extern void SiS_SetTVSystem301(VOID);
extern BOOLEAN SiS_GetLCDDDCInfo301(PSIS_HW_DEVICE_INFO HwDeviceExtension);
extern BOOLEAN SiS_GetSenseStatus301(PSIS_HW_DEVICE_INFO HwDeviceExtension,
USHORT BaseAddr,UCHAR *ROMAddr);
extern USHORT SiS_GetVCLKLen(UCHAR *ROMAddr,PSIS_HW_DEVICE_INFO HwDeviceExtension);
extern BOOLEAN SiS_SetCRT2Group302(USHORT BaseAddr,UCHAR *ROMAddr,USHORT ModeNo,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
extern void SiS_GetVBInfo301(USHORT BaseAddr,UCHAR *ROMAddr,USHORT ModeNo,
USHORT ModeIdIndex,PSIS_HW_DEVICE_INFO HwDeviceExtension);
extern BOOLEAN SiS_GetLCDResInfo301(UCHAR *ROMAddr,USHORT P3d4,USHORT ModeNo,
USHORT ModeIdIndex, PSIS_HW_DEVICE_INFO HwDeviceExtension);
extern void SiS_SetHiVision(USHORT BaseAddr,PSIS_HW_DEVICE_INFO HwDeviceExtension);
/* extern USHORT SiS_VBInfo,LCDResInfo,LCDTypeInfo,LCDInfo; */ /* TW: redundant */
extern USHORT SiS_GetRatePtrCRT2(UCHAR *ROMAddr, USHORT ModeNo,USHORT ModeIdIndex);
extern void SiS_LongWait(VOID);
extern void SiS_SetRegOR(USHORT Port,USHORT Index,USHORT DataOR);
extern void SiS_SetRegAND(USHORT Port,USHORT Index,USHORT DataAND);
extern void SiS_SetRegANDOR(USHORT Port,USHORT Index,USHORT DataAND,USHORT DataOR);
extern USHORT SiS_GetResInfo(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex);
extern void SiS_SetCH700x(USHORT tempax);
extern USHORT SiS_GetCH700x(USHORT tempax);
extern void SiS_SetCH701x(USHORT tempax);
extern USHORT SiS_GetCH701x(USHORT tempax);
extern void SiS_SetCH70xx(USHORT tempax);
extern USHORT SiS_GetCH70xx(USHORT tempax);
extern BOOLEAN SiS_GetLVDSCRT1Ptr(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,
USHORT RefreshRateTableIndex,
USHORT *ResInfo,USHORT *DisplayType);
extern BOOLEAN SiS_GetLCDACRT1Ptr(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,
USHORT RefreshRateTableIndex,
USHORT *ResInfo,USHORT *DisplayType);
extern USHORT SiS_GetVCLK2Ptr(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,
USHORT RefreshRateTableIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
extern BOOLEAN SiS_Is301B(USHORT BaseAddr);
extern BOOLEAN SiS_LowModeStuff(USHORT ModeNo,PSIS_HW_DEVICE_INFO HwDeviceExtension);
#endif
drivers/video/sis/init301.c
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drivers/video/sis/init301.h
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......@@ -7,217 +7,308 @@
#include "vgatypes.h"
#include "vstruct.h"
#ifdef TC
#include <stdio.h>
#include <string.h>
#include <conio.h>
#include <dos.h>
#include <stdlib.h>
#endif
#ifdef LINUX_XF86
#include "xf86.h"
#include "xf86Pci.h"
#include "xf86PciInfo.h"
#include "sis.h"
#include "sis_regs.h"
#endif
#ifdef LINUX_KERNEL
#include <asm/io.h>
#include <linux/types.h>
#include <linux/sisfb.h>
#endif
#ifdef WIN2000
#include <stdio.h>
#include <string.h>
#include <miniport.h>
#include "dderror.h"
#include "devioctl.h"
#include "miniport.h"
#include "ntddvdeo.h"
#include "video.h"
#include "sisv.h"
#endif
USHORT SiS_SetFlag;
USHORT SiS_RVBHCFACT,SiS_RVBHCMAX,SiS_RVBHRS;
USHORT SiS_VGAVT,SiS_VGAHT;
USHORT SiS_VT,SiS_HT;
USHORT SiS_VGAVDE,SiS_VGAHDE;
USHORT SiS_VDE,SiS_HDE;
USHORT SiS_NewFlickerMode,SiS_RY1COE,SiS_RY2COE,SiS_RY3COE,SiS_RY4COE;
USHORT SiS_LCDHDES,SiS_LCDVDES;
USHORT SiS_DDC_Port, SiS_DDC_Index,SiS_DDC_Data, SiS_DDC_Clk;
USHORT SiS_DDC_DataShift, SiS_DDC_DeviceAddr, SiS_DDC_Flag;
USHORT SiS_DDC_ReadAddr, SiS_DDC_Buffer;
USHORT Panel800x600, Panel1024x768, Panel1280x1024, Panel1600x1200;
USHORT Panel1280x960, Panel1400x1050, Panel320x480, Panel1152x768;
USHORT Panel1280x768, Panel1024x600, Panel640x480, Panel1152x864;
USHORT PanelMax, PanelMinLVDS, PanelMin301;
USHORT SiS_ChrontelInit;
extern USHORT SiS_CRT1Mode;
extern USHORT SiS_P3c4,SiS_P3d4;
extern USHORT SiS_P3ca;
extern USHORT SiS_P3c9;
extern USHORT SiS_P3da;
extern USHORT SiS_Part1Port,SiS_Part2Port;
extern USHORT SiS_Part3Port,SiS_Part4Port,SiS_Part5Port;
extern USHORT SiS_MDA_DAC[];
extern USHORT SiS_CGA_DAC[];
extern USHORT SiS_EGA_DAC[];
extern USHORT SiS_VGA_DAC[];
extern USHORT SiS_ModeType;
extern USHORT SiS_SelectCRT2Rate;
extern USHORT SiS_IF_DEF_LVDS;
extern USHORT SiS_IF_DEF_TRUMPION;
extern USHORT SiS_IF_DEF_CH70xx;
extern USHORT SiS_Backup70xx;
extern USHORT SiS_IF_DEF_HiVision;
extern USHORT SiS_IF_DEF_DSTN; /*add for dstn*/
extern USHORT SiS_IF_DEF_FSTN; /*add for fstn*/
extern USHORT SiS_VBInfo;
extern USHORT SiS_VBType;
extern USHORT SiS_VBExtInfo;
extern USHORT SiS_LCDResInfo;
extern USHORT SiS_LCDTypeInfo;
extern USHORT SiS_LCDInfo;
extern USHORT SiS_HiVision;
extern BOOLEAN SiS_SearchVBModeID(UCHAR *RomAddr, USHORT *);
BOOLEAN SiS_Is301B(USHORT BaseAddr);
BOOLEAN SiS_IsDisableCRT2(USHORT BaseAddr);
BOOLEAN SiS_IsVAMode(PSIS_HW_DEVICE_INFO HwDeviceExtension, USHORT BaseAddr);
BOOLEAN SiS_IsDualEdge(PSIS_HW_DEVICE_INFO HwDeviceExtension, USHORT BaseAddr);
BOOLEAN SiS_CRT2IsLCD(USHORT BaseAddr);
void SiS_SetDefCRT2ExtRegs(USHORT BaseAddr);
USHORT SiS_GetRatePtrCRT2(UCHAR *ROMAddr, USHORT ModeNo,USHORT ModeIdIndex);
BOOLEAN SiS_AdjustCRT2Rate(UCHAR *ROMAddr,USHORT ModeNo,USHORT MODEIdIndex,USHORT RefreshRateTableIndex,USHORT *i);
void SiS_SaveCRT2Info(USHORT ModeNo);
void SiS_GetCRT2Data(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,USHORT RefreshRateTableIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_GetCRT2DataLVDS(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,USHORT RefreshRateTableIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_GetCRT2PtrA(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,USHORT RefreshRateTableIndex,
USHORT *CRT2Index,USHORT *ResIndex);
void SiS_GetCRT2Part2Ptr(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,
USHORT RefreshRateTableIndex,USHORT *CRT2Index,
USHORT *ResIndex);
void SiS_GetCRT2Data301(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,USHORT RefreshRateTableIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
USHORT SiS_GetResInfo(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex);
void SiS_GetCRT2ResInfo(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_GetRAMDAC2DATA(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,USHORT RefreshRateTableIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_GetCRT2Ptr(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,USHORT RefreshRateTableIndex,
USHORT *CRT2Index,USHORT *ResIndex,PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetCRT2ModeRegs(USHORT BaseAddr,USHORT ModeNo,USHORT ModeIdIndex, PSIS_HW_DEVICE_INFO );
void SiS_SetHiVision(USHORT BaseAddr,PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_GetLVDSDesData(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,USHORT RefreshRateTableIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetCRT2Offset(USHORT Part1Port,UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,
USHORT RefreshRateTableIndex,PSIS_HW_DEVICE_INFO HwDeviceExtension);
USHORT SiS_GetOffset(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,USHORT RefreshRateTableIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
USHORT SiS_GetColorDepth(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex);
USHORT SiS_GetMCLK(UCHAR *ROMAddr, PSIS_HW_DEVICE_INFO HwDeviceExtension);
USHORT SiS_CalcDelayVB(void);
USHORT SiS_GetVCLK2Ptr(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,
USHORT RefreshRateTableIndex,PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetCRT2Sync(USHORT BaseAddr,UCHAR *ROMAddr,USHORT ModeNo,USHORT RefreshRateTableIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetRegANDOR(USHORT Port,USHORT Index,USHORT DataAND,USHORT DataOR);
void SiS_SetRegOR(USHORT Port,USHORT Index,USHORT DataOR);
void SiS_SetRegAND(USHORT Port,USHORT Index,USHORT DataAND);
USHORT SiS_GetVGAHT2(void);
void SiS_SetGroup2(USHORT BaseAddr,UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,
USHORT RefreshRateTableIndex,PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetGroup3(USHORT BaseAddr,UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetGroup4(USHORT BaseAddr,UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,
USHORT RefreshRateTableIndex,PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetGroup5(USHORT BaseAddr,UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex);
void SiS_SetCRT2VCLK(USHORT BaseAddr,UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,
USHORT RefreshRateTableIndex,PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_EnableCRT2(void);
void SiS_LoadDAC2(UCHAR *ROMAddr,USHORT Part5Port,USHORT ModeNo,USHORT ModeIdIndex);
void SiS_WriteDAC2(USHORT Pdata,USHORT dl, USHORT ah, USHORT al, USHORT dh);
void SiS_GetVBInfo301(USHORT BaseAddr,UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
BOOLEAN SiS_GetLCDResInfo(UCHAR *ROMAddr,USHORT P3d4,USHORT ModeNo,USHORT ModeIdIndex);
BOOLEAN SiS_BridgeIsOn(USHORT BaseAddr,PSIS_HW_DEVICE_INFO);
BOOLEAN SiS_BridgeIsEnable(USHORT BaseAddr,PSIS_HW_DEVICE_INFO);
BOOLEAN SiS_BridgeInSlave(void);
void SiS_PresetScratchregister(USHORT SiS_P3d4,PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetTVSystem(VOID);
void SiS_LongWait(VOID);
USHORT SiS_GetQueueConfig(VOID);
void SiS_VBLongWait(VOID);
USHORT SiS_GetVCLKLen(UCHAR *ROMAddr);
void SiS_WaitVBRetrace(PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_WaitRetrace1(PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_WaitRetrace2(PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetCRT2ECLK(UCHAR *ROMAddr, USHORT ModeNo,USHORT ModeIdIndex,USHORT RefreshRateTableIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_GetLVDSDesPtr(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,USHORT RefreshRateTableIndex,
USHORT *PanelIndex,USHORT *ResIndex,PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_GetLVDSDesPtrA(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,USHORT RefreshRateTableIndex,
USHORT *PanelIndex,USHORT *ResIndex);
void SiS_SetTPData(VOID);
void SiS_ModCRT1CRTC(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,USHORT RefreshRateTableIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
extern BOOLEAN SiS_GetLVDSCRT1Ptr(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,USHORT RefreshRateTableIndex,
USHORT *ResInfo,USHORT *DisplayType);
void SiS_SetCHTVReg(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,USHORT RefreshRateTableIndex);
void SiS_GetCHTVRegPtr(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,USHORT RefreshRateTableIndex);
void SiS_SetCH700x(USHORT tempax);
USHORT SiS_GetCH700x(USHORT tempax);
void SiS_SetCH701x(USHORT tempax);
USHORT SiS_GetCH701x(USHORT tempax);
void SiS_SetCH70xx(USHORT tempax);
USHORT SiS_GetCH70xx(USHORT tempax);
void SiS_SetCH70xxANDOR(USHORT tempax,USHORT tempbh);
void SiS_SetSwitchDDC2(void);
USHORT SiS_SetStart(void);
USHORT SiS_SetStop(void);
void SiS_DDC2Delay(USHORT delaytime);
USHORT SiS_SetSCLKLow(void);
USHORT SiS_SetSCLKHigh(void);
USHORT SiS_ReadDDC2Data(USHORT tempax);
USHORT SiS_WriteDDC2Data(USHORT tempax);
USHORT SiS_CheckACK(void);
#ifdef SIS315H
void SiS_OEM310Setting(PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT BaseAddr,
UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex);
void SiS_OEMLCD(PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT BaseAddr,
UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex);
#endif
#ifdef SIS300
void SiS_OEM300Setting(PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT BaseAddr,
UCHAR *ROMAddr,USHORT ModeNo);
#endif
USHORT GetRevisionID(PSIS_HW_DEVICE_INFO HwDeviceExtension);
BOOLEAN SiS_LowModeStuff(USHORT ModeNo,PSIS_HW_DEVICE_INFO HwDeviceExtension);
BOOLEAN SiS_GetLCDResInfo301(UCHAR *ROMAddr,USHORT SiS_P3d4, USHORT ModeNo, USHORT ModeIdIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
/* void SiS_CHACRT1CRTC(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,
USHORT RefreshRateTableIndex); */
BOOLEAN SiS_GetLCDACRT1Ptr(UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,
USHORT RefreshRateTableIndex,USHORT *ResInfo,
USHORT *DisplayType);
/* 310 series OEM */
USHORT GetLCDPtrIndex (void);
USHORT GetTVPtrIndex(void);
void SetDelayComp(PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT BaseAddr,
UCHAR *ROMAddr,USHORT ModeNo);
void SetAntiFlicker(PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT BaseAddr,
UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex);
void SetEdgeEnhance (PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT BaseAddr,
UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex);
void SetYFilter(PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT BaseAddr,
UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex);
void SetPhaseIncr(PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT BaseAddr,
UCHAR *ROMAddr,USHORT ModeNo);
/* 300 series OEM */
USHORT GetOEMLCDPtr(PSIS_HW_DEVICE_INFO HwDeviceExtension, int Flag);
USHORT GetOEMTVPtr(void);
void SetOEMTVDelay(PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT BaseAddr,
UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex);
void SetOEMLCDDelay(PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT BaseAddr,
UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex);
void SetOEMAntiFlicker(PSIS_HW_DEVICE_INFO HwDeviceExtension,
USHORT BaseAddr,UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex);
void SetOEMPhaseIncr(PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT BaseAddr,
UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex);
void SetOEMYFilter(PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT BaseAddr,
UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex);
extern void SiS_SetReg1(USHORT, USHORT, USHORT);
extern void SiS_SetReg3(USHORT, USHORT);
extern UCHAR SiS_GetReg1(USHORT, USHORT);
extern UCHAR SiS_GetReg2(USHORT);
extern BOOLEAN SiS_SearchModeID(UCHAR *ROMAddr, USHORT *ModeNo,USHORT *ModeIdIndex);
extern BOOLEAN SiS_GetRatePtr(ULONG, USHORT);
extern void SiS_SetReg4(USHORT, ULONG);
extern ULONG SiS_GetReg3(USHORT);
extern void SiS_DisplayOff(void);
extern void SiS_DisplayOn(void);
extern UCHAR SiS_GetModePtr(UCHAR *ROMAddr, USHORT ModeNo,USHORT ModeIdIndex);
#ifdef SIS315H
extern UCHAR SiS_Get310DRAMType(UCHAR *ROMAddr,PSIS_HW_DEVICE_INFO HwDeviceExtension);
#endif
BOOLEAN SiS_SetCRT2Group301(USHORT BaseAddr,UCHAR *ROMAddr,USHORT ModeNo,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetGroup1(USHORT BaseAddr,UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT RefreshRateTableIndex);
void SiS_SetGroup1_LVDS(USHORT BaseAddr,UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT RefreshRateTableIndex);
void SiS_SetGroup1_LCDA(USHORT BaseAddr,UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT RefreshRateTableIndex);/*301b*/
void SiS_SetGroup1_301(USHORT BaseAddr,UCHAR *ROMAddr,USHORT ModeNo,USHORT ModeIdIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension,USHORT RefreshRateTableIndex);
#ifdef SIS300
void SiS_SetCRT2FIFO_300(UCHAR *ROMAddr,USHORT ModeNo,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
#endif
#ifdef SIS315H
void SiS_SetCRT2FIFO_310(UCHAR *ROMAddr,USHORT ModeNo,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_CRT2AutoThreshold(USHORT BaseAddr);
#endif
BOOLEAN SiS_GetLCDDDCInfo(PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_UnLockCRT2(PSIS_HW_DEVICE_INFO,USHORT BaseAddr);
void SiS_LockCRT2(PSIS_HW_DEVICE_INFO,USHORT BaseAddr);
void SiS_DisableBridge(PSIS_HW_DEVICE_INFO,USHORT BaseAddr);
void SiS_EnableBridge(PSIS_HW_DEVICE_INFO,USHORT BaseAddr);
void SiS_SetPanelDelay(UCHAR* ROMAddr,PSIS_HW_DEVICE_INFO,USHORT DelayTime);
void SiS_ShortDelay(USHORT delay);
void SiS_LongDelay(USHORT delay);
void SiS_GenericDelay(USHORT delay);
void SiS_VBWait(void);
/* TW: New functions (with temporary names) */
void SiS_Chrontel701xOn(void);
void SiS_Chrontel701xOn2(PSIS_HW_DEVICE_INFO HwDeviceExtension,
USHORT BaseAddr);
void SiS_Chrontel701xOff(void);
void SiS_Chrontel701xOff2(void);
void SiS_ChrontelFlip0x48(void);
void SiS_ChrontelDoSomething4(PSIS_HW_DEVICE_INFO HwDeviceExtension, USHORT BaseAddr);
void SiS_ChrontelDoSomething3(USHORT ModeNo, PSIS_HW_DEVICE_INFO HwDeviceExtension, USHORT BaseAddr);
void SiS_ChrontelDoSomething2(PSIS_HW_DEVICE_INFO HwDeviceExtension, USHORT BaseAddr);
void SiS_ChrontelDoSomething1(PSIS_HW_DEVICE_INFO HwDeviceExtension, USHORT BaseAddr);
BOOLEAN SiS_WeHaveBacklightCtrl(PSIS_HW_DEVICE_INFO HwDeviceExtension, USHORT BaseAddr);
#if 0
BOOLEAN SiS_IsSomethingCR5F(PSIS_HW_DEVICE_INFO HwDeviceExtension, USHORT BaseAddr);
#endif
BOOLEAN SiS_IsYPbPr(PSIS_HW_DEVICE_INFO HwDeviceExtension, USHORT BaseAddr);
BOOLEAN SiS_IsTVOrSomething(PSIS_HW_DEVICE_INFO HwDeviceExtension, USHORT BaseAddr);
BOOLEAN SiS_IsLCDOrLCDA(PSIS_HW_DEVICE_INFO HwDeviceExtension, USHORT BaseAddr);
void SiS_SetCHTVForLCD(PSIS_HW_DEVICE_INFO HwDeviceExtension, USHORT BaseAddr);
void SiS_Chrontel19f2(void);
BOOLEAN SiS_CR36BIOSWord23b(PSIS_HW_DEVICE_INFO HwDeviceExtension);
BOOLEAN SiS_CR36BIOSWord23d(PSIS_HW_DEVICE_INFO HwDeviceExtension);
BOOLEAN SiS_IsSR13_CR30(PSIS_HW_DEVICE_INFO HwDeviceExtension);
USHORT SiS_SetFlag;
USHORT SiS_RVBHCFACT, SiS_RVBHCMAX, SiS_RVBHRS;
USHORT SiS_VGAVT, SiS_VGAHT;
USHORT SiS_VT, SiS_HT;
USHORT SiS_VGAVDE, SiS_VGAHDE;
USHORT SiS_VDE, SiS_HDE;
USHORT SiS_NewFlickerMode, SiS_RY1COE, SiS_RY2COE, SiS_RY3COE, SiS_RY4COE;
USHORT SiS_LCDHDES, SiS_LCDVDES;
USHORT SiS_DDC_Port;
USHORT SiS_DDC_Index;
USHORT SiS_DDC_DataShift;
USHORT SiS_DDC_DeviceAddr;
USHORT SiS_DDC_Flag;
USHORT SiS_DDC_ReadAddr;
USHORT SiS_DDC_Buffer;
extern USHORT SiS_CRT1Mode;
extern USHORT SiS_P3c4, SiS_P3d4;
/*extern USHORT SiS_P3c0,SiS_P3ce,SiS_P3c2;*/
extern USHORT SiS_P3ca;
/*extern USHORT SiS_P3c6,SiS_P3c7,SiS_P3c8;*/
extern USHORT SiS_P3c9;
extern USHORT SiS_P3da;
extern USHORT SiS_Part1Port, SiS_Part2Port;
extern USHORT SiS_Part3Port, SiS_Part4Port, SiS_Part5Port;
extern USHORT SiS_MDA_DAC[];
extern USHORT SiS_CGA_DAC[];
extern USHORT SiS_EGA_DAC[];
extern USHORT SiS_VGA_DAC[];
extern USHORT SiS_ModeType;
extern USHORT SiS_SelectCRT2Rate;
extern USHORT SiS_IF_DEF_LVDS;
extern USHORT SiS_IF_DEF_TRUMPION;
extern USHORT SiS_IF_DEF_CH7005;
extern USHORT SiS_IF_DEF_HiVision;
extern USHORT SiS_IF_DEF_DSTN; /*add for dstn */
extern USHORT SiS_VBInfo;
extern USHORT SiS_VBType; /*301b */
extern USHORT SiS_LCDResInfo;
extern USHORT SiS_LCDTypeInfo;
extern USHORT SiS_LCDInfo;
extern BOOLEAN SiS_SearchVBModeID (ULONG, USHORT);
extern BOOLEAN SiS_Is301B (USHORT BaseAddr); /*301b */
extern BOOLEAN SiS_IsDisableCRT2 (USHORT BaseAddr);
extern BOOLEAN SiS_IsVAMode (USHORT BaseAddr);
extern BOOLEAN SiS_IsDualEdge (USHORT BaseAddr);
/*end 301b*/
void SiS_SetDefCRT2ExtRegs (USHORT BaseAddr);
USHORT SiS_GetRatePtrCRT2 (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex);
BOOLEAN SiS_AjustCRT2Rate (ULONG ROMAddr, USHORT ModeNo, USHORT MODEIdIndex,
USHORT RefreshRateTableIndex, USHORT * i);
void SiS_SaveCRT2Info (USHORT ModeNo);
void SiS_GetCRT2Data (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex,
USHORT RefreshRateTableIndex);
void SiS_GetCRT2DataLVDS (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex,
USHORT RefreshRateTableIndex);
void SiS_GetCRT2PtrA (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex,
USHORT RefreshRateTableIndex, USHORT * CRT2Index, USHORT * ResIndex); /*301b */
void SiS_GetCRT2Data301 (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex,
USHORT RefreshRateTableIndex);
USHORT SiS_GetResInfo (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex);
void SiS_GetCRT2ResInfo (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex);
void SiS_GetRAMDAC2DATA (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex,
USHORT RefreshRateTableIndex);
void SiS_GetCRT2Ptr (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex,
USHORT RefreshRateTableIndex, USHORT * CRT2Index,
USHORT * ResIndex);
void SiS_SetCRT2ModeRegs (USHORT BaseAddr, USHORT ModeNo, PSIS_HW_DEVICE_INFO);
void SiS_GetLVDSDesData (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex,
USHORT RefreshRateTableIndex);
void SiS_SetCRT2Offset (USHORT Part1Port, ULONG ROMAddr, USHORT ModeNo,
USHORT ModeIdIndex, USHORT RefreshRateTableIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
USHORT SiS_GetOffset (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex,
USHORT RefreshRateTableIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
USHORT SiS_GetColorDepth (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex);
USHORT SiS_GetVCLK (ULONG ROMAddr, USHORT ModeNo);
USHORT SiS_GetVCLKPtr (ULONG ROMAddr, USHORT ModeNo);
USHORT SiS_GetColorTh (ULONG ROMAddr);
USHORT SiS_GetMCLK (ULONG ROMAddr);
USHORT SiS_GetMCLKPtr (ULONG ROMAddr);
USHORT SiS_GetDRAMType (ULONG ROMAddr);
USHORT SiS_CalcDelayVB (void);
extern USHORT SiS_GetVCLK2Ptr (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex,
USHORT RefreshRateTableIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetCRT2Sync (USHORT BaseAddr, ULONG ROMAddr, USHORT ModeNo,
USHORT RefreshRateTableIndex);
void SiS_SetRegANDOR (USHORT Port, USHORT Index, USHORT DataAND, USHORT DataOR);
void SiS_SetRegOR (USHORT Port, USHORT Index, USHORT DataOR);
void SiS_SetRegAND (USHORT Port, USHORT Index, USHORT DataAND);
USHORT SiS_GetVGAHT2 (void);
void SiS_SetGroup2 (USHORT BaseAddr, ULONG ROMAddr, USHORT ModeNo,
USHORT ModeIdIndex, USHORT RefreshRateTableIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetGroup3 (USHORT BaseAddr, ULONG ROMAddr, USHORT ModeNo,
USHORT ModeIdIndex, PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetGroup4 (USHORT BaseAddr, ULONG ROMAddr, USHORT ModeNo,
USHORT ModeIdIndex, USHORT RefreshRateTableIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetGroup5 (USHORT BaseAddr, ULONG ROMAddr, USHORT ModeNo,
USHORT ModeIdIndex);
void SiS_SetCRT2VCLK (USHORT BaseAddr, ULONG ROMAddr, USHORT ModeNo,
USHORT ModeIdIndex, USHORT RefreshRateTableIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_EnableCRT2 (void);
void SiS_LoadDAC2 (ULONG ROMAddr, USHORT Part5Port, USHORT ModeNo,
USHORT ModeIdIndex);
void SiS_WriteDAC2 (USHORT Pdata, USHORT dl, USHORT ah, USHORT al, USHORT dh);
void SiS_GetVBInfo301 (USHORT BaseAddr, ULONG ROMAddr, USHORT ModeNo,
USHORT ModeIdIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
BOOLEAN SiS_GetLCDResInfo (ULONG ROMAddr, USHORT P3d4, USHORT ModeNo,
USHORT ModeIdIndex);
BOOLEAN SiS_BridgeIsOn (USHORT BaseAddr);
BOOLEAN SiS_BridgeIsEnable (USHORT BaseAddr, PSIS_HW_DEVICE_INFO);
BOOLEAN SiS_BridgeInSlave (void);
/*void SiS_PresetScratchregister(USHORT P3d4);*/
void SiS_PresetScratchregister (USHORT SiS_P3d4,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetTVSystem (VOID);
void SiS_LongWait (VOID);
USHORT SiS_GetQueueConfig (VOID);
void SiS_VBLongWait (VOID);
USHORT SiS_GetVCLKLen (ULONG ROMAddr);
BOOLEAN SiS_WaitVBRetrace (USHORT BaseAddr);
void SiS_SetCRT2ECLK (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex,
USHORT RefreshRateTableIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_GetLVDSDesPtr (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex,
USHORT RefreshRateTableIndex, USHORT * PanelIndex,
USHORT * ResIndex);
void SiS_GetLVDSDesPtrA (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex,
USHORT RefreshRateTableIndex, USHORT * PanelIndex,
USHORT * ResIndex); /*301b */
void SiS_SetTPData (VOID);
void SiS_ModCRT1CRTC (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex,
USHORT RefreshRateTableIndex);
extern BOOLEAN SiS_GetLVDSCRT1Ptr (ULONG ROMAddr, USHORT ModeNo,
USHORT ModeIdIndex,
USHORT RefreshRateTableIndex,
USHORT * ResInfo, USHORT * DisplayType);
void SiS_SetCHTVReg (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex,
USHORT RefreshRateTableIndex);
void SiS_SetCHTVRegANDOR (USHORT tempax, USHORT tempbh);
void SiS_GetCHTVRegPtr (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex,
USHORT RefreshRateTableIndex);
void SiS_SetCH7005 (USHORT tempax);
USHORT SiS_GetCH7005 (USHORT tempax);
void SiS_SetSwitchDDC2 (void);
void SiS_SetStart (void);
void SiS_SetStop (void);
void SiS_DDC2Delay (void);
void SiS_SetSCLKLow (void);
void SiS_SetSCLKHigh (void);
USHORT SiS_ReadDDC2Data (USHORT tempax);
USHORT SiS_WriteDDC2Data (USHORT tempax);
USHORT SiS_CheckACK (void);
void SiS_OEM310Setting (PSIS_HW_DEVICE_INFO HwDeviceExtension, USHORT BaseAddr,
ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex);
void SiS_OEM300Setting (PSIS_HW_DEVICE_INFO HwDeviceExtension, USHORT BaseAddr,
ULONG ROMAddr, USHORT ModeNo);
USHORT GetRevisionID (PSIS_HW_DEVICE_INFO HwDeviceExtension);
extern void SiS_SetReg1 (USHORT, USHORT, USHORT);
extern void SiS_SetReg3 (USHORT, USHORT);
extern UCHAR SiS_GetReg1 (USHORT, USHORT);
extern UCHAR SiS_GetReg2 (USHORT);
extern BOOLEAN SiS_SearchModeID (ULONG ROMAddr, USHORT ModeNo,
USHORT * ModeIdIndex);
extern BOOLEAN SiS_GetRatePtr (ULONG, USHORT);
extern void SiS_SetReg4 (USHORT, ULONG);
extern ULONG SiS_GetReg3 (USHORT);
extern void SiS_DisplayOff (void);
extern void SiS_CRT2AutoThreshold (USHORT BaseAddr);
extern void SiS_DisplayOn (void);
extern UCHAR SiS_GetModePtr (ULONG ROMAddr, USHORT ModeNo, USHORT ModeIdIndex);
extern UCHAR SiS_Get310DRAMType (ULONG ROMAddr);
BOOLEAN SiS_SetCRT2Group301 (USHORT BaseAddr, ULONG ROMAddr, USHORT ModeNo,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetGroup1 (USHORT BaseAddr, ULONG ROMAddr, USHORT ModeNo,
USHORT ModeIdIndex, PSIS_HW_DEVICE_INFO HwDeviceExtension,
USHORT RefreshRateTableIndex);
void SiS_SetGroup1_LVDS (USHORT BaseAddr, ULONG ROMAddr, USHORT ModeNo,
USHORT ModeIdIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension,
USHORT RefreshRateTableIndex);
void SiS_SetGroup1_LCDA (USHORT BaseAddr, ULONG ROMAddr, USHORT ModeNo,
USHORT ModeIdIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension, USHORT RefreshRateTableIndex); /*301b */
void SiS_SetGroup1_301 (USHORT BaseAddr, ULONG ROMAddr, USHORT ModeNo,
USHORT ModeIdIndex,
PSIS_HW_DEVICE_INFO HwDeviceExtension,
USHORT RefreshRateTableIndex);
void SiS_SetCRT2FIFO (USHORT Part1Port, ULONG ROMAddr, USHORT ModeNo,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_SetCRT2FIFO2 (USHORT Part1Port, ULONG ROMAddr, USHORT ModeNo,
PSIS_HW_DEVICE_INFO HwDeviceExtension);
BOOLEAN SiS_GetLCDDDCInfo (PSIS_HW_DEVICE_INFO HwDeviceExtension);
void SiS_UnLockCRT2 (PSIS_HW_DEVICE_INFO, USHORT BaseAddr);
void SiS_LockCRT2 (PSIS_HW_DEVICE_INFO, USHORT BaseAddr);
void SiS_DisableBridge (PSIS_HW_DEVICE_INFO, USHORT BaseAddr);
void SiS_EnableBridge (PSIS_HW_DEVICE_INFO, USHORT BaseAddr);
void SiS_SetPanelDelay (USHORT DelayTime);
void SiS_LCD_Wait_Time (UCHAR DelayTime);
/* TW end */
#endif
drivers/video/sis/initdef.h
View file @ 4ec16d90
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/sis/initdef.h,v 1.4 2000/12/02 01:16:17 dawes Exp $ */
#ifndef _INITDEF_
#define _INITDEF_
......@@ -6,18 +8,21 @@
#define SiS540 0x5300
#define SiS630 0x6300
#define SiS730 0x6300
#define VB_SIS301 0x0001 /*301b */
#define VB_SIS301B 0x0002
#define VB_SIS302B 0x0004
#define VB_NoLCD 0x8000
/*end 301b*/
/* SiS_VBType */
#define VB_SIS301 0x0001
#define VB_SIS301B 0x0002
#define VB_SIS302B 0x0004
#define VB_SIS301LV 0x0008
#define VB_SIS302LV 0x0010
#define VB_NoLCD 0x8000
#define VB_SIS301BLV302BLV (VB_SIS301B|VB_SIS302B|VB_SIS301LV|VB_SIS302LV)
#define CRT1Len 17
#define LVDSCRT1Len 15
#define CHTVRegDataLen 5
#define ModeInfoFlag 0x07
#define IsTextMode 0x07
/* SiS_ModeType */
#define ModeText 0x00
#define ModeCGA 0x01
#define ModeEGA 0x02
......@@ -27,10 +32,14 @@
#define Mode24Bpp 0x06
#define Mode32Bpp 0x07
#define ModeInfoFlag 0x07
#define IsTextMode 0x07
#define DACInfoFlag 0x18
#define MemoryInfoFlag 0x1E0
#define MemorySizeShift 0x05
/* modeflag */
#define Charx8Dot 0x0200
#define LineCompareOff 0x0400
#define CRT2Mode 0x0800
......@@ -38,16 +47,17 @@
#define NoSupportSimuTV 0x2000
#define DoubleScanMode 0x8000
/* Infoflag */
#define SupportAllCRT2 0x0078
#define SupportTV 0x0008
#define SupportHiVisionTV 0x0010
#define SupportLCD 0x0020
#define SupportRAMDAC2 0x0040
#define SupportRAMDAC2 0x0040
#define NoSupportTV 0x0070
#define NoSupportHiVisionTV 0x0060
#define NoSupportLCD 0x0058
#define SupportCHTV 0x0800
#define SupportTV1024 0x0800 /*301b */
#define SupportTV1024 0x0800 /*301b*/
#define InterlaceMode 0x0080
#define SyncPP 0x0000
#define SyncPN 0x4000
......@@ -59,7 +69,8 @@
#define ECLKindex3 0x0300
#define ECLKindex4 0x0400
#define SetSimuScanMode 0x0001
/* VBInfo */
#define SetSimuScanMode 0x0001 /* CR 30 */
#define SwitchToCRT2 0x0002
#define SetCRT2ToTV 0x009C
#define SetCRT2ToAVIDEO 0x0004
......@@ -68,30 +79,93 @@
#define SetCRT2ToLCD 0x0020
#define SetCRT2ToRAMDAC 0x0040
#define SetCRT2ToHiVisionTV 0x0080
#define SetNTSCTV 0x0000
#define SetNTSCTV 0x0000 /* CR 31 */
#define SetPALTV 0x0100
#define SetInSlaveMode 0x0200
#define SetNotSimuMode 0x0400
#define SetNotSimuTVMode 0x0400
#define SetDispDevSwitch 0x0800
#define LoadDACFlag 0x1000
#define SetCHTVOverScan 0x1000 /* TW: Re-defined (from 0x8000) */
#define DisableCRT2Display 0x2000
#define CRT2DisplayFlag 0x2000
#define DriverMode 0x4000
#define HotKeySwitch 0x8000
#define SetCHTVOverScan 0x8000
#define SetCRT2ToLCDA 0x8000 /*301b */
#define HotKeySwitch 0x8000 /* TW: ? */
#define SetCRT2ToLCDA 0x8000
#define PanelRGB18Bit 0x0100
#define PanelRGB24Bit 0x0000
#define TVOverScan 0x10
#define TVOverScan 0x10 /* Bit in CR35 (300 series only) */
#define TVOverScanShift 4
#define ClearBufferFlag 0x20
#define EnableDualEdge 0x01 /*301b */
#define SetToLCDA 0x02
/* CR32 (Newer 630, and 310/325 series)
[0] VB connected with CVBS
[1] VB connected with SVHS
[2] VB connected with SCART
[3] VB connected with LCD
[4] VB connected with CRT2 (secondary VGA)
[5] CRT1 monitor is connected
[6] VB connected with Hi-Vision TV
[7] VB connected with DVI combo connector
CR37
[0] Set 24/18 bit (0/1) RGB to LVDS/TMDS transmitter (set by BIOS)
[3:1] External chip
300 series:
001 SiS301 (never seen)
010 LVDS
011 LVDS + Tumpion Zurac
100 LVDS + Chrontel 7005
110 Chrontel 7005
310/325 series
001 SiS30x (never seen)
010 LVDS
011 LVDS + Chrontel 7019
All other combinations reserved
[4] LVDS: Expanding(0)/Non-expanding(1) LCD display
30x: SiS30x(0)/LCD monitor(1) scaling display
[5] LCD polarity select
0: VESA DMT Standard
1: EDID 2.x defined
[6] LCD honrizontal polarity select
0: High active
1: Low active
[7] LCD vertical polarity select
0: High active
1: Low active
*/
#define EnableDualEdge 0x01 /* CR38 (310/325 series) */
/* #define PAL_NTSC 0x01 (only on 315PRO) */
#define SetToLCDA 0x02 /* TW: LCD channel A (302 only) */
#define SetYPbPr 0x10 /* TW: ? */
#define EnablePALMN 0x40
#define EnablePALN 0x80
/* CR79 (310/325 series only)
[3-0] Notify driver
0001 Mode Switch event (set by BIOS)
0010 Epansion On/Off event
0011 TV UnderScan/OverScan event
0100 Set Brightness event
0101 Set Contrast event
0110 Set Mute event
0111 Set Volume Up/Down event
[4] Enable Backlight Control by BIOS/driver (set by driver)
[5] PAL/NTSC (set by BIOS)
[6] Expansion On/Off (set by BIOS)
[7] TV UnderScan/OverScan (set by BIOS)
*/
#define SetSCARTOutput 0x01
#define BoardTVType 0x02
#define EnablePALMN 0x40
/* SetFlag */
#define ProgrammingCRT2 0x01
#define TVSimuMode 0x02
#define RPLLDIV2XO 0x04
......@@ -100,35 +174,57 @@
#define SetDispDevSwitchFlag 0x20
#define CheckWinDos 0x40
#define SetJDOSMode 0x80
#define CRT2IsVGA 0x80 /* TW: Not sure about this name... */
/* LCDResInfo */
#define Panel300_800x600 0x01 /* CR36 */
#define Panel300_1024x768 0x02
#define Panel300_1280x1024 0x03
#define Panel300_1280x960 0x04
#define Panel300_640x480 0x05
#define Panel300_1024x600 0x06
#define Panel300_1152x768 0x07
/* #define Panel300_1600x1200 0x06 OLD */
#define Panel300_320x480 0x08 /* fstn - TW: This is fake, can be any */
#define Panel310_800x600 0x01
#define Panel310_1024x768 0x02
#define Panel310_1280x1024 0x03
#define Panel310_640x480 0x04
#define Panel310_1024x600 0x05
#define Panel310_1152x864 0x06
#define Panel310_1280x960 0x07
#define Panel310_1152x768 0x08
#define Panel310_1400x1050 0x09
#define Panel310_1280x768 0x0a
#define Panel310_1600x1200 0x0b
#define Panel310_320x480 0x0c /* fstn - TW: This is fake, can be any */
#define Panel800x600 0x01
#define Panel1024x768 0x02
#define Panel1280x1024 0x03
#define Panel1280x960 0x04
#define Panel640x480 0x05
#define Panel1600x1200 0x06 /*301b */
#define LCDRGB18Bit 0x01
#define ExtChipType 0x0e
#define ExtChip301 0x02
#define ExtChipLVDS 0x04
#define ExtChipTrumpion 0x06
#define ExtChipCH7005 0x08
#define ExtChipMitacTV 0x0a
#define ExtChipMitacTV 0x0a /* TW: Incorrect, 0x0a = Chrontel 7005 only */
#define IsM650 0x80 /* TW: CR5F */
/* LCDInfo */
#define LCDRGB18Bit 0x01
#define LCDNonExpandingShift 0x04
#define LCDNonExpanding 0x10
#define LCDNonExpandingShift 4
#define LCDSync 0x20
/* TW: What is.. */ /* 0x100 */
#define LCDSyncBit 0xe0
#define LCDSyncShift 6
#define DDC2DelayTime 300
#define CRT2DisplayFlag 0x2000
#define LCDDataLen 8
#define HiTVDataLen 12
#define TVDataLen 16
#define SetPALTV 0x0100
#define HalfDCLK 0x1000
#define HalfDCLK 0x1000 /* modeflag */
#define NTSCHT 1716
#define NTSC2HT 1920
#define NTSCVT 525
#define PALHT 1728
#define PALVT 625
......@@ -141,25 +237,23 @@
#define VCLKStartFreq 25
#define SoftDramType 0x80
#define VCLK40 0x04
#define VCLK65 0x09
#define VCLK108_2 0x14
#define LCDRGB18Bit 0x01
#define VCLK40 0x04 /* Index in VCLKData array */
#define VCLK65 0x09 /* Index in VCLKData array */
#define VCLK108_2 0x14 /* Index in VCLKData array */
#define TVVCLKDIV2 0x21 /* Indices in (VB)VCLKData arrays */
#define TVVCLK 0x22
#define HiTVVCLKDIV2 0x23
#define HiTVVCLK 0x24
#define HiTVSimuVCLK 0x25
#define HiTVTextVCLK 0x26
#define LoadDACFlag 0x1000
#define AfterLockCRT2 0x4000
#define SetCRT2ToAVIDEO 0x0004
#define SetCRT2ToSCART 0x0010
#define Ext2StructSize 5
#define TVVCLKDIV2 0x021
#define TVVCLK 0x022
#define HiTVVCLKDIV2 0x023
#define HiTVVCLK 0x024
#define HiTVSimuVCLK 0x025
#define HiTVTextVCLK 0x026
#define SwitchToCRT2 0x0002
#define LCDVESATiming 0x08
#define SetSCARTOutput 0x01
#define AVIDEOSense 0x01
#define SVIDEOSense 0x02
......@@ -172,14 +266,13 @@
#define HotPlugFunction 0x08
#define StStructSize 0x06
#define SIS_CRT2_PORT_04 0x04 - 0x030
#define SIS_CRT2_PORT_04 0x04 - 0x30
#define SIS_CRT2_PORT_10 0x10 - 0x30
#define SIS_CRT2_PORT_12 0x12 - 0x30
#define SIS_CRT2_PORT_14 0x14 - 0x30
#define LCDNonExpanding 0x10
#define ADR_CRT2PtrData 0x20E
#define offset_Zurac 0x210
#define offset_Zurac 0x210 /* TW: Trumpion Zurac data pointer */
#define ADR_LVDSDesPtrData 0x212
#define ADR_LVDSCRT1DataPtr 0x214
#define ADR_CHTVVCLKPtr 0x216
......@@ -198,26 +291,26 @@
#define ModeSettingAddr 0x53
#define SelectCRT1Rate 0x4
#define _PanelType00 0x00
#define _PanelType01 0x08
#define _PanelType02 0x10
#define _PanelType03 0x18
#define _PanelType04 0x20
#define _PanelType05 0x28
#define _PanelType06 0x30
#define _PanelType07 0x38
#define _PanelType08 0x40
#define _PanelType09 0x48
#define _PanelType0A 0x50
#define _PanelType0B 0x58
#define _PanelType0C 0x60
#define _PanelType0D 0x68
#define _PanelType0E 0x70
#define _PanelType0F 0x78
#define _PanelType00 0x00
#define _PanelType01 0x08
#define _PanelType02 0x10
#define _PanelType03 0x18
#define _PanelType04 0x20
#define _PanelType05 0x28
#define _PanelType06 0x30
#define _PanelType07 0x38
#define _PanelType08 0x40
#define _PanelType09 0x48
#define _PanelType0A 0x50
#define _PanelType0B 0x58
#define _PanelType0C 0x60
#define _PanelType0D 0x68
#define _PanelType0E 0x70
#define _PanelType0F 0x78
#define PRIMARY_VGA 0 /* 1: SiS is primary vga 0:SiS is secondary vga */
#define BIOSIDCodeAddr 0x235
#define PRIMARY_VGA 0 /* 1: SiS is primary vga 0:SiS is secondary vga */
#define BIOSIDCodeAddr 0x235 /* TW: Offsets to ptrs in BIOS image */
#define OEMUtilIDCodeAddr 0x237
#define VBModeIDTableAddr 0x239
#define OEMTVPtrAddr 0x241
......@@ -258,55 +351,57 @@
#define OEMLCDPanelIDSupport 0x0080
/* =============================================================
for 310
============================================================== */
#define SoftDRAMType 0x80
#define SoftSetting_OFFSET 0x52
#define SR07_OFFSET 0x7C
#define SR15_OFFSET 0x7D
#define SR16_OFFSET 0x81
#define SR17_OFFSET 0x85
#define SR19_OFFSET 0x8D
#define SR1F_OFFSET 0x99
#define SR21_OFFSET 0x9A
#define SR22_OFFSET 0x9B
#define SR23_OFFSET 0x9C
#define SR24_OFFSET 0x9D
#define SR25_OFFSET 0x9E
#define SR31_OFFSET 0x9F
#define SR32_OFFSET 0xA0
#define SR33_OFFSET 0xA1
#define CR40_OFFSET 0xA2
#define SR25_1_OFFSET 0xF6
#define CR49_OFFSET 0xF7
#define VB310Data_1_2_Offset 0xB6
#define VB310Data_4_D_Offset 0xB7
#define VB310Data_4_E_Offset 0xB8
#define VB310Data_4_10_Offset 0xBB
#define RGBSenseDataOffset 0xBD
#define YCSenseDataOffset 0xBF
#define VideoSenseDataOffset 0xC1
#define OutputSelectOffset 0xF3
#define ECLK_MCLK_DISTANCE 0x14
#define VBIOSTablePointerStart 0x100
#define StandTablePtrOffset VBIOSTablePointerStart+0x02
#define EModeIDTablePtrOffset VBIOSTablePointerStart+0x04
#define CRT1TablePtrOffset VBIOSTablePointerStart+0x06
#define ScreenOffsetPtrOffset VBIOSTablePointerStart+0x08
#define VCLKDataPtrOffset VBIOSTablePointerStart+0x0A
#define MCLKDataPtrOffset VBIOSTablePointerStart+0x0E
#define CRT2PtrDataPtrOffset VBIOSTablePointerStart+0x10
#define TVAntiFlickPtrOffset VBIOSTablePointerStart+0x12
#define TVDelayPtr1Offset VBIOSTablePointerStart+0x14
#define TVPhaseIncrPtr1Offset VBIOSTablePointerStart+0x16
#define TVYFilterPtr1Offset VBIOSTablePointerStart+0x18
#define LCDDelayPtr1Offset VBIOSTablePointerStart+0x20
#define TVEdgePtr1Offset VBIOSTablePointerStart+0x24
#define CRT2Delay1Offset VBIOSTablePointerStart+0x28
/*
=============================================================
for 310/325 series
=============================================================
*/
#define SoftDRAMType 0x80
#define SoftSetting_OFFSET 0x52
#define SR07_OFFSET 0x7C
#define SR15_OFFSET 0x7D
#define SR16_OFFSET 0x81
#define SR17_OFFSET 0x85
#define SR19_OFFSET 0x8D
#define SR1F_OFFSET 0x99
#define SR21_OFFSET 0x9A
#define SR22_OFFSET 0x9B
#define SR23_OFFSET 0x9C
#define SR24_OFFSET 0x9D
#define SR25_OFFSET 0x9E
#define SR31_OFFSET 0x9F
#define SR32_OFFSET 0xA0
#define SR33_OFFSET 0xA1
#define CR40_OFFSET 0xA2
#define SR25_1_OFFSET 0xF6
#define CR49_OFFSET 0xF7
#define VB310Data_1_2_Offset 0xB6
#define VB310Data_4_D_Offset 0xB7
#define VB310Data_4_E_Offset 0xB8
#define VB310Data_4_10_Offset 0xBB
#define RGBSenseDataOffset 0xBD
#define YCSenseDataOffset 0xBF
#define VideoSenseDataOffset 0xC1
#define OutputSelectOffset 0xF3
#define ECLK_MCLK_DISTANCE 0x14
#define VBIOSTablePointerStart 0x100
#define StandTablePtrOffset VBIOSTablePointerStart+0x02
#define EModeIDTablePtrOffset VBIOSTablePointerStart+0x04
#define CRT1TablePtrOffset VBIOSTablePointerStart+0x06
#define ScreenOffsetPtrOffset VBIOSTablePointerStart+0x08
#define VCLKDataPtrOffset VBIOSTablePointerStart+0x0A
#define MCLKDataPtrOffset VBIOSTablePointerStart+0x0E
#define CRT2PtrDataPtrOffset VBIOSTablePointerStart+0x10
#define TVAntiFlickPtrOffset VBIOSTablePointerStart+0x12
#define TVDelayPtr1Offset VBIOSTablePointerStart+0x14
#define TVPhaseIncrPtr1Offset VBIOSTablePointerStart+0x16
#define TVYFilterPtr1Offset VBIOSTablePointerStart+0x18
#define LCDDelayPtr1Offset VBIOSTablePointerStart+0x20
#define TVEdgePtr1Offset VBIOSTablePointerStart+0x24
#define CRT2Delay1Offset VBIOSTablePointerStart+0x28
#endif
drivers/video/sis/oem300.h
View file @ 4ec16d90
UCHAR SiS300_TVEdge1[3][2] = {
{0x0, 0x4},
{0x0, 0x4},
{0x0, 0x0}
};
UCHAR SiS300_OEMTVDelay[8][4] = {
{0x08, 0x08, 0x08, 0x08},
{0x08, 0x08, 0x08, 0x08},
{0x08, 0x08, 0x08, 0x08},
{0x2c, 0x2c, 0x2c, 0x2c},
{0x08, 0x08, 0x08, 0x08},
{0x08, 0x08, 0x08, 0x08},
{0x08, 0x08, 0x08, 0x08},
{0x20, 0x20, 0x20, 0x20}
};
UCHAR SiS300_OEMTVFlicker[8][4] = {
{0x00, 0x00, 0x00, 0x00},
{0x00, 0x00, 0x00, 0x00},
{0x00, 0x00, 0x00, 0x00},
{0x00, 0x00, 0x00, 0x00},
{0x00, 0x00, 0x00, 0x00},
{0x00, 0x00, 0x00, 0x00},
{0x00, 0x00, 0x00, 0x00},
{0x00, 0x00, 0x00, 0x00}
};
UCHAR SiS300_OEMLCDDelay1[12][4] = {
{0x2c, 0x2c, 0x2c, 0x2c},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x2c, 0x2c, 0x2c, 0x2c},
{0x2c, 0x2c, 0x2c, 0x2c},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x24, 0x24, 0x24, 0x24},
{0x24, 0x24, 0x24, 0x24},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x24, 0x24, 0x24, 0x24}
};
UCHAR SiS300_OEMLCDDelay2[32][4] = {
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20},
{0x20, 0x20, 0x20, 0x20}
};
UCHAR SiS300_StNTSCPhase[6][4] = {
{0x21, 0xed, 0x00, 0x08},
{0x21, 0xed, 0x8a, 0x08},
{0x21, 0xed, 0x8a, 0x08},
{0x21, 0xed, 0x8a, 0x08},
{0x21, 0xed, 0x8a, 0x08},
{0xff, 0xff, 0xff, 0xff}
};
UCHAR SiS300_StPALPhase[6][4] = {
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0xff, 0xff, 0xff, 0xff}
};
UCHAR SiS300_StSCARTPhase[6][4] = {
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0xff, 0xff, 0xff, 0xff}
};
UCHAR SiS300_StHiTVPhase[6][4] = {
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0xff, 0xff, 0xff, 0xff}
};
UCHAR SiS300_ExtNTSCPhase[6][4] = {
{0x21, 0xed, 0x00, 0x08},
{0x21, 0xed, 0x8a, 0x08},
{0x21, 0xed, 0x8a, 0x08},
{0x21, 0xed, 0x8a, 0x08},
{0x21, 0xed, 0x8a, 0x08},
{0xff, 0xff, 0xff, 0xff}
};
UCHAR SiS300_ExtPALPhase[6][4] = {
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0xff, 0xff, 0xff, 0xff}
};
UCHAR SiS300_ExtSCARTPhase[6][4] = {
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0xff, 0xff, 0xff, 0xff}
};
/* OEM Data for 300 series */
UCHAR SiS300_ExtHiTVPhase[6][4] = {
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0x2a, 0x05, 0xd3, 0x00},
{0xff, 0xff, 0xff, 0xff}
UCHAR SiS300_OEMTVDelay301[8][4] =
{
{0x08,0x08,0x08,0x08},
{0x08,0x08,0x08,0x08},
{0x08,0x08,0x08,0x08},
{0x2c,0x2c,0x2c,0x2c},
{0x08,0x08,0x08,0x08},
{0x08,0x08,0x08,0x08},
{0x08,0x08,0x08,0x08},
{0x20,0x20,0x20,0x20}
};
UCHAR SiS300_StNTSCFilter[17][4] = {
{0x00, 0xf4, 0x10, 0x38},
{0x00, 0xf4, 0x10, 0x38},
{0xeb, 0x04, 0x10, 0x18},
{0xf7, 0x06, 0x19, 0x14},
{0x00, 0xf4, 0x10, 0x38},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x15, 0x25, 0xf6},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xff, 0xff, 0xff, 0xff}
UCHAR SiS300_OEMTVDelayLVDS[8][4] =
{
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20}
};
UCHAR SiS300_StPALFilter[17][4] = {
{0x00, 0xf4, 0x10, 0x38},
{0x00, 0xf4, 0x10, 0x38},
{0xf1, 0xf7, 0x10, 0x32},
{0xf3, 0x00, 0x1d, 0x20},
{0x00, 0xf4, 0x10, 0x38},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xfc, 0xfb, 0x14, 0x2a},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xff, 0xff, 0xff, 0xff}
UCHAR SiS300_OEMTVFlicker[8][4] =
{
{0x00,0x00,0x00,0x00},
{0x00,0x00,0x00,0x00},
{0x00,0x00,0x00,0x00},
{0x00,0x00,0x00,0x00},
{0x00,0x00,0x00,0x00},
{0x00,0x00,0x00,0x00},
{0x00,0x00,0x00,0x00},
{0x00,0x00,0x00,0x00}
};
UCHAR SiS300_StSCARTFilter[17][4] = {
{0x00, 0xf4, 0x10, 0x38},
{0x00, 0xf4, 0x10, 0x38},
{0xf1, 0xf7, 0x10, 0x32},
{0xf3, 0x00, 0x1d, 0x20},
{0x00, 0xf4, 0x10, 0x38},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xfc, 0xfb, 0x14, 0x2a},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xff, 0xff, 0xff, 0xff}
#if 0 /* TW: Not used */
UCHAR SiS300_OEMLCDDelay1[12][4]={
{0x2c,0x2c,0x2c,0x2c},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x2c,0x2c,0x2c,0x2c},
{0x2c,0x2c,0x2c,0x2c},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x24,0x24,0x24,0x24},
{0x24,0x24,0x24,0x24},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x24,0x24,0x24,0x24}
};
#endif
UCHAR SiS300_StHiTVFilter[17][4] = {
{0x00, 0xf4, 0x10, 0x38},
{0x00, 0xf4, 0x10, 0x38},
{0xf1, 0xf7, 0x10, 0x32},
{0xf3, 0x00, 0x1d, 0x20},
{0x00, 0xf4, 0x10, 0x38},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xfc, 0xfb, 0x14, 0x2a},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xff, 0xff, 0xff, 0xff}
/* TW: From 630/301B BIOS */
UCHAR SiS300_OEMLCDDelay2[64][4] = /* for 301/301b/302b/301LV/302LV */
{
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20}
};
UCHAR SiS300_ExtNTSCFilter[17][4] = {
{0x00, 0xf4, 0x10, 0x38},
{0x00, 0xf4, 0x10, 0x38},
{0xeb, 0x04, 0x10, 0x18},
{0xf7, 0x06, 0x19, 0x14},
{0x00, 0xf4, 0x10, 0x38},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x15, 0x25, 0xf6},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xff, 0xff, 0xff, 0xff}
/* TW: Added for LVDS */
UCHAR SiS300_OEMLCDDelay3[32][4] = { /* For LVDS */
{0x20,0x20,0x20,0x20}, /* --- Expanding panels */
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x04,0x04,0x04,0x04}, /* Clevo 2202 (PanelType 12); Mitac needs 0x20! */
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20}, /* Uniwill N241S2 (PanelType 14)*/
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20}, /* ---- NonExpanding panels */
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x04,0x04,0x04,0x04}, /* Gericom 2200C (PanelType 28) */
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20},
{0x20,0x20,0x20,0x20}
};
UCHAR SiS300_ExtPALFilter[17][4] = {
{0x00, 0xf4, 0x10, 0x38},
{0x00, 0xf4, 0x10, 0x38},
{0xf1, 0xf7, 0x10, 0x32},
{0xf3, 0x00, 0x1d, 0x20},
{0x00, 0xf4, 0x10, 0x38},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xfc, 0xfb, 0x14, 0x2a},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xff, 0xff, 0xff, 0xff}
UCHAR SiS300_Phase1[8][6][4] =
{
{
{0x21,0xed,0x00,0x08},
{0x21,0xed,0x8a,0x08},
{0x21,0xed,0x8a,0x08},
{0x21,0xed,0x8a,0x08},
{0x21,0xed,0x8a,0x08},
{0xff,0xff,0xff,0xff}
},
{
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0xff,0xff,0xff,0xff}
},
{
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0xff,0xff,0xff,0xff}
},
{
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0xff,0xff,0xff,0xff}
},
{
{0x21,0xed,0x00,0x08},
{0x21,0xed,0x8a,0x08},
{0x21,0xed,0x8a,0x08},
{0x21,0xed,0x8a,0x08},
{0x21,0xed,0x8a,0x08},
{0xff,0xff,0xff,0xff}
},
{
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0xff,0xff,0xff,0xff}
},
{
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0xff,0xff,0xff,0xff}
},
{
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0xff,0xff,0xff,0xff}
}
};
UCHAR SiS300_ExtSCARTFilter[17][4] = {
{0x00, 0xf4, 0x10, 0x38},
{0x00, 0xf4, 0x10, 0x38},
{0xf1, 0xf7, 0x10, 0x32},
{0xf3, 0x00, 0x1d, 0x20},
{0x00, 0xf4, 0x10, 0x38},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xfc, 0xfb, 0x14, 0x2a},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xff, 0xff, 0xff, 0xff}
};
UCHAR SiS300_ExtHiTVFilter[17][4] = {
{0x00, 0xf4, 0x10, 0x38},
{0x00, 0xf4, 0x10, 0x38},
{0xf1, 0xf7, 0x10, 0x32},
{0xf3, 0x00, 0x1d, 0x20},
{0x00, 0xf4, 0x10, 0x38},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xfc, 0xfb, 0x14, 0x2a},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf1, 0xf7, 0x1f, 0x32},
{0xff, 0xff, 0xff, 0xff}
UCHAR SiS300_Phase2[8][6][4] =
{
{
{0x21,0xed,0x00,0x08},
{0x21,0xed,0x8a,0x08},
{0x21,0xed,0x8a,0x08},
{0x21,0xed,0x8a,0x08},
{0x21,0xed,0x8a,0x08},
{0xff,0xff,0xff,0xff}
},
{
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0xff,0xff,0xff,0xff}
},
{
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0xff,0xff,0xff,0xff}
},
{
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0xff,0xff,0xff,0xff}
},
{
{0x21,0xed,0x00,0x08},
{0x21,0xed,0x8a,0x08},
{0x21,0xed,0x8a,0x08},
{0x21,0xed,0x8a,0x08},
{0x21,0xed,0x8a,0x08},
{0xff,0xff,0xff,0xff}
},
{
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0xff,0xff,0xff,0xff}
},
{
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0xff,0xff,0xff,0xff}
},
{
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00},
{0xff,0xff,0xff,0xff}
}
};
UCHAR SiS300_NTSCFilter2[9][7] = {
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0x01, 0x01, 0xFC, 0xF8, 0x08, 0x26, 0x38},
{0xFF, 0xFF, 0xFC, 0x00, 0x0F, 0x22, 0x28}
UCHAR SiS300_Filter1[10][17][4] =
{
{
{0x00,0xf4,0x10,0x38},
{0x00,0xf4,0x10,0x38},
{0xeb,0x04,0x10,0x18},
{0xf7,0x06,0x19,0x14},
{0x00,0xf4,0x10,0x38},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x15,0x25,0xf6},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xff,0xff,0xff,0xff}
},
{
{0x00,0xf4,0x10,0x38},
{0x00,0xf4,0x10,0x38},
{0xf1,0xf7,0x10,0x32},
{0xf3,0x00,0x1d,0x20},
{0x00,0xf4,0x10,0x38},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xfc,0xfb,0x14,0x2a},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xff,0xff,0xff,0xff}
},
{
{0x00,0xf4,0x10,0x38},
{0x00,0xf4,0x10,0x38},
{0xf1,0xf7,0x10,0x32},
{0xf3,0x00,0x1d,0x20},
{0x00,0xf4,0x10,0x38},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xfc,0xfb,0x14,0x2a},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xff,0xff,0xff,0xff}
},
{
{0x00,0xf4,0x10,0x38},
{0x00,0xf4,0x10,0x38},
{0xf1,0xf7,0x10,0x32},
{0xf3,0x00,0x1d,0x20},
{0x00,0xf4,0x10,0x38},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xfc,0xfb,0x14,0x2a},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xff,0xff,0xff,0xff}
},
{
{0x00,0xf4,0x10,0x38},
{0x00,0xf4,0x10,0x38},
{0xeb,0x04,0x10,0x18},
{0xf7,0x06,0x19,0x14},
{0x00,0xf4,0x10,0x38},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x15,0x25,0xf6},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xff,0xff,0xff,0xff}
},
{
{0x00,0xf4,0x10,0x38},
{0x00,0xf4,0x10,0x38},
{0xf1,0xf7,0x10,0x32},
{0xf3,0x00,0x1d,0x20},
{0x00,0xf4,0x10,0x38},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xfc,0xfb,0x14,0x2a},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xff,0xff,0xff,0xff}
},
{
{0x00,0xf4,0x10,0x38},
{0x00,0xf4,0x10,0x38},
{0xf1,0xf7,0x10,0x32},
{0xf3,0x00,0x1d,0x20},
{0x00,0xf4,0x10,0x38},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xfc,0xfb,0x14,0x2a},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xff,0xff,0xff,0xff}
},
{
{0x00,0xf4,0x10,0x38},
{0x00,0xf4,0x10,0x38},
{0xf1,0xf7,0x10,0x32},
{0xf3,0x00,0x1d,0x20},
{0x00,0xf4,0x10,0x38},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xfc,0xfb,0x14,0x2a},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xf1,0xf7,0x1f,0x32},
{0xff,0xff,0xff,0xff}
},
{
{0x00,0xf4,0x10,0x38},
{0x00,0xf4,0x10,0x38},
{0xeb,0x04,0x10,0x18},
{0xf7,0x06,0x19,0x14},
{0x00,0xf4,0x10,0x38},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x15,0x25,0xf6},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xff,0xff,0xff,0xff}
},
{
{0x00,0xf4,0x10,0x38},
{0x00,0xf4,0x10,0x38},
{0xeb,0x04,0x10,0x18},
{0xf7,0x06,0x19,0x14},
{0x00,0xf4,0x10,0x38},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x15,0x25,0xf6},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xff,0xff,0xff,0xff}
},
};
UCHAR SiS300_PALFilter2[9][7] = {
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0x01, 0x01, 0xFC, 0xF8, 0x08, 0x26, 0x38},
{0xFF, 0xFF, 0xFC, 0x00, 0x0F, 0x22, 0x28}
UCHAR SiS300_Filter2[10][9][7] =
{
{
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0x01,0x01,0xFC,0xF8,0x08,0x26,0x38},
{0xFF,0xFF,0xFC,0x00,0x0F,0x22,0x28}
},
{
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0x01,0x01,0xFC,0xF8,0x08,0x26,0x38},
{0xFF,0xFF,0xFC,0x00,0x0F,0x22,0x28}
},
{
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0x01,0x01,0xFC,0xF8,0x08,0x26,0x38},
{0xFF,0xFF,0xFC,0x00,0x0F,0x22,0x28}
},
{
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0x01,0x01,0xFC,0xF8,0x08,0x26,0x38},
{0xFF,0xFF,0xFC,0x00,0x0F,0x22,0x28}
},
{
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0x01,0x01,0xFC,0xF8,0x08,0x26,0x38},
{0xFF,0xFF,0xFC,0x00,0x0F,0x22,0x28}
},
{
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0x01,0x01,0xFC,0xF8,0x08,0x26,0x38},
{0xFF,0xFF,0xFC,0x00,0x0F,0x22,0x28}
},
{
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0x01,0x01,0xFC,0xF8,0x08,0x26,0x38},
{0xFF,0xFF,0xFC,0x00,0x0F,0x22,0x28}
},
{
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0x01,0x01,0xFC,0xF8,0x08,0x26,0x38},
{0xFF,0xFF,0xFC,0x00,0x0F,0x22,0x28}
},
{
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0x01,0x01,0xFC,0xF8,0x08,0x26,0x38},
{0xFF,0xFF,0xFC,0x00,0x0F,0x22,0x28}
},
{
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0x01,0x01,0xFC,0xF8,0x08,0x26,0x38},
{0xFF,0xFF,0xFC,0x00,0x0F,0x22,0x28}
}
};
UCHAR SiS300_PALMFilter[17][4] = {
{0x00, 0xf4, 0x10, 0x38},
{0x00, 0xf4, 0x10, 0x38},
{0xeb, 0x04, 0x10, 0x18},
{0xf7, 0x06, 0x19, 0x14},
{0x00, 0xf4, 0x10, 0x38},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x15, 0x25, 0xf6},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xff, 0xff, 0xff, 0xff}
};
UCHAR SiS300_PALNFilter[17][4] = {
{0x00, 0xf4, 0x10, 0x38},
{0x00, 0xf4, 0x10, 0x38},
{0xeb, 0x04, 0x10, 0x18},
{0xf7, 0x06, 0x19, 0x14},
{0x00, 0xf4, 0x10, 0x38},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x15, 0x25, 0xf6},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xff, 0xff, 0xff, 0xff}
};
UCHAR SiS300_PALMFilter2[9][7] = {
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0x01, 0x01, 0xFC, 0xF8, 0x08, 0x26, 0x38},
{0xFF, 0xFF, 0xFC, 0x00, 0x0F, 0x22, 0x28}
};
UCHAR SiS300_PALNFilter2[9][7] = {
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0x01, 0x01, 0xFC, 0xF8, 0x08, 0x26, 0x38},
{0xFF, 0xFF, 0xFC, 0x00, 0x0F, 0x22, 0x28}
};
drivers/video/sis/oem310.h
View file @ 4ec16d90
UCHAR SiS310_CRT2DelayCompensation1 = 0x4; /* 301A */
UCHAR SiS310_LCDDelayCompensation1[] = {
0x0, 0x0, 0x0, 0xb, 0xb, 0xb, 0x8, 0x8,
0x8, 0x8, 0x8, 0x8, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0
};
UCHAR SiS310_TVDelayCompensation1[] = { 0x2, 0x2, 0x2, 0x2, 0x8, 0xb };
UCHAR SiS310_CRT2DelayCompensation2 = 0xC; /* 301B */
UCHAR SiS310_LCDDelayCompensation2[] = {
0x0, 0x0, 0x0, 0x0C, 0x0C, 0x0C, 0x0C,
0x0C, 0x0C, 0x8, 0x8, 0x8, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
};
UCHAR SiS310_TVDelayCompensation2[] = { 0x3, 0x3, 0x3, 0x3, 0x8, 0xb };
UCHAR SiS310_TVAntiFlick1[3][2] = {
{0x4, 0x0},
{0x4, 0x8},
{0x0, 0x0}
};
UCHAR SiS310_TVEdge1[3][2] = {
{0x0, 0x4},
{0x0, 0x4},
{0x0, 0x0}
};
UCHAR SiS310_TVYFilter1[3][8][4] = {
{
{0x0, 0xf4, 0x10, 0x38},
{0x0, 0xf4, 0x10, 0x38},
{0xeb, 0x4, 0x25, 0x18},
{0xf7, 0x6, 0x19, 0x14},
{0x0, 0xf4, 0x10, 0x38},
{0xeb, 0x4, 0x25, 0x18},
{0xee, 0xc, 0x22, 0x8},
{0xeb, 0x15, 0x25, 0xf6}
}
,
{
{0x0, 0xf4, 0x10, 0x38},
{0x0, 0xf4, 0x10, 0x38},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf3, 0x0, 0x1d, 0x20},
{0x0, 0xf4, 0x10, 0x38},
{0xf1, 0xf7, 0x1f, 0x32},
{0xf3, 0x0, 0x1d, 0x20},
{0xfc, 0xfb, 0x14, 0x2a}
}
,
{
{0x0, 0x0, 0x0, 0x0},
{0x0, 0xf4, 0x10, 0x38},
{0x0, 0xf4, 0x10, 0x38},
{0xeb, 0x4, 0x25, 0x18},
{0xf7, 0x6, 0x19, 0x14},
{0x0, 0xf4, 0x10, 0x38},
{0xeb, 0x4, 0x25, 0x18},
{0xee, 0xc, 0x22, 0x8}
}
};
/*301b*/
UCHAR SiS310_TVYFilter2[3][9][7] = {
{
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0x01, 0x01, 0xFC, 0xF8, 0x08, 0x26, 0x38},
{0xFF, 0xFF, 0xFC, 0x00, 0x0F, 0x22, 0x28}
}
,
{
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0x01, 0x01, 0xFC, 0xF8, 0x08, 0x26, 0x38},
{0xFF, 0xFF, 0xFC, 0x00, 0x0F, 0x22, 0x28}
}
,
{
{0x0, 0x0, 0x0, 0xF4, 0xFF, 0x1C, 0x22},
{0x0, 0x0, 0x0, 0xF4, 0xFF, 0x1C, 0x22},
{0x0, 0x0, 0x0, 0xF4, 0xFF, 0x1C, 0x22},
{0x0, 0x0, 0x0, 0xF4, 0xFF, 0x1C, 0x22},
{0x0, 0x0, 0x0, 0xF4, 0xFF, 0x1C, 0x22},
{0x0, 0x0, 0x0, 0xF4, 0xFF, 0x1C, 0x22},
{0x0, 0x0, 0x0, 0xF4, 0xFF, 0x1C, 0x22},
{0x0, 0x0, 0x0, 0xF4, 0xFF, 0x1C, 0x22}
}
};
/*end 301b*/
/*add PALMN*/
UCHAR SiS310_PALMFilter[17][4] = {
{0x00, 0xf4, 0x10, 0x38},
{0x00, 0xf4, 0x10, 0x38},
{0xeb, 0x04, 0x10, 0x18},
{0xf7, 0x06, 0x19, 0x14},
{0x00, 0xf4, 0x10, 0x38},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x15, 0x25, 0xf6},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xff, 0xff, 0xff, 0xff}
};
UCHAR SiS310_PALNFilter[17][4] = {
{0x00, 0xf4, 0x10, 0x38},
{0x00, 0xf4, 0x10, 0x38},
{0xeb, 0x04, 0x10, 0x18},
{0xf7, 0x06, 0x19, 0x14},
{0x00, 0xf4, 0x10, 0x38},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x15, 0x25, 0xf6},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xeb, 0x04, 0x25, 0x18},
{0xff, 0xff, 0xff, 0xff}
};
UCHAR SiS310_PALMFilter2[9][7] = {
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0x01, 0x01, 0xFC, 0xF8, 0x08, 0x26, 0x38},
{0xFF, 0xFF, 0xFC, 0x00, 0x0F, 0x22, 0x28}
};
UCHAR SiS310_PALNFilter2[9][7] = {
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46},
{0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C},
{0x01, 0x01, 0xFC, 0xF8, 0x08, 0x26, 0x38},
{0xFF, 0xFF, 0xFC, 0x00, 0x0F, 0x22, 0x28}
};
/*end PALMN*/
UCHAR SiS310_TVPhaseIncr1[3][2][4] = {
{
{0x21, 0xed, 0x8a, 0x8},
{0x21, 0xed, 0x8a, 0x8}
}
,
{
{0x2a, 0x5, 0xd3, 0x0},
{0x2a, 0x5, 0xd3, 0x0}
}
,
{
{0x2a, 0x5, 0xd3, 0x0},
{0x2a, 0x5, 0xd3, 0x0}
}
};
UCHAR SiS310_TVPhaseIncr2[3][2][4] = {
{
{0x21, 0xF0, 0x7b, 0xd6},
{0x21, 0xF0, 0x7b, 0xd6}
}
,
{
{0x2a, 0x09, 0x86, 0xe9},
{0x2a, 0x09, 0x86, 0xe9}
}
,
{
{0x2a, 0x5, 0xd3, 0x0},
{0x2a, 0x5, 0xd3, 0x0}
}
/* OEM Data for 300 series */
UCHAR SiS310_CRT2DelayCompensation1 = 0x04; /* 301A */
UCHAR SiS310_LCDDelayCompensation1[] =
{
0x00,0x00,0x00,
0x0b,0x0b,0x0b,
0x08,0x08,0x08,
0x08,0x08,0x08,
0x00,0x00,0x00,
0x00,0x00,0x00,
0x00,0x00,0x00
};
UCHAR SiS310_TVDelayCompensation1[] =
{
0x02,0x02, /* NTSC Enhanced, Standard */
0x02,0x02, /* PAL */
0x08,0x0b /* HiVision */
};
UCHAR SiS310_CRT2DelayCompensation2 = 0x00; /* TW: From 650/301LV BIOS; was 0x0C; */ /* 301B */
UCHAR SiS310_LCDDelayCompensation2[] =
{
0x01,0x01,0x01, /* TW: From 650/301LV BIOS */
0x01,0x01,0x01,
0x01,0x01,0x01,
0x01,0x01,0x01,
0x01,0x01,0x01,
0x01,0x01,0x01,
0x01,0x01,0x01
#if 0
0x00,0x00,0x00, /* 800x600 VESA, non-VESA, non-expanding */
0x0C,0x0C,0x0C, /* 1024x768 */
0x0C,0x0C,0x0C, /* 1280x1024 */
0x08,0x08,0x08, /* 1280x960 */
0x00,0x00,0x00, /* 640x480 */
0x00,0x00,0x00, /* 1600x1200 */
0x00,0x00,0x00 /* 1920x1440 */
#endif
};
UCHAR SiS310_TVDelayCompensation2[] =
{
0x05,0x05, /* TW: From 650/301LV BIOS */
0x05,0x05,
0x05,0x05
#if 0
0x03,0x03, /* NTSC Enhanced, Standard */
0x03,0x03, /* PAL */
0x08,0x0b /* HiVision */
#endif
};
UCHAR SiS310_CRT2DelayCompensation3 = 0x00; /* LVDS */
UCHAR SiS310_LCDDelayCompensation3[] =
{
0x00,0x00,0x00, /* 800x600 */
0x00,0x00,0x00, /* 1024x768 */
0x00,0x00,0x00, /* 1280x1024 */
0x00,0x00,0x00, /* 1400x1050 */
0x00,0x00,0x00 /* 1600x1200 */
};
UCHAR SiS310_TVDelayCompensation3[] =
{
0x0a,0x0a,
0x0a,0x0a,
0x0a,0x0a
};
UCHAR SiS310_TVAntiFlick1[3][2] =
{
{0x4,0x0},
{0x4,0x8},
{0x0,0x0}
};
UCHAR SiS310_TVEdge1[3][2] =
{
{0x0,0x4},
{0x0,0x4},
{0x0,0x0}
};
UCHAR SiS310_TVYFilter1[3][8][4] =
{
{
{0x00,0xf4,0x10,0x38},
{0x00,0xf4,0x10,0x38},
{0xeb,0x04,0x25,0x18},
{0xf1,0x04,0x1f,0x18},
{0x00,0xf4,0x10,0x38},
{0xeb,0x04,0x25,0x18},
{0xee,0x0c,0x22,0x08},
{0xeb,0x15,0x25,0xf6}
},
{
{0x00,0xf4,0x10,0x38},
{0x00,0xf4,0x10,0x38},
{0xf1,0xf7,0x1f,0x32},
{0xf3,0x00,0x1d,0x20},
{0x00,0xf4,0x10,0x38},
{0xf1,0xf7,0x1f,0x32},
{0xf3,0x00,0x1d,0x20},
{0xfc,0xfb,0x14,0x2a}
},
{
{0x00,0x00,0x00,0x00},
{0x00,0xf4,0x10,0x38},
{0x00,0xf4,0x10,0x38},
{0xeb,0x04,0x25,0x18},
{0xf7,0x06,0x19,0x14},
{0x00,0xf4,0x10,0x38},
{0xeb,0x04,0x25,0x18},
{0xee,0x0c,0x22,0x08}
}
};
UCHAR SiS310_TVYFilter2[3][9][7] =
{
{
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0x01,0x01,0xFC,0xF8,0x08,0x26,0x38},
{0xFF,0xFF,0xFC,0x00,0x0F,0x22,0x28}
},
{
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0x01,0x01,0xFC,0xF8,0x08,0x26,0x38},
{0xFF,0xFF,0xFC,0x00,0x0F,0x22,0x28}
},
{
{0x00,0x00,0x00,0xF4,0xFF,0x1C,0x22},
{0x00,0x00,0x00,0xF4,0xFF,0x1C,0x22},
{0x00,0x00,0x00,0xF4,0xFF,0x1C,0x22},
{0x00,0x00,0x00,0xF4,0xFF,0x1C,0x22},
{0x00,0x00,0x00,0xF4,0xFF,0x1C,0x22},
{0x00,0x00,0x00,0xF4,0xFF,0x1C,0x22},
{0x00,0x00,0x00,0xF4,0xFF,0x1C,0x22},
{0x00,0x00,0x00,0xF4,0xFF,0x1C,0x22}
}
};
UCHAR SiS310_PALMFilter[17][4] =
{
{0x00,0xf4,0x10,0x38},
{0x00,0xf4,0x10,0x38},
{0xeb,0x04,0x10,0x18},
{0xf7,0x06,0x19,0x14},
{0x00,0xf4,0x10,0x38},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x15,0x25,0xf6},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xff,0xff,0xff,0xff}
};
UCHAR SiS310_PALNFilter[17][4] =
{
{0x00,0xf4,0x10,0x38},
{0x00,0xf4,0x10,0x38},
{0xeb,0x04,0x10,0x18},
{0xf7,0x06,0x19,0x14},
{0x00,0xf4,0x10,0x38},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x15,0x25,0xf6},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xeb,0x04,0x25,0x18},
{0xff,0xff,0xff,0xff}
};
UCHAR SiS310_PALMFilter2[9][7] =
{
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0x01,0x01,0xFC,0xF8,0x08,0x26,0x38},
{0xFF,0xFF,0xFC,0x00,0x0F,0x22,0x28}
};
UCHAR SiS310_PALNFilter2[9][7] =
{
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
{0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
{0x01,0x01,0xFC,0xF8,0x08,0x26,0x38},
{0xFF,0xFF,0xFC,0x00,0x0F,0x22,0x28}
};
UCHAR SiS310_TVPhaseIncr1[3][2][4]=
{
{
{0x21,0xed,0xba,0x08},
{0x21,0xed,0xba,0x08}
},
{
{0x2a,0x05,0xe3,0x00},
{0x2a,0x05,0xe3,0x00}
},
{
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00}
}
};
UCHAR SiS310_TVPhaseIncr2[3][2][4]=
{
{
{0x21,0xF1,0x37,0x56},
{0x21,0xF1,0x37,0x56}
},
{
{0x2a,0x09,0x86,0xe9},
{0x2a,0x09,0x86,0xe9}
},
{
{0x2a,0x05,0xd3,0x00},
{0x2a,0x05,0xd3,0x00}
}
};
drivers/video/sis/osdef.h
View file @ 4ec16d90
#define LINUX_KERNEL
/* #define WINCE_HEADER */
/* #define WIN2000 */
/* #define TC */
#define LINUX_KERNEL /* Kernel framebuffer */
/* #define LINUX_XF86 */ /* XFree86 */
/**********************************************************************/
#ifdef LINUX_KERNEL
#include <linux/config.h>
#ifdef CONFIG_FB_SIS_300
#define SIS300
#endif
#ifdef CONFIG_FB_SIS_315
#define SIS315H
#endif
#else
/* #define SIS300*/
#define SIS315H
#endif
#ifdef LINUX_XF86
#define SIS300
/* #define SIS315H */ /* TW: done above */
#endif
/**********************************************************************/
#ifdef TC
#endif
#ifdef WIN2000
#endif
#ifdef WINCE_HEADER
#endif
#ifdef LINUX_XF86
#endif
#ifdef LINUX_KERNEL
#endif
/**********************************************************************/
#ifdef TC
#define SiS_SetMemory(MemoryAddress,MemorySize,value) memset(MemoryAddress, value, MemorySize);
#endif
#ifdef WIN2000
#define SiS_SetMemory(MemoryAddress,MemorySize,value) MemFill((PVOID) MemoryAddress,(ULONG) MemorySize,(UCHAR) value);
#endif
#ifdef WINCE_HEADER
#define SiS_SetMemory(MemoryAddress,MemorySize,value) memset(MemoryAddress, value, MemorySize);
#endif
#ifdef LINUX_XF86
#define SiS_SetMemory(MemoryAddress,MemorySize,value) memset(MemoryAddress, value, MemorySize)
#endif
#ifdef LINUX_KERNEL
#define SiS_SetMemory(MemoryAddress,MemorySize,value) memset(MemoryAddress, value, MemorySize)
#endif
/**********************************************************************/
/**********************************************************************/
#ifdef TC
#define SiS_MemoryCopy(Destination,Soruce,Length) memmove(Destination, Soruce, Length);
#endif
#ifdef WIN2000
#define SiS_MemoryCopy(Destination,Soruce,Length) /*VideoPortMoveMemory((PUCHAR)Destination , Soruce,length);*/
#endif
#ifdef WINCE_HEADER
#define SiS_MemoryCopy(Destination,Soruce,Length) memmove(Destination, Soruce, Length);
#endif
#ifdef LINUX_XF86
#define SiS_MemoryCopy(Destination,Soruce,Length) memcpy(Destination,Soruce,Length)
#endif
#ifdef LINUX_KERNEL
#define SiS_MemoryCopy(Destination,Soruce,Length) memcpy(Destination,Soruce,Length)
#endif
/**********************************************************************/
#ifdef OutPortByte
#undef OutPortByte
#endif /* OutPortByte */
#endif /* OutPortByte */
#ifdef OutPortWord
#undef OutPortWord
#endif /* OutPortWord */
#endif /* OutPortWord */
#ifdef OutPortLong
#undef OutPortLong
#endif /* OutPortLong */
#endif /* OutPortLong */
#ifdef InPortByte
#undef InPortByte
#endif /* InPortByte */
#endif /* InPortByte */
#ifdef InPortWord
#undef InPortWord
#endif /* InPortWord */
#endif /* InPortWord */
#ifdef InPortLong
#undef InPortLong
#endif /* InPortLong */
#endif /* InPortLong */
/**********************************************************************/
/* TC */
/**********************************************************************/
#ifdef TC
#define OutPortByte(p,v) outp((unsigned short)(p),(unsigned char)(v))
#define OutPortWord(p,v) outp((unsigned short)(p),(unsigned short)(v))
#define OutPortLong(p,v) outp((unsigned short)(p),(unsigned long)(v))
#define InPortByte(p) inp((unsigned short)(p))
#define InPortWord(p) inp((unsigned short)(p))
#define InPortLong(p) ((inp((unsigned short)(p+2))<<16) | inp((unsigned short)(p)))
#endif
/**********************************************************************/
/* LINUX XF86 */
/**********************************************************************/
#ifdef LINUX_XF86
#define OutPortByte(p,v) outb((CARD16)(p),(CARD8)(v))
#define OutPortWord(p,v) outw((CARD16)(p),(CARD16)(v))
#define OutPortLong(p,v) outl((CARD16)(p),(CARD32)(v))
#define InPortByte(p) inb((CARD16)(p))
#define InPortWord(p) inw((CARD16)(p))
#define InPortLong(p) inl((CARD16)(p))
#endif
#ifdef LINUX_KERNEL
#define OutPortByte(p,v) outb((u8)(v),(u16)(p))
#define OutPortWord(p,v) outw((u16)(v),(u16)(p))
#define OutPortLong(p,v) outl((u32)(v),(u16)(p))
#define InPortByte(p) inb((u16)(p))
#define InPortWord(p) inw((u16)(p))
#define InPortLong(p) inl((u16)(p))
#endif
/**********************************************************************/
/* WIN 2000 */
/**********************************************************************/
#ifdef WIN2000
#define OutPortByte(p,v) VideoPortWritePortUchar ((PUCHAR) (p), (UCHAR) (v))
#define OutPortWord(p,v) VideoPortWritePortUshort((PUSHORT) (p), (USHORT) (v))
#define OutPortLong(p,v) VideoPortWritePortUlong ((PULONG) (p), (ULONG) (v))
#define InPortByte(p) VideoPortReadPortUchar ((PUCHAR) (p))
#define InPortWord(p) VideoPortReadPortUshort ((PUSHORT) (p))
#define InPortLong(p) VideoPortReadPortUlong ((PULONG) (p))
#endif
/**********************************************************************/
/* WIN CE */
/**********************************************************************/
#ifdef WINCE_HEADER
#define OutPortByte(p,v) WRITE_PORT_UCHAR ((PUCHAR) (p), (UCHAR) (v))
#define OutPortWord(p,v) WRITE_PORT_USHORT((PUSHORT) (p), (USHORT) (v))
#define OutPortLong(p,v) WRITE_PORT_ULONG ((PULONG) (p), (ULONG) (v))
#define InPortByte(p) READ_PORT_UCHAR ((PUCHAR) (p))
#define InPortWord(p) READ_PORT_USHORT ((PUSHORT) (p))
#define InPortLong(p) READ_PORT_ULONG ((PULONG) (p))
#endif
drivers/video/sis/sis_main.c
View file @ 4ec16d90
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/video/sis/sis_main.h
View file @ 4ec16d90
#ifndef _SISFB_MAIN
#define _SISFB_MAIN
/* Comments and changes marked with "TW" by Thomas Winischhofer <tw@webit.com> */
/* ------------------- Constant Definitions ------------------------- */
#undef LINUXBIOS /* turn on when use LINUXBIOS */
#define AGPOFF /* default is turn off AGP */
#undef LINUXBIOS /* turn on when use LINUXBIOS */
#define AGPOFF /* default is turn off AGP */
#define VER_MAJOR 1
#define VER_MINOR 3
#define VER_LEVEL 9
#define VER_MINOR 4
#define VER_LEVEL 1
#define DEFAULT_MODE 0
#define DEFAULT_LCDMODE 9
#define DEFAULT_TVMODE 9
/* TW: To be included in pci_ids.h */
#ifndef PCI_DEVICE_ID_SI_650_VGA
#define PCI_DEVICE_ID_SI_650_VGA 0x6325
#endif
#ifndef PCI_DEVICE_ID_SI_650
#define PCI_DEVICE_ID_SI_650 0x0650
#endif
/* TW end */
#define MAX_ROM_SCAN 0x10000
......@@ -23,17 +30,19 @@
/* For 300 series */
#ifdef CONFIG_FB_SIS_300
#define TURBO_QUEUE_AREA_SIZE 0x80000 /* 512K */
#define HW_CURSOR_AREA_SIZE 0x1000 /* 4K */
#define TURBO_QUEUE_AREA_SIZE 0x80000 /* 512K */
#endif
/* For 315 series */
#ifdef CONFIG_FB_SIS_315
#define COMMAND_QUEUE_AREA_SIZE 0x80000 /* 512K */
#define HW_CURSOR_AREA_SIZE 0x4000 /* 16K */
#define COMMAND_QUEUE_AREA_SIZE 0x80000 /* 512K */
#define COMMAND_QUEUE_THRESHOLD 0x1F
#endif
/* TW */
#define HW_CURSOR_AREA_SIZE_315 0x4000 /* 16K */
#define HW_CURSOR_AREA_SIZE_300 0x1000 /* 4K */
#define OH_ALLOC_SIZE 4000
#define SENTINEL 0x7fffffff
......@@ -54,7 +63,7 @@
#define VB_PART4_ADR (0x14-0x30)
#define VB_PART4_DATA (0x15-0x30)
#define IND_SIS_PASSWORD 0x05 /* SRs */
#define IND_SIS_PASSWORD 0x05 /* SRs */
#define IND_SIS_COLOR_MODE 0x06
#define IND_SIS_RAMDAC_CONTROL 0x07
#define IND_SIS_DRAM_SIZE 0x14
......@@ -70,7 +79,7 @@
#define IND_SIS_CMDQUEUE_SET 0x26
#define IND_SIS_CMDQUEUE_THRESHOLD 0x27
#define IND_SIS_SCRATCH_REG_CR30 0x30 /* CRs */
#define IND_SIS_SCRATCH_REG_CR30 0x30 /* CRs */
#define IND_SIS_SCRATCH_REG_CR31 0x31
#define IND_SIS_SCRATCH_REG_CR32 0x32
#define IND_SIS_SCRATCH_REG_CR33 0x33
......@@ -78,28 +87,24 @@
#define IND_SIS_SCRATCH_REG_CR37 0x37
#define IND_SIS_AGP_IO_PAD 0x48
#define IND_BRI_DRAM_STATUS 0x63
#define IND_BRI_DRAM_STATUS 0x63 /* PCI config memory size offset */
#define MMIO_QUEUE_PHYBASE 0x85C0
#define MMIO_QUEUE_WRITEPORT 0x85C4
#define MMIO_QUEUE_READPORT 0x85C8
// Eden Chen
#ifdef CONFIG_FB_SIS_300
#define IND_SIS_CRT2_WRITE_ENABLE 0x24
#endif
#ifdef CONFIG_FB_SIS_315
#define IND_SIS_CRT2_WRITE_ENABLE 0x2F
#endif
// ~Eden Chen
#define SIS_PASSWORD 0x86 /* SR05 */
#define SIS_INTERLACED_MODE 0x20 /* SR06 */
#define SIS_8BPP_COLOR_MODE 0x0
#define SIS_15BPP_COLOR_MODE 0x1
#define SIS_16BPP_COLOR_MODE 0x2
#define SIS_32BPP_COLOR_MODE 0x4
#define SIS_DRAM_SIZE_MASK 0x3F /* SR14 */
/* Eden Chen; TW */
#define IND_SIS_CRT2_WRITE_ENABLE_300 0x24
#define IND_SIS_CRT2_WRITE_ENABLE_315 0x2F
/* ~Eden Chen; TW */
#define SIS_PASSWORD 0x86 /* SR05 */
#define SIS_INTERLACED_MODE 0x20 /* SR06 */
#define SIS_8BPP_COLOR_MODE 0x0
#define SIS_15BPP_COLOR_MODE 0x1
#define SIS_16BPP_COLOR_MODE 0x2
#define SIS_32BPP_COLOR_MODE 0x4
#define SIS_DRAM_SIZE_MASK 0x3F /* SR14 */
#define SIS_DRAM_SIZE_1MB 0x00
#define SIS_DRAM_SIZE_2MB 0x01
#define SIS_DRAM_SIZE_4MB 0x03
......@@ -111,7 +116,8 @@
#define SIS_DATA_BUS_32 0x00
#define SIS_DATA_BUS_64 0x01
#define SIS_DATA_BUS_128 0x02
#define SIS315_DRAM_SIZE_MASK 0xF0 /* 315 SR14 */
#define SIS315_DRAM_SIZE_MASK 0xF0 /* 315 SR14 */
#define SIS315_DRAM_SIZE_2MB 0x01
#define SIS315_DRAM_SIZE_4MB 0x02
#define SIS315_DRAM_SIZE_8MB 0x03
......@@ -123,10 +129,12 @@
#define SIS315_DATA_BUS_64 0x00
#define SIS315_DATA_BUS_128 0x01
#define SIS315_DUAL_CHANNEL_MASK 0x0C
#define SIS315_SINGLE_CHANNEL_1_RANK 0x0
#define SIS315_SINGLE_CHANNEL_2_RANK 0x1
#define SIS315_DUAL_CHANNEL_1_RANK 0x3
#define SIS550_DRAM_SIZE_MASK 0x3F /* 550 SR14 */
#define SIS315_SINGLE_CHANNEL_1_RANK 0x0
#define SIS315_SINGLE_CHANNEL_2_RANK 0x1
#define SIS315_ASYM_DDR 0x02
#define SIS315_DUAL_CHANNEL_1_RANK 0x3
#define SIS550_DRAM_SIZE_MASK 0x3F /* 550/650/740 SR14 */
#define SIS550_DRAM_SIZE_4MB 0x00
#define SIS550_DRAM_SIZE_8MB 0x01
#define SIS550_DRAM_SIZE_16MB 0x03
......@@ -138,10 +146,13 @@
#define SIS550_DRAM_SIZE_256MB 0x3F
#define SIS_SCRATCH_REG_1A_MASK 0x10
#define SIS_ENABLE_2D 0x40 /* SR1E */
#define SIS_MEM_MAP_IO_ENABLE 0x01 /* SR20 */
#define SIS_ENABLE_2D 0x40 /* SR1E */
#define SIS_MEM_MAP_IO_ENABLE 0x01 /* SR20 */
#define SIS_PCI_ADDR_ENABLE 0x80
#define SIS_AGP_CMDQUEUE_ENABLE 0x80 /* 315 SR26 */
#define SIS_AGP_CMDQUEUE_ENABLE 0x80 /* 315/650/740 SR26 */
#define SIS_VRAM_CMDQUEUE_ENABLE 0x40
#define SIS_MMIO_CMD_ENABLE 0x20
#define SIS_CMD_QUEUE_SIZE_512k 0x00
......@@ -149,7 +160,9 @@
#define SIS_CMD_QUEUE_SIZE_2M 0x08
#define SIS_CMD_QUEUE_SIZE_4M 0x0C
#define SIS_CMD_QUEUE_RESET 0x01
#define SIS_SIMULTANEOUS_VIEW_ENABLE 0x01 /* CR30 */
#define SIS_CMD_AUTO_CORR 0x02
#define SIS_SIMULTANEOUS_VIEW_ENABLE 0x01 /* CR30 */
#define SIS_MODE_SELECT_CRT2 0x02
#define SIS_VB_OUTPUT_COMPOSITE 0x04
#define SIS_VB_OUTPUT_SVIDEO 0x08
......@@ -157,9 +170,11 @@
#define SIS_VB_OUTPUT_LCD 0x20
#define SIS_VB_OUTPUT_CRT2 0x40
#define SIS_VB_OUTPUT_HIVISION 0x80
#define SIS_VB_OUTPUT_DISABLE 0x20 /* CR31 */
#define SIS_VB_OUTPUT_DISABLE 0x20 /* CR31 */
#define SIS_DRIVER_MODE 0x40
#define SIS_VB_COMPOSITE 0x01 /* CR32 */
#define SIS_VB_COMPOSITE 0x01 /* CR32 */
#define SIS_VB_SVIDEO 0x02
#define SIS_VB_SCART 0x04
#define SIS_VB_LCD 0x08
......@@ -167,21 +182,21 @@
#define SIS_CRT1 0x20
#define SIS_VB_HIVISION 0x40
#define SIS_VB_DVI 0x80
#define SIS_VB_TV (SIS_VB_COMPOSITE | SIS_VB_SVIDEO | SIS_VB_SCART | SIS_VB_HIVISION)
#define SIS_LCD_PANEL_800X600 0x1 /* CR36 */
#define SIS_LCD_PANEL_1024X768 0x2
#define SIS_LCD_PANEL_1280X1024 0x3
#define SIS_LCD_PANEL_1280X960 0x4
#define SIS_LCD_PANEL_640X480 0x5
#define SIS_EXTERNAL_CHIP_MASK 0x0E /* CR37 */
#define SIS_EXTERNAL_CHIP_SIS301 0x01
#define SIS_EXTERNAL_CHIP_LVDS 0x02
#define SIS_EXTERNAL_CHIP_TRUMPION 0x03
#define SIS_EXTERNAL_CHIP_LVDS_CHRONTEL 0x04
#define SIS_EXTERNAL_CHIP_CHRONTEL 0x05
#define SIS_AGP_2X 0x20 /* CR48 */
#define BRI_DRAM_SIZE_MASK 0x70 /* PCI bridge */
#define SIS_VB_TV (SIS_VB_COMPOSITE | SIS_VB_SVIDEO | \
SIS_VB_SCART | SIS_VB_HIVISION)
#define SIS_EXTERNAL_CHIP_MASK 0x0E /* CR37 */
#define SIS_EXTERNAL_CHIP_SIS301 0x01 /* in CR37 << 1 ! */
#define SIS_EXTERNAL_CHIP_LVDS 0x02 /* in CR37 << 1 ! */
#define SIS_EXTERNAL_CHIP_TRUMPION 0x03 /* in CR37 << 1 ! */
#define SIS_EXTERNAL_CHIP_LVDS_CHRONTEL 0x04 /* in CR37 << 1 ! */
#define SIS_EXTERNAL_CHIP_CHRONTEL 0x05 /* in CR37 << 1 ! */
#define SIS310_EXTERNAL_CHIP_LVDS 0x02 /* in CR37 << 1 ! */
#define SIS310_EXTERNAL_CHIP_LVDS_CHRONTEL 0x03 /* in CR37 << 1 ! */
#define SIS_AGP_2X 0x20 /* CR48 */
#define BRI_DRAM_SIZE_MASK 0x70 /* PCI bridge config data */
#define BRI_DRAM_SIZE_2MB 0x00
#define BRI_DRAM_SIZE_4MB 0x01
#define BRI_DRAM_SIZE_8MB 0x02
......@@ -190,7 +205,7 @@
#define BRI_DRAM_SIZE_64MB 0x05
// Eden Chen
#define HW_DEVICE_EXTENSION SIS_HW_DEVICE_INFO
#define HW_DEVICE_EXTENSION SIS_HW_DEVICE_INFO
#define PHW_DEVICE_EXTENSION PSIS_HW_DEVICE_INFO
#define SR_BUFFER_SIZE 5
......@@ -207,19 +222,33 @@ static int video_linelength;
static int video_cmap_len;
static struct display_switch sisfb_sw;
static struct fb_var_screeninfo default_var = {
0, 0, 0, 0,
0, 0,
0,
0,
{0, 8, 0},
{0, 8, 0},
{0, 8, 0},
{0, 0, 0},
0,
FB_ACTIVATE_NOW, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0,
0,
FB_VMODE_NONINTERLACED,
{0, 0, 0, 0, 0, 0}
xres: 0,
yres: 0,
xres_virtual: 0,
yres_virtual: 0,
xoffset: 0,
yoffset: 0,
bits_per_pixel: 0,
grayscale: 0,
red: {0, 8, 0},
green: {0, 8, 0},
blue: {0, 8, 0},
transp: {0, 0, 0},
nonstd: 0,
activate: FB_ACTIVATE_NOW,
height: -1,
width: -1,
accel_flags: 0,
pixclock: 0,
left_margin: 0,
right_margin: 0,
upper_margin: 0,
lower_margin: 0,
hsync_len: 0,
vsync_len: 0,
sync: 0,
vmode: FB_VMODE_NONINTERLACED,
reserved: {0, 0, 0, 0, 0, 0}
};
static struct {
......@@ -240,11 +269,14 @@ static union {
/* display status */
static int sisfb_off = 0;
static int sisfb_crt1off = 0;
static int sisfb_forcecrt1 = -1;
static int sisfb_inverse = 0;
static int sisvga_enabled = 0;
/*karl*/
static int currcon = 0;
static int sisfb_tvmode = 0;
static int sisfb_mem = 0;
static int sisfb_pdc = 0;
static int enable_dstn = 0;
static enum _VGA_ENGINE {
UNKNOWN_VGA = 0,
......@@ -252,22 +284,28 @@ static enum _VGA_ENGINE {
SIS_315_VGA,
} sisvga_engine = UNKNOWN_VGA;
/* mode-related variables */
int sisfb_mode_idx = -1;
u8 sisfb_mode_no = 0;
u8 sisfb_rate_idx = 0;
/* TW: These are to adapted according to VGA_ENGINE type */
static int sisfb_hwcursor_size = 0;
static int sisfb_CRT2_write_enable = 0;
int sisfb_crt2type = -1; /* TW: CRT2 type (for overriding autodetection) */
int sisfb_queuemode = -1; /* TW: Use MMIO queue mode by default (310 series only) */
/* data for sis components*/
struct video_info ivideo;
// Eden Chen
/* TW: For ioctl SISFB_GET_INFO */
sisfb_info sisfbinfo;
/* TW: Hardware extension; contains data on hardware */
HW_DEVICE_EXTENSION sishw_ext = {
NULL, NULL, NULL, NULL,
0, 0, 0, 0, 0, 0, 0, 0, 0,
NULL, NULL, NULL, NULL,
{0, 0, 0, 0}
{0, 0, 0, 0},
0
};
// ~Eden Chen
/* card parameters */
static unsigned long sisfb_mmio_size = 0;
......@@ -284,19 +322,19 @@ static struct board {
u16 vendor, device;
const char *name;
} sisdev_list[] = {
{
PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_300, "SIS 300"}, {
PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_540_VGA, "SIS 540"}, {
PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_630_VGA, "SIS 630"}, {
PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_315H, "SIS 315H"}, {
PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_315, "SIS 315"}, {
PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_315PRO, "SIS 315Pro"}, {
PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_550_VGA, "SIS 550"}, {
0, 0, NULL}
{PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_300, "SIS 300"},
{PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_540_VGA, "SIS 540"},
{PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_630_VGA, "SIS 630/730"},
{PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_315H, "SIS 315H"},
{PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_315, "SIS 315"},
{PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_315PRO, "SIS 315PRO"},
{PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_550_VGA, "SIS 550"},
{PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650_VGA, "SIS 650/M650/740 VGA"},
{0, 0, NULL}
};
/* mode table */
static const struct _sisbios_mode {
struct _sisbios_mode {
char name[15];
u8 mode_no;
u16 xres;
......@@ -306,32 +344,131 @@ static const struct _sisbios_mode {
u16 cols;
u16 rows;
} sisbios_mode[] = {
{
"640x480x8", 0x2E, 640, 480, 8, 1, 80, 30}, {
"640x480x16", 0x44, 640, 480, 16, 1, 80, 30}, {
"640x480x32", 0x62, 640, 480, 32, 1, 80, 30}, {
"720x480x8", 0x31, 720, 480, 8, 1, 90, 30}, {
"720x480x16", 0x33, 720, 480, 16, 1, 90, 30}, {
"720x480x32", 0x35, 720, 480, 32, 1, 90, 30}, {
"720x576x8", 0x32, 720, 576, 8, 1, 90, 36}, {
"720x576x16", 0x34, 720, 576, 16, 1, 90, 36}, {
"720x576x32", 0x36, 720, 576, 32, 1, 90, 36}, {
"800x600x8", 0x30, 800, 600, 8, 2, 100, 37}, {
"800x600x16", 0x47, 800, 600, 16, 2, 100, 37}, {
"800x600x32", 0x63, 800, 600, 32, 2, 100, 37}, {
"1024x768x8", 0x38, 1024, 768, 8, 2, 128, 48}, {
"1024x768x16", 0x4A, 1024, 768, 16, 2, 128, 48}, {
"1024x768x32", 0x64, 1024, 768, 32, 2, 128, 48}, {
"1280x1024x8", 0x3A, 1280, 1024, 8, 2, 160, 64}, {
"1280x1024x16", 0x4D, 1280, 1024, 16, 2, 160, 64}, {
"1280x1024x32", 0x65, 1280, 1024, 32, 2, 160, 64}, {
"1600x1200x8", 0x3C, 1600, 1200, 8, 1, 200, 75}, {
"1600x1200x16", 0x3D, 1600, 1200, 16, 1, 200, 75}, {
"1600x1200x32", 0x66, 1600, 1200, 32, 1, 200, 75}, {
"1920x1440x8", 0x68, 1920, 1440, 8, 1, 240, 75}, {
"1920x1440x16", 0x69, 1920, 1440, 16, 1, 240, 75}, {
"1920x1440x32", 0x6B, 1920, 1440, 32, 1, 240, 75}, {
"\0", 0x00, 0, 0, 0, 0, 0, 0}
#define MODE_INDEX_NONE 0 /* TW: index for mode=none */
{"none", 0xFF, 0, 0, 0, 0, 0, 0}, /* TW: for mode "none" */
{"320x240x16", 0x56, 320, 240, 16, 1, 40, 15},
{"320x480x8", 0x5A, 320, 480, 8, 1, 40, 30}, /* TW: FSTN */
{"320x480x16", 0x5B, 320, 480, 16, 1, 40, 30}, /* TW: FSTN */
{"640x480x8", 0x2E, 640, 480, 8, 1, 80, 30},
{"640x480x16", 0x44, 640, 480, 16, 1, 80, 30},
{"640x480x24", 0x62, 640, 480, 32, 1, 80, 30}, /* TW: That's for people who mix up color- and fb depth */
{"640x480x32", 0x62, 640, 480, 32, 1, 80, 30},
{"720x480x8", 0x31, 720, 480, 8, 1, 90, 30},
{"720x480x16", 0x33, 720, 480, 16, 1, 90, 30},
{"720x480x24", 0x35, 720, 480, 32, 1, 90, 30},
{"720x480x32", 0x35, 720, 480, 32, 1, 90, 30},
{"720x576x8", 0x32, 720, 576, 8, 1, 90, 36},
{"720x576x16", 0x34, 720, 576, 16, 1, 90, 36},
{"720x576x24", 0x36, 720, 576, 32, 1, 90, 36},
{"720x576x32", 0x36, 720, 576, 32, 1, 90, 36},
{"800x480x8", 0x70, 800, 480, 8, 1, 100, 30}, /* TW: 310/325 series only */
{"800x480x16", 0x7a, 800, 480, 16, 1, 100, 30},
{"800x480x24", 0x76, 800, 480, 32, 1, 100, 30},
{"800x480x32", 0x76, 800, 480, 32, 1, 100, 30},
#define DEFAULT_MODE 20 /* TW: index for 800x600x8 */
#define DEFAULT_LCDMODE 20 /* TW: index for 800x600x8 */
#define DEFAULT_TVMODE 20 /* TW: index for 800x600x8 */
{"800x600x8", 0x30, 800, 600, 8, 2, 100, 37},
{"800x600x16", 0x47, 800, 600, 16, 2, 100, 37},
{"800x600x24", 0x63, 800, 600, 32, 2, 100, 37},
{"800x600x32", 0x63, 800, 600, 32, 2, 100, 37},
{"1024x576x8", 0x71, 1024, 576, 8, 1, 128, 36}, /* TW: 310/325 series only */
{"1024x576x16", 0x74, 1024, 576, 16, 1, 128, 36},
{"1024x576x24", 0x77, 1024, 576, 32, 1, 128, 36},
{"1024x576x32", 0x77, 1024, 576, 32, 1, 128, 36},
{"1024x600x8", 0x20, 1024, 600, 8, 1, 128, 37}, /* TW: 300 series only */
{"1024x600x16", 0x21, 1024, 600, 16, 1, 128, 37},
{"1024x600x24", 0x22, 1024, 600, 32, 1, 128, 37},
{"1024x600x32", 0x22, 1024, 600, 32, 1, 128, 37},
{"1024x768x8", 0x38, 1024, 768, 8, 2, 128, 48},
{"1024x768x16", 0x4A, 1024, 768, 16, 2, 128, 48},
{"1024x768x24", 0x64, 1024, 768, 32, 2, 128, 48},
{"1024x768x32", 0x64, 1024, 768, 32, 2, 128, 48},
{"1152x768x8", 0x23, 1152, 768, 8, 1, 144, 48}, /* TW: 300 series only */
{"1152x768x16", 0x24, 1152, 768, 16, 1, 144, 48},
{"1152x768x24", 0x25, 1152, 768, 32, 1, 144, 48},
{"1152x768x32", 0x25, 1152, 768, 32, 1, 144, 48},
{"1280x720x8", 0x79, 1280, 720, 8, 1, 160, 45}, /* TW: 310/325 series only */
{"1280x720x16", 0x75, 1280, 720, 16, 1, 160, 45},
{"1280x720x24", 0x78, 1280, 720, 32, 1, 160, 45},
{"1280x720x32", 0x78, 1280, 720, 32, 1, 160, 45},
{"1280x768x8", 0x23, 1280, 768, 8, 1, 160, 48}, /* TW: 3107325 series only */
{"1280x768x16", 0x24, 1280, 768, 16, 1, 160, 48},
{"1280x768x24", 0x25, 1280, 768, 32, 1, 160, 48},
{"1280x768x32", 0x25, 1280, 768, 32, 1, 160, 48},
#define MODEINDEX_1280x960 48
{"1280x960x8", 0x7C, 1280, 960, 8, 1, 160, 60}, /* TW: Modenumbers being patched */
{"1280x960x16", 0x7D, 1280, 960, 16, 1, 160, 60},
{"1280x960x24", 0x7E, 1280, 960, 32, 1, 160, 60},
{"1280x960x32", 0x7E, 1280, 960, 32, 1, 160, 60},
{"1280x1024x8", 0x3A, 1280, 1024, 8, 2, 160, 64},
{"1280x1024x16", 0x4D, 1280, 1024, 16, 2, 160, 64},
{"1280x1024x24", 0x65, 1280, 1024, 32, 2, 160, 64},
{"1280x1024x32", 0x65, 1280, 1024, 32, 2, 160, 64},
{"1400x1050x8", 0x26, 1400, 1050, 8, 1, 175, 65}, /* TW: 310/325 series only */
{"1400x1050x16", 0x27, 1400, 1050, 16, 1, 175, 65},
{"1400x1050x24", 0x28, 1400, 1050, 32, 1, 175, 65},
{"1400x1050x32", 0x28, 1400, 1050, 32, 1, 175, 65},
{"1600x1200x8", 0x3C, 1600, 1200, 8, 1, 200, 75},
{"1600x1200x16", 0x3D, 1600, 1200, 16, 1, 200, 75},
{"1600x1200x24", 0x66, 1600, 1200, 32, 1, 200, 75},
{"1600x1200x32", 0x66, 1600, 1200, 32, 1, 200, 75},
{"1920x1440x8", 0x68, 1920, 1440, 8, 1, 240, 75},
{"1920x1440x16", 0x69, 1920, 1440, 16, 1, 240, 75},
{"1920x1440x24", 0x6B, 1920, 1440, 32, 1, 240, 75},
{"1920x1440x32", 0x6B, 1920, 1440, 32, 1, 240, 75},
{"2048x1536x8", 0x6c, 2048, 1536, 8, 1, 256, 96}, /* TW: 310/325 series only */
{"2048x1536x16", 0x6d, 2048, 1536, 16, 1, 256, 96},
{"2048x1536x24", 0x6e, 2048, 1536, 32, 1, 256, 96},
{"2048x1536x32", 0x6e, 2048, 1536, 32, 1, 256, 96},
{"\0", 0x00, 0, 0, 0, 0, 0, 0}
};
/* mode-related variables */
int sisfb_mode_idx = MODE_INDEX_NONE;
u8 sisfb_mode_no = 0;
u8 sisfb_rate_idx = 0;
/* TW: CR36 evaluation */
USHORT sis300paneltype[] =
{ LCD_UNKNOWN, LCD_800x600, LCD_1024x768, LCD_1280x1024,
LCD_1280x960, LCD_640x480, LCD_1024x600, LCD_1152x768,
LCD_320x480, LCD_1024x768, LCD_1024x768, LCD_1024x768,
LCD_1024x768, LCD_1024x768, LCD_1024x768, LCD_1024x768 };
USHORT sis310paneltype[] =
{ LCD_UNKNOWN, LCD_800x600, LCD_1024x768, LCD_1280x1024,
LCD_640x480, LCD_1024x600, LCD_1152x864, LCD_1280x960,
LCD_1152x768, LCD_1400x1050,LCD_1280x768, LCD_1600x1200,
LCD_320x480, LCD_1024x768, LCD_1024x768, LCD_1024x768 };
static const struct _sis_crt2type {
char name[6];
int type_no;
} sis_crt2type[] = {
{"NONE", 0},
{"LCD", DISPTYPE_LCD},
{"TV", DISPTYPE_TV},
{"VGA", DISPTYPE_CRT2},
{"none", 0}, /* TW: make it fool-proof */
{"lcd", DISPTYPE_LCD},
{"tv", DISPTYPE_TV},
{"vga", DISPTYPE_CRT2},
{"\0", -1}
};
/* Queue mode selection for 310 series */
static const struct _sis_queuemode {
char name[6];
int type_no;
} sis_queuemode[] = {
{"AGP", AGP_CMD_QUEUE},
{"VRAM", VM_CMD_QUEUE},
{"MMIO", MMIO_CMD},
{"agp", AGP_CMD_QUEUE},
{"vram", VM_CMD_QUEUE},
{"mmio", MMIO_CMD},
{"\0", -1}
};
static struct _sis_vrate {
......@@ -340,43 +477,32 @@ static struct _sis_vrate {
u16 yres;
u16 refresh;
} sisfb_vrate[] = {
{
1, 640, 480, 60}, {
2, 640, 480, 72}, {
3, 640, 480, 75}, {
4, 640, 480, 85}, {
5, 640, 480, 100}, {
6, 640, 480, 120}, {
7, 640, 480, 160}, {
8, 640, 480, 200}, {
1, 720, 480, 60}, {
1, 720, 576, 50}, {
1, 800, 600, 56}, {
2, 800, 600, 60}, {
3, 800, 600, 72}, {
4, 800, 600, 75}, {
5, 800, 600, 85}, {
6, 800, 600, 100}, {
7, 800, 600, 120}, {
8, 800, 600, 160}, {
1, 1024, 768, 43}, {
2, 1024, 768, 60}, {
3, 1024, 768, 70}, {
4, 1024, 768, 75}, {
5, 1024, 768, 85}, {
6, 1024, 768, 100}, {
7, 1024, 768, 120}, {
1, 1280, 1024, 43}, {
2, 1280, 1024, 60}, {
3, 1280, 1024, 75}, {
4, 1280, 1024, 85}, {
1, 1600, 1200, 60}, {
2, 1600, 1200, 65}, {
3, 1600, 1200, 70}, {
4, 1600, 1200, 75}, {
5, 1600, 1200, 85}, {
1, 1920, 1440, 60}, {
0, 0, 0, 0}
{1, 640, 480, 60}, {2, 640, 480, 72}, {3, 640, 480, 75}, {4, 640, 480, 85},
{5, 640, 480,100}, {6, 640, 480, 120}, {7, 640, 480, 160}, {8, 640, 480, 200},
{1, 720, 480, 60},
{1, 720, 576, 58},
{1, 800, 480, 60}, {2, 800, 480, 75}, {3, 800, 480, 85},
{1, 800, 600, 56}, {2, 800, 600, 60}, {3, 800, 600, 72}, {4, 800, 600, 75},
{5, 800, 600, 85}, {6, 800, 600, 100}, {7, 800, 600, 120}, {8, 800, 600, 160},
{1, 1024, 768, 43}, {2, 1024, 768, 60}, {3, 1024, 768, 70}, {4, 1024, 768, 75},
{5, 1024, 768, 85}, {6, 1024, 768, 100}, {7, 1024, 768, 120},
{1, 1024, 576, 60}, {2, 1024, 576, 65}, {3, 1024, 576, 75},
{1, 1024, 600, 60},
{1, 1152, 768, 60},
{1, 1280, 720, 60}, {2, 1280, 720, 75}, {3, 1280, 720, 85},
{1, 1280, 768, 60},
{1, 1280, 1024, 43}, {2, 1280, 1024, 60}, {3, 1280, 1024, 75}, {4, 1280, 1024, 85},
{1, 1280, 960, 60},
{1, 1400, 1050, 60},
{1, 1600, 1200, 60}, {2, 1600, 1200, 65}, {3, 1600, 1200, 70}, {4, 1600, 1200, 75},
{5, 1600, 1200, 85}, {6, 1600, 1200, 100}, {7, 1600, 1200, 120},
/* TW: Clock values for 1920x1440 guessed (except for the first one) */
{1, 1920, 1440, 60}, {2, 1920, 1440, 70}, {3, 1920, 1440, 75}, {4, 1920, 1440, 85},
{5, 1920, 1440,100}, {6, 1920, 1440, 120},
/* TW: Clock values for 2048x1536 guessed */
{1, 2048, 1536, 60}, {2, 2048, 1536, 70}, {3, 2048, 1536, 75}, {4, 2048, 1536, 85},
{5, 2048, 1536,100},
{0, 0, 0, 0}
};
/* Offscreen layout */
......@@ -419,167 +545,150 @@ static SIS_HEAP sisfb_heap;
static struct _sis_TV_filter {
u8 filter[9][4];
} sis_TV_filter[] = {
{ { {
0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_0 */
{
0x00, 0xE0, 0x10, 0x60}, {
0x00, 0xEE, 0x10, 0x44}, {
0x00, 0xF4, 0x10, 0x38}, {
0xF8, 0xF4, 0x18, 0x38}, {
0xFC, 0xFB, 0x14, 0x2A}, {
0x00, 0x00, 0x10, 0x20}, {
0x00, 0x04, 0x10, 0x18}, {
0xFF, 0xFF, 0xFF, 0xFF}}}, { { {
0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_1 */
{
0x00, 0xE0, 0x10, 0x60}, {
0x00, 0xEE, 0x10, 0x44}, {
0x00, 0xF4, 0x10, 0x38}, {
0xF8, 0xF4, 0x18, 0x38}, {
0xFC, 0xFB, 0x14, 0x2A}, {
0x00, 0x00, 0x10, 0x20}, {
0x00, 0x04, 0x10, 0x18}, {
0xFF, 0xFF, 0xFF, 0xFF}}}, { { {
0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_2 */
{
0xF5, 0xEE, 0x1B, 0x44}, {
0xF8, 0xF4, 0x18, 0x38}, {
0xEB, 0x04, 0x25, 0x18}, {
0xF1, 0x05, 0x1F, 0x16}, {
0xF6, 0x06, 0x1A, 0x14}, {
0xFA, 0x06, 0x16, 0x14}, {
0x00, 0x04, 0x10, 0x18}, {
0xFF, 0xFF, 0xFF, 0xFF}}}, { { {
0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_3 */
{
0xF1, 0x04, 0x1F, 0x18}, {
0xEE, 0x0D, 0x22, 0x06}, {
0xF7, 0x06, 0x19, 0x14}, {
0xF4, 0x0B, 0x1C, 0x0A}, {
0xFA, 0x07, 0x16, 0x12}, {
0xF9, 0x0A, 0x17, 0x0C}, {
0x00, 0x07, 0x10, 0x12}, {
0xFF, 0xFF, 0xFF, 0xFF}}}, { { {
0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_4 */
{
0x00, 0xE0, 0x10, 0x60}, {
0x00, 0xEE, 0x10, 0x44}, {
0x00, 0xF4, 0x10, 0x38}, {
0xF8, 0xF4, 0x18, 0x38}, {
0xFC, 0xFB, 0x14, 0x2A}, {
0x00, 0x00, 0x10, 0x20}, {
0x00, 0x04, 0x10, 0x18}, {
0xFF, 0xFF, 0xFF, 0xFF}}}, { { {
0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_5 */
{
0xF5, 0xEE, 0x1B, 0x44}, {
0xF8, 0xF4, 0x18, 0x38}, {
0xEB, 0x04, 0x25, 0x18}, {
0xF1, 0x05, 0x1F, 0x16}, {
0xF6, 0x06, 0x1A, 0x14}, {
0xFA, 0x06, 0x16, 0x14}, {
0x00, 0x04, 0x10, 0x18}, {
0xFF, 0xFF, 0xFF, 0xFF}}}, { { {
0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_6 */
{
0xEB, 0x04, 0x25, 0x18}, {
0xE7, 0x0E, 0x29, 0x04}, {
0xEE, 0x0C, 0x22, 0x08}, {
0xF6, 0x0B, 0x1A, 0x0A}, {
0xF9, 0x0A, 0x17, 0x0C}, {
0xFC, 0x0A, 0x14, 0x0C}, {
0x00, 0x08, 0x10, 0x10}, {
0xFF, 0xFF, 0xFF, 0xFF}}}, { { {
0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_7 */
{
0xEC, 0x02, 0x24, 0x1C}, {
0xF2, 0x04, 0x1E, 0x18}, {
0xEB, 0x15, 0x25, 0xF6}, {
0xF4, 0x10, 0x1C, 0x00}, {
0xF8, 0x0F, 0x18, 0x02}, {
0x00, 0x04, 0x10, 0x18}, {
0x01, 0x06, 0x0F, 0x14}, {
0xFF, 0xFF, 0xFF, 0xFF}}}, { { {
0x00, 0x00, 0x00, 0x40}, /* PALFilter_0 */
{
0x00, 0xE0, 0x10, 0x60}, {
0x00, 0xEE, 0x10, 0x44}, {
0x00, 0xF4, 0x10, 0x38}, {
0xF8, 0xF4, 0x18, 0x38}, {
0xFC, 0xFB, 0x14, 0x2A}, {
0x00, 0x00, 0x10, 0x20}, {
0x00, 0x04, 0x10, 0x18}, {
0xFF, 0xFF, 0xFF, 0xFF}}}, { { {
0x00, 0x00, 0x00, 0x40}, /* PALFilter_1 */
{
0x00, 0xE0, 0x10, 0x60}, {
0x00, 0xEE, 0x10, 0x44}, {
0x00, 0xF4, 0x10, 0x38}, {
0xF8, 0xF4, 0x18, 0x38}, {
0xFC, 0xFB, 0x14, 0x2A}, {
0x00, 0x00, 0x10, 0x20}, {
0x00, 0x04, 0x10, 0x18}, {
0xFF, 0xFF, 0xFF, 0xFF}}}, { { {
0x00, 0x00, 0x00, 0x40}, /* PALFilter_2 */
{
0xF5, 0xEE, 0x1B, 0x44}, {
0xF8, 0xF4, 0x18, 0x38}, {
0xF1, 0xF7, 0x01, 0x32}, {
0xF5, 0xFB, 0x1B, 0x2A}, {
0xF9, 0xFF, 0x17, 0x22}, {
0xFB, 0x01, 0x15, 0x1E}, {
0x00, 0x04, 0x10, 0x18}, {
0xFF, 0xFF, 0xFF, 0xFF}}}, { { {
0x00, 0x00, 0x00, 0x40}, /* PALFilter_3 */
{
0xF5, 0xFB, 0x1B, 0x2A}, {
0xEE, 0xFE, 0x22, 0x24}, {
0xF3, 0x00, 0x1D, 0x20}, {
0xF9, 0x03, 0x17, 0x1A}, {
0xFB, 0x02, 0x14, 0x1E}, {
0xFB, 0x04, 0x15, 0x18}, {
0x00, 0x06, 0x10, 0x14}, {
0xFF, 0xFF, 0xFF, 0xFF}}}, { { {
0x00, 0x00, 0x00, 0x40}, /* PALFilter_4 */
{
0x00, 0xE0, 0x10, 0x60}, {
0x00, 0xEE, 0x10, 0x44}, {
0x00, 0xF4, 0x10, 0x38}, {
0xF8, 0xF4, 0x18, 0x38}, {
0xFC, 0xFB, 0x14, 0x2A}, {
0x00, 0x00, 0x10, 0x20}, {
0x00, 0x04, 0x10, 0x18}, {
0xFF, 0xFF, 0xFF, 0xFF}}}, { { {
0x00, 0x00, 0x00, 0x40}, /* PALFilter_5 */
{
0xF5, 0xEE, 0x1B, 0x44}, {
0xF8, 0xF4, 0x18, 0x38}, {
0xF1, 0xF7, 0x1F, 0x32}, {
0xF5, 0xFB, 0x1B, 0x2A}, {
0xF9, 0xFF, 0x17, 0x22}, {
0xFB, 0x01, 0x15, 0x1E}, {
0x00, 0x04, 0x10, 0x18}, {
0xFF, 0xFF, 0xFF, 0xFF}}}, { { {
0x00, 0x00, 0x00, 0x40}, /* PALFilter_6 */
{
0xF5, 0xEE, 0x1B, 0x2A}, {
0xEE, 0xFE, 0x22, 0x24}, {
0xF3, 0x00, 0x1D, 0x20}, {
0xF9, 0x03, 0x17, 0x1A}, {
0xFB, 0x02, 0x14, 0x1E}, {
0xFB, 0x04, 0x15, 0x18}, {
0x00, 0x06, 0x10, 0x14}, {
0xFF, 0xFF, 0xFF, 0xFF}}}, { { {
0x00, 0x00, 0x00, 0x40}, /* PALFilter_7 */
{
0xF5, 0xEE, 0x1B, 0x44}, {
0xF8, 0xF4, 0x18, 0x38}, {
0xFC, 0xFB, 0x14, 0x2A}, {
0xEB, 0x05, 0x25, 0x16}, {
0xF1, 0x05, 0x1F, 0x16}, {
0xFA, 0x07, 0x16, 0x12}, {
0x00, 0x07, 0x10, 0x12}, {
0xFF, 0xFF, 0xFF, 0xFF}}}
{ {{0x00,0x00,0x00,0x40}, /* NTSCFilter_0 */
{0x00,0xE0,0x10,0x60},
{0x00,0xEE,0x10,0x44},
{0x00,0xF4,0x10,0x38},
{0xF8,0xF4,0x18,0x38},
{0xFC,0xFB,0x14,0x2A},
{0x00,0x00,0x10,0x20},
{0x00,0x04,0x10,0x18},
{0xFF,0xFF,0xFF,0xFF} }},
{ {{0x00,0x00,0x00,0x40}, /* NTSCFilter_1 */
{0x00,0xE0,0x10,0x60},
{0x00,0xEE,0x10,0x44},
{0x00,0xF4,0x10,0x38},
{0xF8,0xF4,0x18,0x38},
{0xFC,0xFB,0x14,0x2A},
{0x00,0x00,0x10,0x20},
{0x00,0x04,0x10,0x18},
{0xFF,0xFF,0xFF,0xFF} }},
{ {{0x00,0x00,0x00,0x40}, /* NTSCFilter_2 */
{0xF5,0xEE,0x1B,0x44},
{0xF8,0xF4,0x18,0x38},
{0xEB,0x04,0x25,0x18},
{0xF1,0x05,0x1F,0x16},
{0xF6,0x06,0x1A,0x14},
{0xFA,0x06,0x16,0x14},
{0x00,0x04,0x10,0x18},
{0xFF,0xFF,0xFF,0xFF} }},
{ {{0x00,0x00,0x00,0x40}, /* NTSCFilter_3 */
{0xF1,0x04,0x1F,0x18},
{0xEE,0x0D,0x22,0x06},
{0xF7,0x06,0x19,0x14},
{0xF4,0x0B,0x1C,0x0A},
{0xFA,0x07,0x16,0x12},
{0xF9,0x0A,0x17,0x0C},
{0x00,0x07,0x10,0x12},
{0xFF,0xFF,0xFF,0xFF} }},
{ {{0x00,0x00,0x00,0x40}, /* NTSCFilter_4 */
{0x00,0xE0,0x10,0x60},
{0x00,0xEE,0x10,0x44},
{0x00,0xF4,0x10,0x38},
{0xF8,0xF4,0x18,0x38},
{0xFC,0xFB,0x14,0x2A},
{0x00,0x00,0x10,0x20},
{0x00,0x04,0x10,0x18},
{0xFF,0xFF,0xFF,0xFF} }},
{ {{0x00,0x00,0x00,0x40}, /* NTSCFilter_5 */
{0xF5,0xEE,0x1B,0x44},
{0xF8,0xF4,0x18,0x38},
{0xEB,0x04,0x25,0x18},
{0xF1,0x05,0x1F,0x16},
{0xF6,0x06,0x1A,0x14},
{0xFA,0x06,0x16,0x14},
{0x00,0x04,0x10,0x18},
{0xFF,0xFF,0xFF,0xFF} }},
{ {{0x00,0x00,0x00,0x40}, /* NTSCFilter_6 */
{0xEB,0x04,0x25,0x18},
{0xE7,0x0E,0x29,0x04},
{0xEE,0x0C,0x22,0x08},
{0xF6,0x0B,0x1A,0x0A},
{0xF9,0x0A,0x17,0x0C},
{0xFC,0x0A,0x14,0x0C},
{0x00,0x08,0x10,0x10},
{0xFF,0xFF,0xFF,0xFF} }},
{ {{0x00,0x00,0x00,0x40}, /* NTSCFilter_7 */
{0xEC,0x02,0x24,0x1C},
{0xF2,0x04,0x1E,0x18},
{0xEB,0x15,0x25,0xF6},
{0xF4,0x10,0x1C,0x00},
{0xF8,0x0F,0x18,0x02},
{0x00,0x04,0x10,0x18},
{0x01,0x06,0x0F,0x14},
{0xFF,0xFF,0xFF,0xFF} }},
{ {{0x00,0x00,0x00,0x40}, /* PALFilter_0 */
{0x00,0xE0,0x10,0x60},
{0x00,0xEE,0x10,0x44},
{0x00,0xF4,0x10,0x38},
{0xF8,0xF4,0x18,0x38},
{0xFC,0xFB,0x14,0x2A},
{0x00,0x00,0x10,0x20},
{0x00,0x04,0x10,0x18},
{0xFF,0xFF,0xFF,0xFF} }},
{ {{0x00,0x00,0x00,0x40}, /* PALFilter_1 */
{0x00,0xE0,0x10,0x60},
{0x00,0xEE,0x10,0x44},
{0x00,0xF4,0x10,0x38},
{0xF8,0xF4,0x18,0x38},
{0xFC,0xFB,0x14,0x2A},
{0x00,0x00,0x10,0x20},
{0x00,0x04,0x10,0x18},
{0xFF,0xFF,0xFF,0xFF} }},
{ {{0x00,0x00,0x00,0x40}, /* PALFilter_2 */
{0xF5,0xEE,0x1B,0x44},
{0xF8,0xF4,0x18,0x38},
{0xF1,0xF7,0x01,0x32},
{0xF5,0xFB,0x1B,0x2A},
{0xF9,0xFF,0x17,0x22},
{0xFB,0x01,0x15,0x1E},
{0x00,0x04,0x10,0x18},
{0xFF,0xFF,0xFF,0xFF} }},
{ {{0x00,0x00,0x00,0x40}, /* PALFilter_3 */
{0xF5,0xFB,0x1B,0x2A},
{0xEE,0xFE,0x22,0x24},
{0xF3,0x00,0x1D,0x20},
{0xF9,0x03,0x17,0x1A},
{0xFB,0x02,0x14,0x1E},
{0xFB,0x04,0x15,0x18},
{0x00,0x06,0x10,0x14},
{0xFF,0xFF,0xFF,0xFF} }},
{ {{0x00,0x00,0x00,0x40}, /* PALFilter_4 */
{0x00,0xE0,0x10,0x60},
{0x00,0xEE,0x10,0x44},
{0x00,0xF4,0x10,0x38},
{0xF8,0xF4,0x18,0x38},
{0xFC,0xFB,0x14,0x2A},
{0x00,0x00,0x10,0x20},
{0x00,0x04,0x10,0x18},
{0xFF,0xFF,0xFF,0xFF} }},
{ {{0x00,0x00,0x00,0x40}, /* PALFilter_5 */
{0xF5,0xEE,0x1B,0x44},
{0xF8,0xF4,0x18,0x38},
{0xF1,0xF7,0x1F,0x32},
{0xF5,0xFB,0x1B,0x2A},
{0xF9,0xFF,0x17,0x22},
{0xFB,0x01,0x15,0x1E},
{0x00,0x04,0x10,0x18},
{0xFF,0xFF,0xFF,0xFF} }},
{ {{0x00,0x00,0x00,0x40}, /* PALFilter_6 */
{0xF5,0xEE,0x1B,0x2A},
{0xEE,0xFE,0x22,0x24},
{0xF3,0x00,0x1D,0x20},
{0xF9,0x03,0x17,0x1A},
{0xFB,0x02,0x14,0x1E},
{0xFB,0x04,0x15,0x18},
{0x00,0x06,0x10,0x14},
{0xFF,0xFF,0xFF,0xFF} }},
{ {{0x00,0x00,0x00,0x40}, /* PALFilter_7 */
{0xF5,0xEE,0x1B,0x44},
{0xF8,0xF4,0x18,0x38},
{0xFC,0xFB,0x14,0x2A},
{0xEB,0x05,0x25,0x16},
{0xF1,0x05,0x1F,0x16},
{0xFA,0x07,0x16,0x12},
{0x00,0x07,0x10,0x12},
{0xFF,0xFF,0xFF,0xFF} }}
};
static int filter = -1;
......@@ -589,101 +698,107 @@ static unsigned char filter_tb;
/* ---------------------- Routine Prototype ------------------------- */
/* Interface used by the world */
int sisfb_setup (char *options);
static int sisfb_get_fix (struct fb_fix_screeninfo *fix, int con,
int sisfb_setup(char *options);
static int sisfb_get_fix(struct fb_fix_screeninfo *fix, int con,
struct fb_info *info);
static int sisfb_get_var(struct fb_var_screeninfo *var, int con,
struct fb_info *info);
static int sisfb_set_var(struct fb_var_screeninfo *var, int con,
struct fb_info *info);
static int sisfb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
struct fb_info *info);
static int sisfb_get_var (struct fb_var_screeninfo *var, int con,
static int sisfb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
struct fb_info *info);
static int sisfb_set_var (struct fb_var_screeninfo *var, int con,
struct fb_info *info);
static int sisfb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
struct fb_info *info);
static int sisfb_setcolreg (unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *fb_info);
static int sisfb_ioctl (struct inode *inode, struct file *file,
unsigned int cmd, unsigned long arg, int con,
struct fb_info *info);
static int sisfb_ioctl(struct inode *inode, struct file *file,
unsigned int cmd, unsigned long arg, int con,
struct fb_info *info);
/* Interface to the low level console driver */
int sisfb_init (void);
static int sisfb_update_var (int con, struct fb_info *info);
static int sisfb_switch (int con, struct fb_info *info);
static int sisfb_blank(int blank, struct fb_info *info);
int sisfb_init(void);
static int sisfb_update_var(int con, struct fb_info *info);
static int sisfb_switch(int con, struct fb_info *info);
static void sisfb_blank(int blank, struct fb_info *info);
/* hardware access routines */
void sisfb_set_reg1 (u16 port, u16 index, u16 data);
void sisfb_set_reg3 (u16 port, u16 data);
void sisfb_set_reg4 (u16 port, unsigned long data);
u8 sisfb_get_reg1 (u16 port, u16 index);
u8 sisfb_get_reg2 (u16 port);
u32 sisfb_get_reg3 (u16 port);
// Eden Chen
//void sisfb_clear_DAC(u16 port);
//void sisfb_clear_buffer(PHW_DEVICE_EXTENSION psishw_ext);
// ~Eden Chen
void sisfb_set_reg1(u16 port, u16 index, u16 data);
void sisfb_set_reg3(u16 port, u16 data);
void sisfb_set_reg4(u16 port, unsigned long data);
u8 sisfb_get_reg1(u16 port, u16 index);
u8 sisfb_get_reg2(u16 port);
u32 sisfb_get_reg3(u16 port);
/* Internal routines */
static void sisfb_search_mode (const char *name);
static void sisfb_validate_mode (void);
static u8 sisfb_search_refresh_rate (unsigned int rate);
static int sis_getcolreg (unsigned regno, unsigned *red, unsigned *green,
unsigned *blue, unsigned *transp,
struct fb_info *fb_info);
static int sisfb_do_set_var (struct fb_var_screeninfo *var, int isactive,
struct fb_info *info);
static void sisfb_set_disp (int con, struct fb_var_screeninfo *var);
static void sisfb_search_mode(const char *name);
static void sisfb_validate_mode(void);
static u8 sisfb_search_refresh_rate(unsigned int rate);
static int sis_getcolreg(unsigned regno, unsigned *red, unsigned *green,
unsigned *blue, unsigned *transp,
struct fb_info *fb_info);
static int sisfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *fb_info);
static int sisfb_do_set_var(struct fb_var_screeninfo *var, int isactive,
struct fb_info *info);
static void sisfb_set_disp(int con, struct fb_var_screeninfo *var);
static void sisfb_do_install_cmap(int con, struct fb_info *info);
/* Chip-dependent Routines */
#ifdef CONFIG_FB_SIS_300
static int sisfb_get_dram_size_300 (void);
//extern BOOLEAN SiSInit300(PHW_DEVICE_EXTENSION HwDeviceExtension);
static void sisfb_detect_VB_connect_300 (void);
static void sisfb_get_VB_type_300 (void);
static int sisfb_has_VB_300 (void);
//extern BOOLEAN SiSSetMode(PHW_DEVICE_EXTENSION HwDeviceExtension,USHORT ModeNo);
static int sisfb_get_dram_size_300(void);
static void sisfb_detect_VB_connect_300(void);
static void sisfb_get_VB_type_300(void);
static int sisfb_has_VB_300(void);
#endif
#ifdef CONFIG_FB_SIS_315
static int sisfb_get_dram_size_315 (void);
//extern BOOLEAN SiSInit310(PHW_DEVICE_EXTENSION HwDeviceExtension);
static void sisfb_detect_VB_connect_315 (void);
static void sisfb_get_VB_type_315 (void);
//extern BOOLEAN SiSSetMode310(PHW_DEVICE_EXTENSION HwDeviceExtension, USHORT ModeNo);
static int sisfb_get_dram_size_315(void);
static void sisfb_detect_VB_connect_315(void);
static void sisfb_get_VB_type_315(void);
static int sisfb_has_VB_315(void);
#endif
/* SetMode routines */
/* Routines from init.c/init301.c */
// Eden Chen
extern BOOLEAN SiSSetMode (PSIS_HW_DEVICE_INFO HwDeviceExtension,
USHORT ModeNo);
extern BOOLEAN SiSInit (PSIS_HW_DEVICE_INFO HwDeviceExtension);
// ~Eden Chen
extern void SiSRegInit(USHORT BaseAddr);
extern BOOLEAN SiSInit(PSIS_HW_DEVICE_INFO HwDeviceExtension);
extern BOOLEAN SiSSetMode(PSIS_HW_DEVICE_INFO HwDeviceExtension, USHORT ModeNo);
extern void SetEnableDstn(void);
static void sisfb_pre_setmode (void);
static void sisfb_post_setmode (void);
static void sisfb_crtc_to_var (struct fb_var_screeninfo *var);
/* TW: Chrontel TV functions */
extern USHORT SiS_IF_DEF_CH70xx;
extern USHORT SiS_GetCH700x(USHORT tempbx);
extern void SiS_SetCH700x(USHORT tempbx);
extern USHORT SiS_GetCH701x(USHORT tempbx);
extern void SiS_SetCH701x(USHORT tempbx);
extern void SiS_SetCH70xxANDOR(USHORT tempax,USHORT tempbh);
extern void SiS_DDC2Delay(USHORT delaytime);
static void sisfb_pre_setmode(void);
static void sisfb_post_setmode(void);
static void sisfb_crtc_to_var(struct fb_var_screeninfo *var);
/* Export functions */
static void sis_get_glyph (struct fb_info *info, SIS_GLYINFO * gly);
void sis_dispinfo (struct ap_data *rec);
void sis_malloc (struct sis_memreq *req);
void sis_free (unsigned long base);
#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,23)
static void sis_get_glyph(SIS_GLYINFO *gly);
#else
static void sis_get_glyph(struct fb_info *info, SIS_GLYINFO *gly);
#endif
void sis_dispinfo(struct ap_data *rec);
void sis_malloc(struct sis_memreq *req);
void sis_free(unsigned long base);
/* heap routines */
static int sisfb_heap_init (void);
static SIS_OH *sisfb_poh_new_node (void);
static SIS_OH *sisfb_poh_allocate (unsigned long size);
static void sisfb_delete_node (SIS_OH * poh);
static void sisfb_insert_node (SIS_OH * pohList, SIS_OH * poh);
static SIS_OH *sisfb_poh_free (unsigned long base);
static void sisfb_free_node (SIS_OH * poh);
static int sisfb_heap_init(void);
static SIS_OH *sisfb_poh_new_node(void);
static SIS_OH *sisfb_poh_allocate(unsigned long size);
static void sisfb_delete_node(SIS_OH *poh);
static void sisfb_insert_node(SIS_OH *pohList, SIS_OH *poh);
static SIS_OH *sisfb_poh_free(unsigned long base);
static void sisfb_free_node(SIS_OH *poh);
/* routines to access PCI configuration space */
BOOLEAN sisfb_query_VGA_config_space (PSIS_HW_DEVICE_INFO psishw_ext,
unsigned long offset, unsigned long set,
unsigned long *value);
BOOLEAN sisfb_query_north_bridge_space (PSIS_HW_DEVICE_INFO psishw_ext,
unsigned long offset, unsigned long set,
unsigned long *value);
BOOLEAN sisfb_query_VGA_config_space(PSIS_HW_DEVICE_INFO psishw_ext,
unsigned long offset, unsigned long set, unsigned long *value);
BOOLEAN sisfb_query_north_bridge_space(PSIS_HW_DEVICE_INFO psishw_ext,
unsigned long offset, unsigned long set, unsigned long *value);
#endif
drivers/video/sis/sisfb.h 0 → 100644
View file @ 4ec16d90
#ifndef _LINUX_SISFB
#define _LINUX_SISFB
#include <asm/ioctl.h>
#include <asm/types.h>
#define DISPTYPE_CRT1 0x00000008L
#define DISPTYPE_CRT2 0x00000004L
#define DISPTYPE_LCD 0x00000002L
#define DISPTYPE_TV 0x00000001L
#define DISPTYPE_DISP1 DISPTYPE_CRT1
#define DISPTYPE_DISP2 (DISPTYPE_CRT2 | DISPTYPE_LCD | DISPTYPE_TV)
#define DISPMODE_SINGLE 0x00000020L
#define DISPMODE_MIRROR 0x00000010L
#define DISPMODE_DUALVIEW 0x00000040L
#define HASVB_NONE 0x00
#define HASVB_301 0x01
#define HASVB_LVDS 0x02
#define HASVB_TRUMPION 0x04
#define HASVB_LVDS_CHRONTEL 0x10
#define HASVB_302 0x20
#define HASVB_303 0x40
#define HASVB_CHRONTEL 0x80
/* TW: *Never* change the order of the following enum */
typedef enum _SIS_CHIP_TYPE {
SIS_VGALegacy = 0,
SIS_300,
SIS_630,
SIS_540,
SIS_730,
SIS_315H,
SIS_315,
SIS_550,
SIS_315PRO,
SIS_640,
SIS_740,
SIS_650,
SIS_330,
MAX_SIS_CHIP
} SIS_CHIP_TYPE;
typedef enum _TVTYPE {
TVMODE_NTSC = 0,
TVMODE_PAL,
TVMODE_HIVISION,
TVMODE_TOTAL
} SIS_TV_TYPE;
typedef enum _TVPLUGTYPE {
TVPLUG_Legacy = 0,
TVPLUG_COMPOSITE,
TVPLUG_SVIDEO,
TVPLUG_SCART,
TVPLUG_TOTAL
} SIS_TV_PLUG;
struct sis_memreq {
unsigned long offset;
unsigned long size;
};
struct mode_info {
int bpp;
int xres;
int yres;
int v_xres;
int v_yres;
int org_x;
int org_y;
unsigned int vrate;
};
struct ap_data {
struct mode_info minfo;
unsigned long iobase;
unsigned int mem_size;
unsigned long disp_state;
SIS_CHIP_TYPE chip;
unsigned char hasVB;
SIS_TV_TYPE TV_type;
SIS_TV_PLUG TV_plug;
unsigned long version;
char reserved[256];
};
struct video_info {
int chip_id;
unsigned int video_size;
unsigned long video_base;
char *video_vbase;
unsigned long mmio_base;
char *mmio_vbase;
unsigned long vga_base;
unsigned long mtrr;
unsigned long heapstart;
int video_bpp;
int video_width;
int video_height;
int video_vwidth;
int video_vheight;
int org_x;
int org_y;
unsigned int refresh_rate;
unsigned long disp_state;
unsigned char hasVB;
unsigned char TV_type;
unsigned char TV_plug;
SIS_CHIP_TYPE chip;
unsigned char revision_id;
char reserved[256];
};
/* TW: Addtional IOCTL for communication sisfb <> X driver */
/* If changing this, vgatypes.h must also be changed (for X driver) */
/* TW: ioctl for identifying and giving some info (esp. memory heap start) */
#define SISFB_GET_INFO _IOR('n',0xF8,sizeof(__u32))
/* TW: Structure argument for SISFB_GET_INFO ioctl */
typedef struct _SISFB_INFO sisfb_info, *psisfb_info;
struct _SISFB_INFO {
unsigned long sisfb_id; /* for identifying sisfb */
#ifndef SISFB_ID
#define SISFB_ID 0x53495346 /* Identify myself with 'SISF' */
#endif
int chip_id; /* PCI ID of detected chip */
int memory; /* video memory in KB which sisfb manages */
int heapstart; /* heap start (= sisfb "mem" argument) in KB */
unsigned char fbvidmode; /* current sisfb mode */
unsigned char sisfb_version;
unsigned char sisfb_revision;
unsigned char sisfb_patchlevel;
char reserved[253]; /* for future use */
};
#ifdef __KERNEL__
extern struct video_info ivideo;
extern void sis_malloc(struct sis_memreq *req);
extern void sis_free(unsigned long base);
extern void sis_dispinfo(struct ap_data *rec);
#endif
#endif
drivers/video/sis/vgatypes.h
View file @ 4ec16d90
#ifndef _VGATYPES_
#define _VGATYPES_
#ifdef LINUX_XF86
#include "xf86Pci.h"
#endif
#ifdef LINUX_KERNEL /* TW: We don't want the X driver to depend on kernel source */
#include <linux/ioctl.h>
#endif
#ifndef TC
#define far
#endif
......@@ -26,7 +34,7 @@ typedef short SHORT;
#endif
#ifndef LONG
typedef long LONG;
typedef long LONG;
#endif
#ifndef UCHAR
......@@ -68,27 +76,52 @@ typedef UCHAR BOOLEAN;
#ifndef bool
typedef UCHAR bool;
#endif
#endif /* WINCE_HEADER */
#endif /*WINCE_HEADER*/
#ifndef VBIOS_VER_MAX_LENGTH
#define VBIOS_VER_MAX_LENGTH 4
#endif
#ifndef LINUX_KERNEL /* For kernel, this is defined in sisfb.h */
#ifndef WIN2000
#ifndef SIS_CHIP_TYPE
typedef enum _SIS_CHIP_TYPE {
SIS_VGALegacy = 0,
#ifdef LINUX_XF86
SIS_530, /* TW */
SIS_OLD, /* TW */
#endif
SIS_300,
SIS_630,
SIS_730,
SIS_540,
SIS_315H, /* SiS 310 */
SIS_315,
SIS_315PRO, /* SiS 325 */
SIS_550,
SIS_640,
SIS_740,
SIS_650,
SIS_330,
MAX_SIS_CHIP
} SIS_CHIP_TYPE;
#endif
#endif
#endif
#ifndef WIN2000
#ifndef SIS_VB_CHIP_TYPE
typedef enum _SIS_VB_CHIP_TYPE {
VB_CHIP_Legacy = 0,
VB_CHIP_301,
VB_CHIP_301B,
VB_CHIP_301BLCD,
VB_CHIP_301BTV,
VB_CHIP_302,
VB_CHIP_302B,
VB_CHIP_302BLCD,
VB_CHIP_302BTV,
VB_CHIP_303,
VB_CHIP_UNKNOWN, /* other video bridge or no video bridge */
MAX_VB_CHIP
VB_CHIP_Legacy = 0,
VB_CHIP_301,
VB_CHIP_301B,
VB_CHIP_301LV,
VB_CHIP_302,
VB_CHIP_302B,
VB_CHIP_302LV,
VB_CHIP_303,
VB_CHIP_UNKNOWN, /* other video bridge or no video bridge */
MAX_VB_CHIP
} SIS_VB_CHIP_TYPE;
#endif
#endif
......@@ -96,125 +129,169 @@ typedef enum _SIS_VB_CHIP_TYPE {
#ifndef WIN2000
#ifndef SIS_LCD_TYPE
typedef enum _SIS_LCD_TYPE {
LCD_INVALID = 0,
LCD_800x600,
LCD_1024x768,
LCD_1280x1024,
LCD_1280x960,
LCD_640x480,
LCD_1600x1200,
LCD_1920x1440,
LCD_2048x1536,
LCD_UNKNOWN
LCD_INVALID = 0,
LCD_800x600,
LCD_1024x768,
LCD_1280x1024,
LCD_1280x960,
LCD_640x480,
LCD_1600x1200,
LCD_1920x1440,
LCD_2048x1536,
LCD_320x480, /* TW: FSTN */
LCD_1400x1050,
LCD_1152x864,
LCD_1152x768,
LCD_1280x768,
LCD_1024x600,
LCD_UNKNOWN
} SIS_LCD_TYPE;
#endif
#endif
#ifndef WIN2000 /* mark by Paul ,Move definition to sisv.h */
#ifndef WIN2000 /* mark by Paul, Move definition to sisv.h*/
#ifndef PSIS_DSReg
typedef struct _SIS_DSReg {
UCHAR jIdx;
UCHAR jVal;
typedef struct _SIS_DSReg
{
UCHAR jIdx;
UCHAR jVal;
} SIS_DSReg, *PSIS_DSReg;
#endif
#ifndef SIS_HW_DEVICE_INFO
typedef struct _SIS_HW_DEVICE_INFO SIS_HW_DEVICE_INFO, *PSIS_HW_DEVICE_INFO;
typedef BOOLEAN (*PSIS_QUERYSPACE) (PSIS_HW_DEVICE_INFO, ULONG, ULONG, ULONG *);
struct _SIS_HW_DEVICE_INFO {
PVOID pDevice; /* The pointer to the physical device data structure
in each OS or NULL for unused. */
UCHAR *pjVirtualRomBase; /* Only for NT, NULL for WinCE & Linux. */
/* base virtual address of VBIOS ROM Space */
/* or base virtual address of ROM image file. */
/* if NULL, then read from pjROMImage; */
/* Note:ROM image file is the file of VBIOS ROM */
UCHAR *pjCustomizedROMImage; /* base virtual address of ROM image file. */
/* wincE:ROM image file is the file for OEM */
/* customized table */
/* Linux: not used */
/* NT : not used */
/* Note : pjCustomizedROMImage=NULL if no ROM image file */
UCHAR *pjVideoMemoryAddress; /* base virtual memory address */
/* of Linear VGA memory */
ULONG ulVideoMemorySize; /* size, in bytes, of the memory on the board */
ULONG ulIOAddress; /* base I/O address of VGA ports (0x3B0) */
UCHAR jChipType; /* Used to Identify SiS Graphics Chip */
/* defined in the data structure type */
/* "SIS_CHIP_TYPE" */
UCHAR jChipRevision; /* Used to Identify SiS Graphics Chip Revision */
UCHAR ujVBChipID; /* the ID of video bridge */
/* defined in the data structure type */
/* "SIS_VB_CHIP_TYPE" */
USHORT usExternalChip; /* NO VB or other video bridge(not */
/* SiS video bridge) */
/* if ujVBChipID = VB_CHIP_UNKNOWN, */
/* then bit0=1 : LVDS,bit1=1 : trumpion, */
/* bit2=1 : CH7005 & no video bridge if */
/* usExternalChip = 0. */
/* Note: CR37[3:1]: */
/* 001:SiS 301 */
/* 010:LVDS */
/* 011:Trumpion LVDS Scaling Chip */
/* 100:LVDS(LCD-out)+Chrontel 7005 */
/* 101:Single Chrontel 7005 */
ULONG ulCRT2LCDType; /* defined in the data structure type */
/* "SIS_LCD_TYPE" */
BOOLEAN bIntegratedMMEnabled; /* supporting integration MM enable */
BOOLEAN bSkipDramSizing; /* True: Skip video memory sizing. */
PSIS_DSReg pSR; /* restore SR registers in initial function. */
/* end data :(idx, val) = (FF, FF). */
/* Note : restore SR registers if */
/* bSkipDramSizing = TRUE */
PSIS_DSReg pCR; /* restore CR registers in initial function. */
/* end data :(idx, val) = (FF, FF) */
/* Note : restore cR registers if */
/* bSkipDramSizing = TRUE */
PSIS_QUERYSPACE pQueryVGAConfigSpace; /* Get/Set VGA Configuration */
/* space */
PSIS_QUERYSPACE pQueryNorthBridgeSpace; /* Get/Set North Bridge */
/* space */
UCHAR szVBIOSVer[VBIOS_VER_MAX_LENGTH];
typedef struct _SIS_HW_DEVICE_INFO SIS_HW_DEVICE_INFO, *PSIS_HW_DEVICE_INFO;
typedef BOOLEAN (*PSIS_QUERYSPACE) (PSIS_HW_DEVICE_INFO, ULONG, ULONG, ULONG *);
struct _SIS_HW_DEVICE_INFO
{
PVOID pDevice; /* The pointer to the physical device data structure
in each OS or NULL for unused. */
UCHAR *pjVirtualRomBase; /* base virtual address of VBIOS ROM Space */
/* or base virtual address of ROM image file. */
/* if NULL, then read from pjROMImage; */
/* Note:ROM image file is the file of VBIOS ROM */
UCHAR *pjCustomizedROMImage;/* base virtual address of ROM image file. */
/* wincE:ROM image file is the file for OEM */
/* customized table */
/* Linux: not used */
/* NT : not used */
/* Note : pjCustomizedROMImage=NULL if no ROM image file */
UCHAR *pjVideoMemoryAddress;/* base virtual memory address */
/* of Linear VGA memory */
ULONG ulVideoMemorySize; /* size, in bytes, of the memory on the board */
ULONG ulIOAddress; /* base I/O address of VGA ports (0x3B0) */
UCHAR jChipType; /* Used to Identify SiS Graphics Chip */
/* defined in the data structure type */
/* "SIS_CHIP_TYPE" */
UCHAR jChipRevision; /* Used to Identify SiS Graphics Chip Revision */
UCHAR ujVBChipID; /* the ID of video bridge */
/* defined in the data structure type */
/* "SIS_VB_CHIP_TYPE" */
USHORT usExternalChip; /* NO VB or other video bridge(not */
/* SiS video bridge) */
/* if ujVBChipID = VB_CHIP_UNKNOWN, */
/* then bit0=1 : LVDS,bit1=1 : trumpion, */
/* bit2=1 : CH7005 & no video bridge if */
/* usExternalChip = 0. */
/* Note: CR37[3:1]: */
/* 001:SiS 301 */
/* 010:LVDS */
/* 011:Trumpion LVDS Scaling Chip */
/* 100:LVDS(LCD-out)+Chrontel 7005 */
/* 101:Single Chrontel 7005 */
ULONG ulCRT2LCDType; /* defined in the data structure type */
/* "SIS_LCD_TYPE" */
BOOLEAN bIntegratedMMEnabled;/* supporting integration MM enable */
BOOLEAN bSkipDramSizing; /* True: Skip video memory sizing. */
PSIS_DSReg pSR; /* restore SR registers in initial function. */
/* end data :(idx, val) = (FF, FF). */
/* Note : restore SR registers if */
/* bSkipDramSizing = TRUE */
PSIS_DSReg pCR; /* restore CR registers in initial function. */
/* end data :(idx, val) = (FF, FF) */
/* Note : restore cR registers if */
/* bSkipDramSizing = TRUE */
PSIS_QUERYSPACE pQueryVGAConfigSpace; /* Get/Set VGA Configuration */
/* space */
PSIS_QUERYSPACE pQueryNorthBridgeSpace;/* Get/Set North Bridge */
/* space */
UCHAR szVBIOSVer[VBIOS_VER_MAX_LENGTH];
UCHAR pdc; /* TW: PanelDelayCompensation */
#ifdef LINUX_XF86
PCITAG PciTag; /* PCI Tag for Linux XF86 */
#endif
};
#endif
#endif /*~ mark by Paul ,Move definition to sisv.h */
/* TW: Addtional IOCTL for communication sisfb <> X driver */
/* If changing this, sisfb.h must also be changed (for sisfb) */
#ifdef LINUX_XF86 /* We don't want the X driver to depend on the kernel source */
/* TW: ioctl for identifying and giving some info (esp. memory heap start) */
#define SISFB_GET_INFO 0x80046ef8 /* Wow, what a terrible hack... */
/* TW: Structure argument for SISFB_GET_INFO ioctl */
typedef struct _SISFB_INFO sisfb_info, *psisfb_info;
struct _SISFB_INFO {
unsigned long sisfb_id; /* for identifying sisfb */
#ifndef SISFB_ID
#define SISFB_ID 0x53495346 /* Identify myself with 'SISF' */
#endif
int chip_id; /* PCI ID of detected chip */
int memory; /* video memory in KB which sisfb manages */
int heapstart; /* heap start (= sisfb "mem" argument) in KB */
unsigned char fbvidmode; /* current sisfb mode */
unsigned char sisfb_version;
unsigned char sisfb_revision;
unsigned char sisfb_patchlevel;
char reserved[253]; /* for future use */
};
#endif
#endif /*~ mark by Paul ,Move definition to sisv.h */
#ifndef WIN2000
#ifndef WINCE_HEADER
#ifndef BUS_DATA_TYPE
typedef enum _BUS_DATA_TYPE {
ConfigurationSpaceUndefined = -1,
Cmos,
EisaConfiguration,
Pos,
CbusConfiguration,
PCIConfiguration,
VMEConfiguration,
NuBusConfiguration,
PCMCIAConfiguration,
MPIConfiguration,
MPSAConfiguration,
PNPISAConfiguration,
MaximumBusDataType
ConfigurationSpaceUndefined = -1,
Cmos,
EisaConfiguration,
Pos,
CbusConfiguration,
PCIConfiguration,
VMEConfiguration,
NuBusConfiguration,
PCMCIAConfiguration,
MPIConfiguration,
MPSAConfiguration,
PNPISAConfiguration,
MaximumBusDataType
} BUS_DATA_TYPE, *PBUS_DATA_TYPE;
#endif
#endif /* WINCE_HEADER */
#endif /* WINCE_HEADER */
#ifndef PCI_TYPE0_ADDRESSES
#define PCI_TYPE0_ADDRESSES 6
......@@ -227,41 +304,42 @@ typedef enum _BUS_DATA_TYPE {
#ifndef WINCE_HEADER
#ifndef PCI_COMMON_CONFIG
typedef struct _PCI_COMMON_CONFIG {
USHORT VendorID; /* (ro) */
USHORT DeviceID; /* (ro) */
USHORT Command; /* Device control */
USHORT Status;
UCHAR RevisionID; /* (ro) */
UCHAR ProgIf; /* (ro) */
UCHAR SubClass; /* (ro) */
UCHAR BaseClass; /* (ro) */
UCHAR CacheLineSize; /* (ro+) */
UCHAR LatencyTimer; /* (ro+) */
UCHAR HeaderType; /* (ro) */
UCHAR BIST; /* Built in self test */
union {
struct _PCI_HEADER_TYPE_0 {
ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
ULONG CIS;
USHORT SubVendorID;
USHORT SubSystemID;
ULONG ROMBaseAddress;
ULONG Reserved2[2];
UCHAR InterruptLine; /* */
UCHAR InterruptPin; /* (ro) */
UCHAR MinimumGrant; /* (ro) */
UCHAR MaximumLatency; /* (ro) */
} type0;
} u;
UCHAR DeviceSpecific[192];
USHORT VendorID; /* (ro) */
USHORT DeviceID; /* (ro) */
USHORT Command; /* Device control */
USHORT Status;
UCHAR RevisionID; /* (ro) */
UCHAR ProgIf; /* (ro) */
UCHAR SubClass; /* (ro) */
UCHAR BaseClass; /* (ro) */
UCHAR CacheLineSize; /* (ro+) */
UCHAR LatencyTimer; /* (ro+) */
UCHAR HeaderType; /* (ro) */
UCHAR BIST; /* Built in self test */
union {
struct _PCI_HEADER_TYPE_0 {
ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
ULONG CIS;
USHORT SubVendorID;
USHORT SubSystemID;
ULONG ROMBaseAddress;
ULONG Reserved2[2];
UCHAR InterruptLine; /* */
UCHAR InterruptPin; /* (ro) */
UCHAR MinimumGrant; /* (ro) */
UCHAR MaximumLatency; /* (ro) */
} type0;
} u;
UCHAR DeviceSpecific[192];
} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
#endif
#endif /* WINCE_HEADER */
#endif /* WINCE_HEADER */
#ifndef FIELD_OFFSET
#define FIELD_OFFSET(type, field) ((LONG)&(((type *)0)->field))
......
drivers/video/sis/vstruct.h
View file @ 4ec16d90
......@@ -2,13 +2,15 @@
#define EXTERN
#else
#define EXTERN extern
#endif /* _INIT_ */
#endif /* _INIT_ */
typedef struct _SiS_PanelDelayTblStruct {
UCHAR timer[2];
typedef struct _SiS_PanelDelayTblStruct
{
UCHAR timer[2];
} SiS_PanelDelayTblStruct;
typedef struct _SiS_LCDDataStruct {
typedef struct _SiS_LCDDataStruct
{
USHORT RVBHCMAX;
USHORT RVBHCFACT;
USHORT VGAHT;
......@@ -17,7 +19,8 @@ typedef struct _SiS_LCDDataStruct {
USHORT LCDVT;
} SiS_LCDDataStruct;
typedef struct _SiS_TVDataStruct {
typedef struct _SiS_TVDataStruct
{
USHORT RVBHCMAX;
USHORT RVBHCFACT;
USHORT VGAHT;
......@@ -33,32 +36,38 @@ typedef struct _SiS_TVDataStruct {
UCHAR RY4COE;
} SiS_TVDataStruct;
typedef struct _SiS_LVDSDataStruct {
typedef struct _SiS_LVDSDataStruct
{
USHORT VGAHT;
USHORT VGAVT;
USHORT LCDHT;
USHORT LCDVT;
} SiS_LVDSDataStruct;
typedef struct _SiS_LVDSDesStruct {
typedef struct _SiS_LVDSDesStruct
{
USHORT LCDHDES;
USHORT LCDVDES;
} SiS_LVDSDesStruct;
typedef struct _SiS_LVDSCRT1DataStruct {
typedef struct _SiS_LVDSCRT1DataStruct
{
UCHAR CR[15];
} SiS_LVDSCRT1DataStruct;
/*add for LCDA*/
typedef struct _SiS_LCDACRT1DataStruct {
typedef struct _SiS_LCDACRT1DataStruct
{
UCHAR CR[17];
} SiS_LCDACRT1DataStruct;
typedef struct _SiS_CHTVRegDataStruct {
UCHAR Reg[5];
typedef struct _SiS_CHTVRegDataStruct
{
UCHAR Reg[16];
} SiS_CHTVRegDataStruct;
typedef struct _SiS_StStruct {
typedef struct _SiS_StStruct
{
UCHAR St_ModeID;
USHORT St_ModeFlag;
UCHAR St_StTableIndex;
......@@ -69,18 +78,20 @@ typedef struct _SiS_StStruct {
UCHAR VB_StTVYFilterIndex;
} SiS_StStruct;
typedef struct _SiS_VBModeStruct {
UCHAR ModeID;
UCHAR VB_TVDelayIndex;
UCHAR VB_TVFlickerIndex;
UCHAR VB_TVPhaseIndex;
UCHAR VB_TVYFilterIndex;
UCHAR VB_LCDDelayIndex;
UCHAR _VB_LCDHIndex;
UCHAR _VB_LCDVIndex;
typedef struct _SiS_VBModeStruct
{
UCHAR ModeID;
UCHAR VB_TVDelayIndex;
UCHAR VB_TVFlickerIndex;
UCHAR VB_TVPhaseIndex;
UCHAR VB_TVYFilterIndex;
UCHAR VB_LCDDelayIndex;
UCHAR _VB_LCDHIndex;
UCHAR _VB_LCDVIndex;
} SiS_VBModeStruct;
typedef struct _SiS_StandTableStruct {
typedef struct _SiS_StandTableStruct
{
UCHAR CRT_COLS;
UCHAR ROWS;
UCHAR CHAR_HEIGHT;
......@@ -92,7 +103,8 @@ typedef struct _SiS_StandTableStruct {
UCHAR GRC[9];
} SiS_StandTableStruct;
typedef struct _SiS_ExtStruct {
typedef struct _SiS_ExtStruct
{
UCHAR Ext_ModeID;
USHORT Ext_ModeFlag;
USHORT Ext_ModeInfo;
......@@ -106,65 +118,79 @@ typedef struct _SiS_ExtStruct {
UCHAR REFindex;
} SiS_ExtStruct;
typedef struct _SiS_Ext2Struct {
typedef struct _SiS_Ext2Struct
{
USHORT Ext_InfoFlag;
UCHAR Ext_CRT1CRTC;
UCHAR Ext_CRTVCLK;
UCHAR Ext_CRT2CRTC;
UCHAR ModeID;
UCHAR ModeID;
USHORT XRes;
USHORT YRes;
USHORT ROM_OFFSET;
} SiS_Ext2Struct;
typedef struct _SiS_CRT1TableStruct {
typedef struct _SiS_Part2PortTblStruct
{
UCHAR CR[12];
} SiS_Part2PortTblStruct;
typedef struct _SiS_CRT1TableStruct
{
UCHAR CR[17];
} SiS_CRT1TableStruct;
typedef struct _SiS_MCLKDataStruct {
UCHAR SR28, SR29, SR2A;
typedef struct _SiS_MCLKDataStruct
{
UCHAR SR28,SR29,SR2A;
USHORT CLOCK;
} SiS_MCLKDataStruct;
typedef struct _SiS_ECLKDataStruct {
UCHAR SR2E, SR2F, SR30;
typedef struct _SiS_ECLKDataStruct
{
UCHAR SR2E,SR2F,SR30;
USHORT CLOCK;
} SiS_ECLKDataStruct;
typedef struct _SiS_VCLKDataStruct {
UCHAR SR2B, SR2C;
typedef struct _SiS_VCLKDataStruct
{
UCHAR SR2B,SR2C;
USHORT CLOCK;
} SiS_VCLKDataStruct;
typedef struct _SiS_VBVCLKDataStruct {
UCHAR Part4_A, Part4_B;
typedef struct _SiS_VBVCLKDataStruct
{
UCHAR Part4_A,Part4_B;
USHORT CLOCK;
} SiS_VBVCLKDataStruct;
typedef struct _SiS_StResInfoStruct {
typedef struct _SiS_StResInfoStruct
{
USHORT HTotal;
USHORT VTotal;
} SiS_StResInfoStruct;
typedef struct _SiS_ModeResInfoStruct {
typedef struct _SiS_ModeResInfoStruct
{
USHORT HTotal;
USHORT VTotal;
UCHAR XChar;
UCHAR YChar;
UCHAR XChar;
UCHAR YChar;
} SiS_ModeResInfoStruct;
EXTERN SiS_StStruct *SiS_SModeIDTable;
EXTERN SiS_StandTableStruct *SiS_StandTable;
EXTERN SiS_ExtStruct *SiS_EModeIDTable;
EXTERN SiS_Ext2Struct *SiS_RefIndex;
EXTERN SiS_ExtStruct *SiS_EModeIDTable;
EXTERN SiS_Ext2Struct *SiS_RefIndex;
EXTERN SiS_VBModeStruct *SiS_VBModeIDTable;
EXTERN SiS_CRT1TableStruct *SiS_CRT1Table;
EXTERN SiS_MCLKDataStruct *SiS_MCLKData;
EXTERN SiS_ECLKDataStruct *SiS_ECLKData;
EXTERN SiS_VCLKDataStruct *SiS_VCLKData;
EXTERN SiS_VBVCLKDataStruct *SiS_VBVCLKData;
EXTERN SiS_StResInfoStruct *SiS_StResInfo;
EXTERN SiS_ModeResInfoStruct *SiS_ModeResInfo;
EXTERN SiS_CRT1TableStruct *SiS_CRT1Table;
EXTERN SiS_MCLKDataStruct *SiS_MCLKData_0;
EXTERN SiS_MCLKDataStruct *SiS_MCLKData_1;
EXTERN SiS_ECLKDataStruct *SiS_ECLKData;
EXTERN SiS_VCLKDataStruct *SiS_VCLKData;
EXTERN SiS_VBVCLKDataStruct *SiS_VBVCLKData;
EXTERN SiS_StResInfoStruct *SiS_StResInfo;
EXTERN SiS_ModeResInfoStruct *SiS_ModeResInfo;
EXTERN UCHAR *SiS_ScreenOffset;
EXTERN UCHAR *pSiS_OutputSelect;
......@@ -172,8 +198,8 @@ EXTERN UCHAR *pSiS_SoftSetting;
EXTERN UCHAR *pSiS_SR07;
typedef UCHAR DRAM4Type[4];
EXTERN DRAM4Type *SiS_SR15; /* pointer : point to array */
EXTERN DRAM4Type *SiS_CR40; /* pointer : point to array */
EXTERN DRAM4Type *SiS_SR15; /* pointer : point to array */
EXTERN DRAM4Type *SiS_CR40; /* pointer : point to array */
EXTERN UCHAR *SiS_CR49;
EXTERN UCHAR *SiS_SR25;
......@@ -192,7 +218,7 @@ EXTERN UCHAR *pSiS_CRT2Data_4_10;
EXTERN USHORT *pSiS_RGBSenseData;
EXTERN USHORT *pSiS_VideoSenseData;
EXTERN USHORT *pSiS_YCSenseData;
EXTERN USHORT *pSiS_RGBSenseData2; /*301b */
EXTERN USHORT *pSiS_RGBSenseData2; /*301b*/
EXTERN USHORT *pSiS_VideoSenseData2;
EXTERN USHORT *pSiS_YCSenseData2;
......@@ -202,21 +228,24 @@ EXTERN UCHAR *SiS_NTSCPhase2;
EXTERN UCHAR *SiS_PALPhase2;
EXTERN UCHAR *SiS_PALMPhase;
EXTERN UCHAR *SiS_PALNPhase;
EXTERN SiS_LCDDataStruct *SiS_StLCD1024x768Data;
EXTERN SiS_LCDDataStruct *SiS_ExtLCD1024x768Data;
EXTERN SiS_LCDDataStruct *SiS_St2LCD1024x768Data;
EXTERN SiS_LCDDataStruct *SiS_StLCD1280x1024Data;
EXTERN SiS_LCDDataStruct *SiS_ExtLCD1280x1024Data;
EXTERN SiS_LCDDataStruct *SiS_St2LCD1280x1024Data;
EXTERN SiS_LCDDataStruct *SiS_NoScaleData;
EXTERN SiS_LCDDataStruct *SiS_LCD1280x960Data;
EXTERN SiS_TVDataStruct *SiS_StPALData;
EXTERN SiS_TVDataStruct *SiS_ExtPALData;
EXTERN SiS_TVDataStruct *SiS_StNTSCData;
EXTERN SiS_TVDataStruct *SiS_ExtNTSCData;
EXTERN SiS_TVDataStruct *SiS_St1HiTVData;
EXTERN SiS_TVDataStruct *SiS_St2HiTVData;
EXTERN SiS_TVDataStruct *SiS_ExtHiTVData;
EXTERN UCHAR *SiS_PALMPhase2;
EXTERN UCHAR *SiS_PALNPhase2;
EXTERN SiS_LCDDataStruct *SiS_StLCD1024x768Data;
EXTERN SiS_LCDDataStruct *SiS_ExtLCD1024x768Data;
EXTERN SiS_LCDDataStruct *SiS_St2LCD1024x768Data;
EXTERN SiS_LCDDataStruct *SiS_StLCD1280x1024Data;
EXTERN SiS_LCDDataStruct *SiS_ExtLCD1280x1024Data;
EXTERN SiS_LCDDataStruct *SiS_St2LCD1280x1024Data;
EXTERN SiS_LCDDataStruct *SiS_NoScaleData1024x768;
EXTERN SiS_LCDDataStruct *SiS_NoScaleData1280x1024;
EXTERN SiS_LCDDataStruct *SiS_LCD1280x960Data;
EXTERN SiS_TVDataStruct *SiS_StPALData;
EXTERN SiS_TVDataStruct *SiS_ExtPALData;
EXTERN SiS_TVDataStruct *SiS_StNTSCData;
EXTERN SiS_TVDataStruct *SiS_ExtNTSCData;
EXTERN SiS_TVDataStruct *SiS_St1HiTVData;
EXTERN SiS_TVDataStruct *SiS_St2HiTVData;
EXTERN SiS_TVDataStruct *SiS_ExtHiTVData;
EXTERN UCHAR *SiS_NTSCTiming;
EXTERN UCHAR *SiS_PALTiming;
EXTERN UCHAR *SiS_HiTVExtTiming;
......@@ -228,91 +257,125 @@ EXTERN UCHAR *SiS_HiTVGroup3Simu;
EXTERN UCHAR *SiS_HiTVGroup3Text;
EXTERN SiS_PanelDelayTblStruct *SiS_PanelDelayTbl;
EXTERN SiS_LVDSDataStruct *SiS_LVDS800x600Data_1;
EXTERN SiS_LVDSDataStruct *SiS_LVDS800x600Data_2;
EXTERN SiS_LVDSDataStruct *SiS_LVDS1024x768Data_1;
EXTERN SiS_LVDSDataStruct *SiS_LVDS1024x768Data_2;
EXTERN SiS_LVDSDataStruct *SiS_LVDS1280x1024Data_1;
EXTERN SiS_LVDSDataStruct *SiS_LVDS1280x1024Data_2;
EXTERN SiS_LVDSDataStruct *SiS_LVDS640x480Data_1;
EXTERN SiS_LVDSDataStruct *SiS_CHTVUNTSCData;
EXTERN SiS_LVDSDataStruct *SiS_CHTVONTSCData;
EXTERN SiS_LVDSDataStruct *SiS_CHTVUPALData;
EXTERN SiS_LVDSDataStruct *SiS_CHTVOPALData;
EXTERN SiS_LVDSDesStruct *SiS_PanelType00_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType01_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType02_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType03_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType04_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType05_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType06_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType07_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType08_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType09_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0a_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0b_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0c_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0d_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0e_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0f_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType00_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType01_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType02_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType03_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType04_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType05_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType06_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType07_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType08_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType09_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0a_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0b_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0c_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0d_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0e_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0f_2;
/*301b*/
EXTERN SiS_LVDSDesStruct *LVDS1024x768Des_1;
EXTERN SiS_LVDSDesStruct *LVDS1280x1024Des_1;
EXTERN SiS_LVDSDesStruct *LVDS1280x960Des_1;
EXTERN SiS_LVDSDesStruct *LVDS1024x768Des_2;
EXTERN SiS_LVDSDesStruct *LVDS1280x1024Des_2;
EXTERN SiS_LVDSDesStruct *LVDS1280x960Des_2;
/*end 301b*/
EXTERN SiS_LVDSDesStruct *SiS_CHTVUNTSCDesData;
EXTERN SiS_LVDSDesStruct *SiS_CHTVONTSCDesData;
EXTERN SiS_LVDSDesStruct *SiS_CHTVUPALDesData;
EXTERN SiS_LVDSDesStruct *SiS_CHTVOPALDesData;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT1800x600_1;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11024x768_1;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11280x1024_1;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT1800x600_1_H;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11024x768_1_H;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11280x1024_1_H;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT1800x600_2;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11024x768_2;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11280x1024_2;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT1800x600_2_H;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11024x768_2_H;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11280x1024_2_H;
EXTERN SiS_LVDSCRT1DataStruct *SiS_CHTVCRT1UNTSC;
EXTERN SiS_LVDSCRT1DataStruct *SiS_CHTVCRT1ONTSC;
EXTERN SiS_LVDSCRT1DataStruct *SiS_CHTVCRT1UPAL;
EXTERN SiS_LVDSCRT1DataStruct *SiS_CHTVCRT1OPAL;
/*add for LCDA*/
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT1800x600_1;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT11024x768_1;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT11280x1024_1;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT1800x600_1_H;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT11024x768_1_H;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT11280x1024_1_H;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT1800x600_2;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT11024x768_2;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT11280x1024_2;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT1800x600_2_H;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT11024x768_2_H;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT11280x1024_2_H;
/*end 301b*/
EXTERN SiS_PanelDelayTblStruct *SiS_PanelDelayTblLVDS;
EXTERN SiS_LVDSDataStruct *SiS_LVDS800x600Data_1;
EXTERN SiS_LVDSDataStruct *SiS_LVDS800x600Data_2;
EXTERN SiS_LVDSDataStruct *SiS_LVDS1024x768Data_1;
EXTERN SiS_LVDSDataStruct *SiS_LVDS1024x768Data_2;
EXTERN SiS_LVDSDataStruct *SiS_LVDS1280x1024Data_1;
EXTERN SiS_LVDSDataStruct *SiS_LVDS1280x1024Data_2;
EXTERN SiS_LVDSDataStruct *SiS_LVDS1280x960Data_1;
EXTERN SiS_LVDSDataStruct *SiS_LVDS1280x960Data_2;
EXTERN SiS_LVDSDataStruct *SiS_LVDS1400x1050Data_1;
EXTERN SiS_LVDSDataStruct *SiS_LVDS1400x1050Data_2;
EXTERN SiS_LVDSDataStruct *SiS_LVDS1024x600Data_1;
EXTERN SiS_LVDSDataStruct *SiS_LVDS1024x600Data_2;
EXTERN SiS_LVDSDataStruct *SiS_LVDS1152x768Data_1;
EXTERN SiS_LVDSDataStruct *SiS_LVDS1152x768Data_2;
EXTERN SiS_LVDSDataStruct *SiS_LVDS640x480Data_1;
EXTERN SiS_LVDSDataStruct *SiS_LVDS320x480Data_1;
EXTERN SiS_LVDSDataStruct *SiS_LVDSXXXxXXXData_1;
EXTERN SiS_LVDSDataStruct *SiS_CHTVUNTSCData;
EXTERN SiS_LVDSDataStruct *SiS_CHTVONTSCData;
EXTERN SiS_LVDSDataStruct *SiS_CHTVUPALData;
EXTERN SiS_LVDSDataStruct *SiS_CHTVOPALData;
EXTERN SiS_LVDSDesStruct *SiS_PanelType00_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType01_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType02_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType03_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType04_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType05_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType06_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType07_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType08_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType09_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0a_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0b_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0c_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0d_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0e_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0f_1;
EXTERN SiS_LVDSDesStruct *SiS_PanelType00_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType01_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType02_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType03_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType04_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType05_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType06_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType07_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType08_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType09_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0a_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0b_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0c_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0d_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0e_2;
EXTERN SiS_LVDSDesStruct *SiS_PanelType0f_2;
EXTERN SiS_LVDSDesStruct *LVDS1024x768Des_1;
EXTERN SiS_LVDSDesStruct *LVDS1280x1024Des_1;
EXTERN SiS_LVDSDesStruct *LVDS1280x960Des_1;
EXTERN SiS_LVDSDesStruct *LVDS1024x768Des_2;
EXTERN SiS_LVDSDesStruct *LVDS1280x1024Des_2;
EXTERN SiS_LVDSDesStruct *LVDS1280x960Des_2;
EXTERN SiS_LVDSDesStruct *SiS_CHTVUNTSCDesData;
EXTERN SiS_LVDSDesStruct *SiS_CHTVONTSCDesData;
EXTERN SiS_LVDSDesStruct *SiS_CHTVUPALDesData;
EXTERN SiS_LVDSDesStruct *SiS_CHTVOPALDesData;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT1800x600_1;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11024x768_1;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11280x1024_1;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11400x1050_1;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11024x600_1;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11152x768_1;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT1800x600_1_H;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11024x768_1_H;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11280x1024_1_H;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11400x1050_1_H;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11024x600_1_H;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11152x768_1_H;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT1800x600_2;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11024x768_2;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11280x1024_2;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11400x1050_2;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11024x600_2;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11152x768_2;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT1800x600_2_H;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11024x768_2_H;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11280x1024_2_H;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11400x1050_2_H;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11024x600_2_H;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT11152x768_2_H;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT1XXXxXXX_1;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT1XXXxXXX_1_H;
EXTERN SiS_LVDSCRT1DataStruct *SiS_CHTVCRT1UNTSC;
EXTERN SiS_LVDSCRT1DataStruct *SiS_CHTVCRT1ONTSC;
EXTERN SiS_LVDSCRT1DataStruct *SiS_CHTVCRT1UPAL;
EXTERN SiS_LVDSCRT1DataStruct *SiS_CHTVCRT1OPAL;
EXTERN SiS_LVDSCRT1DataStruct *SiS_LVDSCRT1320x480_1;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT1800x600_1;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT11024x768_1;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT11280x1024_1;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT1800x600_1_H;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT11024x768_1_H;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT11280x1024_1_H;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT1800x600_2;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT11024x768_2;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT11280x1024_2;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT1800x600_2_H;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT11024x768_2_H;
EXTERN SiS_LCDACRT1DataStruct *SiS_LCDACRT11280x1024_2_H;
/* TW: New from 650/301LV BIOS */
EXTERN SiS_Part2PortTblStruct *SiS_CRT2Part2_1024x768_1;
EXTERN SiS_Part2PortTblStruct *SiS_CRT2Part2_1280x1024_1;
EXTERN SiS_Part2PortTblStruct *SiS_CRT2Part2_1024x768_2;
EXTERN SiS_Part2PortTblStruct *SiS_CRT2Part2_1280x1024_2;
EXTERN SiS_Part2PortTblStruct *SiS_CRT2Part2_1024x768_3;
EXTERN SiS_Part2PortTblStruct *SiS_CRT2Part2_1280x1024_3;
EXTERN SiS_CHTVRegDataStruct *SiS_CHTVReg_UNTSC;
EXTERN SiS_CHTVRegDataStruct *SiS_CHTVReg_ONTSC;
......@@ -322,3 +385,6 @@ EXTERN UCHAR *SiS_CHTVVCLKUNTSC;
EXTERN UCHAR *SiS_CHTVVCLKONTSC;
EXTERN UCHAR *SiS_CHTVVCLKUPAL;
EXTERN UCHAR *SiS_CHTVVCLKOPAL;
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