Commit 4f01e650 authored by Hyungwon Hwang's avatar Hyungwon Hwang Committed by Inki Dae

ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi'

The clock which was named as 'pll_clk' is actually not the clock source
of PLL in MIPI DSI. This patch fixes this disagreement.
Signed-off-by: default avatarHyungwon Hwang <human.hwang@samsung.com>
Acked-by: default avatarKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: default avatarInki Dae <inki.dae@samsung.com>
parent 51d1deca
...@@ -167,7 +167,7 @@ dsi_0: dsi@11C80000 { ...@@ -167,7 +167,7 @@ dsi_0: dsi@11C80000 {
phys = <&mipi_phy 1>; phys = <&mipi_phy 1>;
phy-names = "dsim"; phy-names = "dsim";
clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
clock-names = "bus_clk", "pll_clk"; clock-names = "bus_clk", "sclk_mipi";
status = "disabled"; status = "disabled";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
......
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