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Commit 509a151f authored by Dave Airlie's avatar Dave Airlie
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From Jon Smirl: 

This code allows the mesa drivers to use a single definition of the DRM sarea/IOCTLS
parent ebad1c4d
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Showing with 140 additions and 57 deletions
drivers/char/drm/drm_sarea.h
View file @ 509a151f
...@@ -32,9 +32,23 @@ ...@@ -32,9 +32,23 @@
#ifndef _DRM_SAREA_H_ #ifndef _DRM_SAREA_H_
#define _DRM_SAREA_H_ #define _DRM_SAREA_H_
#include "drm.h"
/* SAREA area needs to be at least a page */
#if defined(__alpha__)
#define SAREA_MAX 0x2000
#elif defined(__ia64__)
#define SAREA_MAX 0x10000 /* 64kB */
#else
/* Intel 830M driver needs at least 8k SAREA */
#define SAREA_MAX 0x2000
#endif
/** Maximum number of drawables in the SAREA */ /** Maximum number of drawables in the SAREA */
#define SAREA_MAX_DRAWABLES 256 #define SAREA_MAX_DRAWABLES 256
#define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000
/** SAREA drawable */ /** SAREA drawable */
typedef struct drm_sarea_drawable { typedef struct drm_sarea_drawable {
unsigned int stamp; unsigned int stamp;
......
drivers/char/drm/mga_drm.h
View file @ 509a151f
...@@ -117,6 +117,8 @@ ...@@ -117,6 +117,8 @@
#define MGA_NR_TEX_REGIONS 16 #define MGA_NR_TEX_REGIONS 16
#define MGA_LOG_MIN_TEX_REGION_SIZE 16 #define MGA_LOG_MIN_TEX_REGION_SIZE 16
#define DRM_MGA_IDLE_RETRY 2048
#endif /* __MGA_SAREA_DEFINES__ */ #endif /* __MGA_SAREA_DEFINES__ */
...@@ -230,16 +232,27 @@ typedef struct _drm_mga_sarea { ...@@ -230,16 +232,27 @@ typedef struct _drm_mga_sarea {
/* MGA specific ioctls /* MGA specific ioctls
* The device specific ioctl range is 0x40 to 0x79. * The device specific ioctl range is 0x40 to 0x79.
*/ */
#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t) #define DRM_MGA_INIT 0x00
#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x41, drm_lock_t) #define DRM_MGA_FLUSH 0x01
#define DRM_IOCTL_MGA_RESET DRM_IO( 0x42) #define DRM_MGA_RESET 0x02
#define DRM_IOCTL_MGA_SWAP DRM_IO( 0x43) #define DRM_MGA_SWAP 0x03
#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x44, drm_mga_clear_t) #define DRM_MGA_CLEAR 0x04
#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x45, drm_mga_vertex_t) #define DRM_MGA_VERTEX 0x05
#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t) #define DRM_MGA_INDICES 0x06
#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x47, drm_mga_iload_t) #define DRM_MGA_ILOAD 0x07
#define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x48, drm_mga_blit_t) #define DRM_MGA_BLIT 0x08
#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(0x49, drm_mga_getparam_t) #define DRM_MGA_GETPARAM 0x09
#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t)
#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET)
#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP)
#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
typedef struct _drm_mga_warp_index { typedef struct _drm_mga_warp_index {
int installed; int installed;
...@@ -330,7 +343,7 @@ typedef struct _drm_mga_blit { ...@@ -330,7 +343,7 @@ typedef struct _drm_mga_blit {
typedef struct drm_mga_getparam { typedef struct drm_mga_getparam {
int param; int param;
int *value; void *value;
} drm_mga_getparam_t; } drm_mga_getparam_t;
#endif #endif
drivers/char/drm/r128_drm.h
View file @ 509a151f
...@@ -176,24 +176,47 @@ typedef struct drm_r128_sarea { ...@@ -176,24 +176,47 @@ typedef struct drm_r128_sarea {
/* Rage 128 specific ioctls /* Rage 128 specific ioctls
* The device specific ioctl range is 0x40 to 0x79. * The device specific ioctl range is 0x40 to 0x79.
*/ */
#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t) #define DRM_R128_INIT 0x00
#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41) #define DRM_R128_CCE_START 0x01
#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t) #define DRM_R128_CCE_STOP 0x02
#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43) #define DRM_R128_CCE_RESET 0x03
#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44) #define DRM_R128_CCE_IDLE 0x04
#define DRM_IOCTL_R128_RESET DRM_IO( 0x46) /* 0x05 not used */
#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47) #define DRM_R128_RESET 0x06
#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t) #define DRM_R128_SWAP 0x07
#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t) #define DRM_R128_CLEAR 0x08
#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t) #define DRM_R128_VERTEX 0x09
#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t) #define DRM_R128_INDICES 0x0a
#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t) #define DRM_R128_BLIT 0x0b
#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t) #define DRM_R128_DEPTH 0x0c
#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(0x4f, drm_r128_indirect_t) #define DRM_R128_STIPPLE 0x0d
#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x50, drm_r128_fullscreen_t) /* 0x0e not used */
#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( 0x51, drm_r128_clear2_t) #define DRM_R128_INDIRECT 0x0f
#define DRM_IOCTL_R128_GETPARAM DRM_IOW( 0x52, drm_r128_getparam_t) #define DRM_R128_FULLSCREEN 0x10
#define DRM_IOCTL_R128_FLIP DRM_IO( 0x53) #define DRM_R128_CLEAR2 0x11
#define DRM_R128_GETPARAM 0x12
#define DRM_R128_FLIP 0x13
#define DRM_IOCTL_R128_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t)
#define DRM_IOCTL_R128_CCE_START DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_START)
#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t)
#define DRM_IOCTL_R128_CCE_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_RESET)
#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_IDLE)
/* 0x05 not used */
#define DRM_IOCTL_R128_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_RESET)
#define DRM_IOCTL_R128_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_R128_SWAP)
#define DRM_IOCTL_R128_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t)
#define DRM_IOCTL_R128_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t)
#define DRM_IOCTL_R128_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t)
#define DRM_IOCTL_R128_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t)
#define DRM_IOCTL_R128_DEPTH DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t)
#define DRM_IOCTL_R128_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t)
/* 0x0e not used */
#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t)
#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t)
#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
#define DRM_IOCTL_R128_GETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
#define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP)
typedef struct drm_r128_init { typedef struct drm_r128_init {
enum { enum {
...@@ -316,7 +339,7 @@ typedef struct drm_r128_fullscreen { ...@@ -316,7 +339,7 @@ typedef struct drm_r128_fullscreen {
typedef struct drm_r128_getparam { typedef struct drm_r128_getparam {
int param; int param;
int *value; void *value;
} drm_r128_getparam_t; } drm_r128_getparam_t;
#endif #endif
drivers/char/drm/radeon_drm.h
View file @ 509a151f
...@@ -226,6 +226,13 @@ typedef union { ...@@ -226,6 +226,13 @@ typedef union {
#define RADEON_MAX_TEXTURE_LEVELS 12 #define RADEON_MAX_TEXTURE_LEVELS 12
#define RADEON_MAX_TEXTURE_UNITS 3 #define RADEON_MAX_TEXTURE_UNITS 3
/* Blits have strict offset rules. All blit offset must be aligned on
* a 1K-byte boundary.
*/
#define RADEON_OFFSET_SHIFT 10
#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
#endif /* __RADEON_SAREA_DEFINES__ */ #endif /* __RADEON_SAREA_DEFINES__ */
typedef struct { typedef struct {
...@@ -365,32 +372,58 @@ typedef struct { ...@@ -365,32 +372,58 @@ typedef struct {
/* Radeon specific ioctls /* Radeon specific ioctls
* The device specific ioctl range is 0x40 to 0x79. * The device specific ioctl range is 0x40 to 0x79.
*/ */
#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t) #define DRM_RADEON_CP_INIT 0x00
#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41) #define DRM_RADEON_CP_START 0x01
#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t) #define DRM_RADEON_CP_STOP 0x02
#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43) #define DRM_RADEON_CP_RESET 0x03
#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44) #define DRM_RADEON_CP_IDLE 0x04
#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45) #define DRM_RADEON_RESET 0x05
#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t) #define DRM_RADEON_FULLSCREEN 0x06
#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47) #define DRM_RADEON_SWAP 0x07
#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t) #define DRM_RADEON_CLEAR 0x08
#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t) #define DRM_RADEON_VERTEX 0x09
#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t) #define DRM_RADEON_INDICES 0x0A
#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t) #define DRM_RADEON_NOT_USED
#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t) #define DRM_RADEON_STIPPLE 0x0C
#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t) #define DRM_RADEON_INDIRECT 0x0D
#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( 0x4f, drm_radeon_vertex2_t) #define DRM_RADEON_TEXTURE 0x0E
#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( 0x50, drm_radeon_cmd_buffer_t) #define DRM_RADEON_VERTEX2 0x0F
#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(0x51, drm_radeon_getparam_t) #define DRM_RADEON_CMDBUF 0x10
#define DRM_IOCTL_RADEON_FLIP DRM_IO( 0x52) #define DRM_RADEON_GETPARAM 0x11
#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR( 0x53, drm_radeon_mem_alloc_t) #define DRM_RADEON_FLIP 0x12
#define DRM_IOCTL_RADEON_FREE DRM_IOW( 0x54, drm_radeon_mem_free_t) #define DRM_RADEON_ALLOC 0x13
#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( 0x55, drm_radeon_mem_init_heap_t) #define DRM_RADEON_FREE 0x14
#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR( 0x56, drm_radeon_irq_emit_t) #define DRM_RADEON_INIT_HEAP 0x15
#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( 0x57, drm_radeon_irq_wait_t) #define DRM_RADEON_IRQ_EMIT 0x16
/* added by Charl P. Botha - see radeon_cp.c for details */ #define DRM_RADEON_IRQ_WAIT 0x17
#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO(0x58) #define DRM_RADEON_CP_RESUME 0x18
#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( 0x59, drm_radeon_setparam_t) #define DRM_RADEON_SETPARAM 0x19
#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
typedef struct drm_radeon_init { typedef struct drm_radeon_init {
enum { enum {
...@@ -542,7 +575,7 @@ typedef struct drm_radeon_indirect { ...@@ -542,7 +575,7 @@ typedef struct drm_radeon_indirect {
typedef struct drm_radeon_getparam { typedef struct drm_radeon_getparam {
int param; int param;
int *value; void *value;
} drm_radeon_getparam_t; } drm_radeon_getparam_t;
/* 1.6: Set up a memory manager for regions of shared memory: /* 1.6: Set up a memory manager for regions of shared memory:
......
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