Commit 50e02e9a authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Rob Herring

dt-bindings: timer: arm,twd: Convert to json-schema

Convert the ARM Timer-Watchdog Device Tree binding documentation to
json-schema.  As the old binding document actually contained two
bindings, it is split in two document: one for the timer part, and one
for the watchdog part.

Document missing properties.
Update examples to match reality.
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/3ccc0cf5319f56e230ee3b8a009f8d63afb114c1.1621521847.git.geert+renesas@glider.be
[robh: Fix up node names]
Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent 1d92d556
......@@ -26,7 +26,7 @@ interrupt-controller:
see binding for interrupt-controller/arm,gic.txt
timer:
see binding for timer/arm,twd.txt
see binding for timer/arm,twd-timer.yaml
clocks:
see binding for clocks/ux500.txt
......
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/arm,twd-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Timer-Watchdog Timer
maintainers:
- Rob Herring <robh@kernel.org>
description:
ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
and watchdog.
The TWD is usually attached to a GIC to deliver its two per-processor
interrupts.
properties:
compatible:
enum:
- arm,cortex-a9-twd-timer
- arm,cortex-a5-twd-timer
- arm,arm11mp-twd-timer
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
always-on:
description:
If present, the timer is powered through an always-on power domain,
therefore it never loses context.
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
timer@2c000600 {
compatible = "arm,arm11mp-twd-timer";
reg = <0x2c000600 0x20>;
interrupts = <GIC_PPI 13 0xf01>;
};
* ARM Timer Watchdog
ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
and watchdog.
The TWD is usually attached to a GIC to deliver its two per-processor
interrupts.
** Timer node required properties:
- compatible : Should be one of:
"arm,cortex-a9-twd-timer"
"arm,cortex-a5-twd-timer"
"arm,arm11mp-twd-timer"
- interrupts : One interrupt to each core
- reg : Specify the base address and the size of the TWD timer
register window.
Optional
- always-on : a boolean property. If present, the timer is powered through
an always-on power domain, therefore it never loses context.
Example:
twd-timer@2c000600 {
compatible = "arm,arm11mp-twd-timer"";
reg = <0x2c000600 0x20>;
interrupts = <1 13 0xf01>;
};
** Watchdog node properties:
- compatible : Should be one of:
"arm,cortex-a9-twd-wdt"
"arm,cortex-a5-twd-wdt"
"arm,arm11mp-twd-wdt"
- interrupts : One interrupt to each core
- reg : Specify the base address and the size of the TWD watchdog
register window.
Example:
twd-watchdog@2c000620 {
compatible = "arm,arm11mp-twd-wdt";
reg = <0x2c000620 0x20>;
interrupts = <1 14 0xf01>;
};
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/arm,twd-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Timer-Watchdog Watchdog
maintainers:
- Rob Herring <robh@kernel.org>
description:
ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
and watchdog.
The TWD is usually attached to a GIC to deliver its two per-processor
interrupts.
properties:
compatible:
enum:
- arm,cortex-a9-twd-wdt
- arm,cortex-a5-twd-wdt
- arm,arm11mp-twd-wdt
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
watchdog@2c000620 {
compatible = "arm,arm11mp-twd-wdt";
reg = <0x2c000620 0x20>;
interrupts = <GIC_PPI 14 0xf01>;
};
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