Commit 51de9c6d authored by Ville Syrjälä's avatar Ville Syrjälä

drm/i915: Don't pass dev_priv around so much

Simplify the calling convention of the skl+ watermark functions
by not passing around dev_priv needlessly. The callees have
what they need to dig it out anyway.
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181114210729.16185-10-ville.syrjala@linux.intel.comReviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
parent 8315847b
...@@ -4617,12 +4617,12 @@ skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate, ...@@ -4617,12 +4617,12 @@ skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
} }
static int static int
skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv, skl_compute_plane_wm_params(const struct intel_crtc_state *cstate,
const struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate, const struct intel_plane_state *intel_pstate,
struct skl_wm_params *wp, int plane_id) struct skl_wm_params *wp, int plane_id)
{ {
struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane); struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_plane_state *pstate = &intel_pstate->base; const struct drm_plane_state *pstate = &intel_pstate->base;
const struct drm_framebuffer *fb = pstate->fb; const struct drm_framebuffer *fb = pstate->fb;
uint32_t interm_pbpl; uint32_t interm_pbpl;
...@@ -4721,8 +4721,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv, ...@@ -4721,8 +4721,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
return 0; return 0;
} }
static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, static int skl_compute_plane_wm(const struct intel_crtc_state *cstate,
const struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate, const struct intel_plane_state *intel_pstate,
uint16_t ddb_allocation, uint16_t ddb_allocation,
int level, int level,
...@@ -4730,6 +4729,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, ...@@ -4730,6 +4729,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
const struct skl_wm_level *result_prev, const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */) struct skl_wm_level *result /* out */)
{ {
struct drm_i915_private *dev_priv =
to_i915(intel_pstate->base.plane->dev);
const struct drm_plane_state *pstate = &intel_pstate->base; const struct drm_plane_state *pstate = &intel_pstate->base;
uint32_t latency = dev_priv->wm.skl_latency[level]; uint32_t latency = dev_priv->wm.skl_latency[level];
uint_fixed_16_16_t method1, method2; uint_fixed_16_16_t method1, method2;
...@@ -4864,13 +4865,14 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, ...@@ -4864,13 +4865,14 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
} }
static int static int
skl_compute_wm_levels(const struct drm_i915_private *dev_priv, skl_compute_wm_levels(const struct intel_crtc_state *cstate,
const struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate, const struct intel_plane_state *intel_pstate,
uint16_t ddb_blocks, uint16_t ddb_blocks,
const struct skl_wm_params *wm_params, const struct skl_wm_params *wm_params,
struct skl_wm_level *levels) struct skl_wm_level *levels)
{ {
struct drm_i915_private *dev_priv =
to_i915(intel_pstate->base.plane->dev);
int level, max_level = ilk_wm_max_level(dev_priv); int level, max_level = ilk_wm_max_level(dev_priv);
struct skl_wm_level *result_prev = &levels[0]; struct skl_wm_level *result_prev = &levels[0];
int ret; int ret;
...@@ -4878,8 +4880,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv, ...@@ -4878,8 +4880,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
for (level = 0; level <= max_level; level++) { for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = &levels[level]; struct skl_wm_level *result = &levels[level];
ret = skl_compute_plane_wm(dev_priv, ret = skl_compute_plane_wm(cstate,
cstate,
intel_pstate, intel_pstate,
ddb_blocks, ddb_blocks,
level, level,
...@@ -4983,19 +4984,18 @@ static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb, ...@@ -4983,19 +4984,18 @@ static int skl_build_plane_wm_single(struct skl_ddb_allocation *ddb,
enum plane_id plane_id, int color_plane) enum plane_id plane_id, int color_plane)
{ {
struct intel_plane *plane = to_intel_plane(plane_state->base.plane); struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
struct skl_wm_params wm_params; struct skl_wm_params wm_params;
enum pipe pipe = plane->pipe; enum pipe pipe = plane->pipe;
uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]); uint16_t ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
int ret; int ret;
ret = skl_compute_plane_wm_params(dev_priv, crtc_state, plane_state, ret = skl_compute_plane_wm_params(crtc_state, plane_state,
&wm_params, color_plane); &wm_params, color_plane);
if (ret) if (ret)
return ret; return ret;
ret = skl_compute_wm_levels(dev_priv, crtc_state, plane_state, ret = skl_compute_wm_levels(crtc_state, plane_state,
ddb_blocks, &wm_params, wm->wm); ddb_blocks, &wm_params, wm->wm);
if (ret) if (ret)
return ret; return ret;
...@@ -5011,7 +5011,6 @@ static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb, ...@@ -5011,7 +5011,6 @@ static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
enum plane_id plane_id) enum plane_id plane_id)
{ {
struct intel_plane *plane = to_intel_plane(plane_state->base.plane); struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
struct skl_wm_params wm_params; struct skl_wm_params wm_params;
enum pipe pipe = plane->pipe; enum pipe pipe = plane->pipe;
...@@ -5021,12 +5020,12 @@ static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb, ...@@ -5021,12 +5020,12 @@ static int skl_build_plane_wm_uv(struct skl_ddb_allocation *ddb,
wm->is_planar = true; wm->is_planar = true;
/* uv plane watermarks must also be validated for NV12/Planar */ /* uv plane watermarks must also be validated for NV12/Planar */
ret = skl_compute_plane_wm_params(dev_priv, crtc_state, plane_state, ret = skl_compute_plane_wm_params(crtc_state, plane_state,
&wm_params, 1); &wm_params, 1);
if (ret) if (ret)
return ret; return ret;
ret = skl_compute_wm_levels(dev_priv, crtc_state, plane_state, ret = skl_compute_wm_levels(crtc_state, plane_state,
ddb_blocks, &wm_params, wm->uv_wm); ddb_blocks, &wm_params, wm->uv_wm);
if (ret) if (ret)
return ret; return ret;
......
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