Commit 52420e48 authored by Palmer Dabbelt's avatar Palmer Dabbelt

RISC-V: Provide the frequency of time CSR via hwprobe

The RISC-V architecture makes a real time counter CSR (via RDTIME
instruction) available for applications in U-mode but there is no
architected mechanism for an application to discover the frequency
the counter is running at. Some applications (e.g., DPDK) use the
time counter for basic performance analysis as well as fine grained
time-keeping.

Add support to the hwprobe system call to export the time CSR
frequency to code running in U-mode.
Signed-off-by: default avatarYunhui Cui <cuiyunhui@bytedance.com>
Reviewed-by: default avatarEvan Green <evan@rivosinc.com>
Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
Acked-by: default avatarPunit Agrawal <punit.agrawal@bytedance.com>
Link: https://lore.kernel.org/r/20240702033731.71955-2-cuiyunhui@bytedance.comSigned-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 5c8405d7
...@@ -264,3 +264,5 @@ The following keys are defined: ...@@ -264,3 +264,5 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS`: An unsigned long which * :c:macro:`RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS`: An unsigned long which
represent the highest userspace virtual address usable. represent the highest userspace virtual address usable.
* :c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`: Frequency (in Hz) of `time CSR`.
...@@ -8,7 +8,7 @@ ...@@ -8,7 +8,7 @@
#include <uapi/asm/hwprobe.h> #include <uapi/asm/hwprobe.h>
#define RISCV_HWPROBE_MAX_KEY 7 #define RISCV_HWPROBE_MAX_KEY 8
static inline bool riscv_hwprobe_key_is_valid(__s64 key) static inline bool riscv_hwprobe_key_is_valid(__s64 key)
{ {
......
...@@ -81,6 +81,7 @@ struct riscv_hwprobe { ...@@ -81,6 +81,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
#define RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS 7 #define RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS 7
#define RISCV_HWPROBE_KEY_TIME_CSR_FREQ 8
/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
/* Flags */ /* Flags */
......
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
#include <asm/cpufeature.h> #include <asm/cpufeature.h>
#include <asm/hwprobe.h> #include <asm/hwprobe.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/delay.h>
#include <asm/sbi.h> #include <asm/sbi.h>
#include <asm/switch_to.h> #include <asm/switch_to.h>
#include <asm/uaccess.h> #include <asm/uaccess.h>
...@@ -236,6 +237,10 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, ...@@ -236,6 +237,10 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
pair->value = user_max_virt_addr(); pair->value = user_max_virt_addr();
break; break;
case RISCV_HWPROBE_KEY_TIME_CSR_FREQ:
pair->value = riscv_timebase;
break;
/* /*
* For forward compatibility, unknown keys don't fail the whole * For forward compatibility, unknown keys don't fail the whole
* call, but get their element key set to -1 and value set to 0 * call, but get their element key set to -1 and value set to 0
......
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