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Commit 524ef29c authored by Maxime Bizon's avatar Maxime Bizon Committed by Ralf Baechle
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MIPS: BCM63xx: Add support for second uart. 

The BCm63xx SOC has two uarts.  Some boards use the second one for
bluetooth.  This patch changes platform device registration code to
handle this.  Changes to the UART driver were already merged in
6a2c7eab.
Signed-off-by: default avatarMaxime Bizon <mbizon@freebox.fr>
To: linux-mips@linux-mips.org
Cc: Maxime Bizon <mbizon@freebox.fr>
Patchwork: http://patchwork.linux-mips.org/patch/900/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 97befcf4
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Showing with 102 additions and 19 deletions
arch/mips/bcm63xx/boards/board_bcm963xx.c
View file @ 524ef29c
...@@ -18,6 +18,7 @@ ...@@ -18,6 +18,7 @@
#include <asm/addrspace.h> #include <asm/addrspace.h>
#include <bcm63xx_board.h> #include <bcm63xx_board.h>
#include <bcm63xx_cpu.h> #include <bcm63xx_cpu.h>
#include <bcm63xx_dev_uart.h>
#include <bcm63xx_regs.h> #include <bcm63xx_regs.h>
#include <bcm63xx_io.h> #include <bcm63xx_io.h>
#include <bcm63xx_dev_pci.h> #include <bcm63xx_dev_pci.h>
...@@ -40,6 +41,7 @@ static struct board_info __initdata board_96338gw = { ...@@ -40,6 +41,7 @@ static struct board_info __initdata board_96338gw = {
.name = "96338GW", .name = "96338GW",
.expected_cpu_id = 0x6338, .expected_cpu_id = 0x6338,
.has_uart0 = 1,
.has_enet0 = 1, .has_enet0 = 1,
.enet0 = { .enet0 = {
.force_speed_100 = 1, .force_speed_100 = 1,
...@@ -82,6 +84,7 @@ static struct board_info __initdata board_96338w = { ...@@ -82,6 +84,7 @@ static struct board_info __initdata board_96338w = {
.name = "96338W", .name = "96338W",
.expected_cpu_id = 0x6338, .expected_cpu_id = 0x6338,
.has_uart0 = 1,
.has_enet0 = 1, .has_enet0 = 1,
.enet0 = { .enet0 = {
.force_speed_100 = 1, .force_speed_100 = 1,
...@@ -126,6 +129,8 @@ static struct board_info __initdata board_96338w = { ...@@ -126,6 +129,8 @@ static struct board_info __initdata board_96338w = {
static struct board_info __initdata board_96345gw2 = { static struct board_info __initdata board_96345gw2 = {
.name = "96345GW2", .name = "96345GW2",
.expected_cpu_id = 0x6345, .expected_cpu_id = 0x6345,
.has_uart0 = 1,
}; };
#endif #endif
...@@ -137,6 +142,7 @@ static struct board_info __initdata board_96348r = { ...@@ -137,6 +142,7 @@ static struct board_info __initdata board_96348r = {
.name = "96348R", .name = "96348R",
.expected_cpu_id = 0x6348, .expected_cpu_id = 0x6348,
.has_uart0 = 1,
.has_enet0 = 1, .has_enet0 = 1,
.has_pci = 1, .has_pci = 1,
...@@ -180,6 +186,7 @@ static struct board_info __initdata board_96348gw_10 = { ...@@ -180,6 +186,7 @@ static struct board_info __initdata board_96348gw_10 = {
.name = "96348GW-10", .name = "96348GW-10",
.expected_cpu_id = 0x6348, .expected_cpu_id = 0x6348,
.has_uart0 = 1,
.has_enet0 = 1, .has_enet0 = 1,
.has_enet1 = 1, .has_enet1 = 1,
.has_pci = 1, .has_pci = 1,
...@@ -239,6 +246,7 @@ static struct board_info __initdata board_96348gw_11 = { ...@@ -239,6 +246,7 @@ static struct board_info __initdata board_96348gw_11 = {
.name = "96348GW-11", .name = "96348GW-11",
.expected_cpu_id = 0x6348, .expected_cpu_id = 0x6348,
.has_uart0 = 1,
.has_enet0 = 1, .has_enet0 = 1,
.has_enet1 = 1, .has_enet1 = 1,
.has_pci = 1, .has_pci = 1,
...@@ -292,6 +300,7 @@ static struct board_info __initdata board_96348gw = { ...@@ -292,6 +300,7 @@ static struct board_info __initdata board_96348gw = {
.name = "96348GW", .name = "96348GW",
.expected_cpu_id = 0x6348, .expected_cpu_id = 0x6348,
.has_uart0 = 1,
.has_enet0 = 1, .has_enet0 = 1,
.has_enet1 = 1, .has_enet1 = 1,
.has_pci = 1, .has_pci = 1,
...@@ -349,9 +358,10 @@ static struct board_info __initdata board_FAST2404 = { ...@@ -349,9 +358,10 @@ static struct board_info __initdata board_FAST2404 = {
.name = "F@ST2404", .name = "F@ST2404",
.expected_cpu_id = 0x6348, .expected_cpu_id = 0x6348,
.has_enet0 = 1, .has_uart0 = 1,
.has_enet1 = 1, .has_enet0 = 1,
.has_pci = 1, .has_enet1 = 1,
.has_pci = 1,
.enet0 = { .enet0 = {
.has_phy = 1, .has_phy = 1,
...@@ -391,6 +401,7 @@ static struct board_info __initdata board_DV201AMR = { ...@@ -391,6 +401,7 @@ static struct board_info __initdata board_DV201AMR = {
.name = "DV201AMR", .name = "DV201AMR",
.expected_cpu_id = 0x6348, .expected_cpu_id = 0x6348,
.has_uart0 = 1,
.has_pci = 1, .has_pci = 1,
.has_ohci0 = 1, .has_ohci0 = 1,
...@@ -410,6 +421,7 @@ static struct board_info __initdata board_96348gw_a = { ...@@ -410,6 +421,7 @@ static struct board_info __initdata board_96348gw_a = {
.name = "96348GW-A", .name = "96348GW-A",
.expected_cpu_id = 0x6348, .expected_cpu_id = 0x6348,
.has_uart0 = 1,
.has_enet0 = 1, .has_enet0 = 1,
.has_enet1 = 1, .has_enet1 = 1,
.has_pci = 1, .has_pci = 1,
...@@ -435,6 +447,7 @@ static struct board_info __initdata board_96358vw = { ...@@ -435,6 +447,7 @@ static struct board_info __initdata board_96358vw = {
.name = "96358VW", .name = "96358VW",
.expected_cpu_id = 0x6358, .expected_cpu_id = 0x6358,
.has_uart0 = 1,
.has_enet0 = 1, .has_enet0 = 1,
.has_enet1 = 1, .has_enet1 = 1,
.has_pci = 1, .has_pci = 1,
...@@ -486,6 +499,7 @@ static struct board_info __initdata board_96358vw2 = { ...@@ -486,6 +499,7 @@ static struct board_info __initdata board_96358vw2 = {
.name = "96358VW2", .name = "96358VW2",
.expected_cpu_id = 0x6358, .expected_cpu_id = 0x6358,
.has_uart0 = 1,
.has_enet0 = 1, .has_enet0 = 1,
.has_enet1 = 1, .has_enet1 = 1,
.has_pci = 1, .has_pci = 1,
...@@ -533,6 +547,7 @@ static struct board_info __initdata board_AGPFS0 = { ...@@ -533,6 +547,7 @@ static struct board_info __initdata board_AGPFS0 = {
.name = "AGPF-S0", .name = "AGPF-S0",
.expected_cpu_id = 0x6358, .expected_cpu_id = 0x6358,
.has_uart0 = 1,
.has_enet0 = 1, .has_enet0 = 1,
.has_enet1 = 1, .has_enet1 = 1,
.has_pci = 1, .has_pci = 1,
...@@ -834,6 +849,12 @@ int __init board_register_devices(void) ...@@ -834,6 +849,12 @@ int __init board_register_devices(void)
{ {
u32 val; u32 val;
if (board.has_uart0)
bcm63xx_uart_register(0);
if (board.has_uart1)
bcm63xx_uart_register(1);
if (board.has_pccard) if (board.has_pccard)
bcm63xx_pcmcia_register(); bcm63xx_pcmcia_register();
......
arch/mips/bcm63xx/cpu.c
View file @ 524ef29c
...@@ -36,6 +36,7 @@ static const unsigned long bcm96338_regs_base[] = { ...@@ -36,6 +36,7 @@ static const unsigned long bcm96338_regs_base[] = {
[RSET_TIMER] = BCM_6338_TIMER_BASE, [RSET_TIMER] = BCM_6338_TIMER_BASE,
[RSET_WDT] = BCM_6338_WDT_BASE, [RSET_WDT] = BCM_6338_WDT_BASE,
[RSET_UART0] = BCM_6338_UART0_BASE, [RSET_UART0] = BCM_6338_UART0_BASE,
[RSET_UART1] = BCM_6338_UART1_BASE,
[RSET_GPIO] = BCM_6338_GPIO_BASE, [RSET_GPIO] = BCM_6338_GPIO_BASE,
[RSET_SPI] = BCM_6338_SPI_BASE, [RSET_SPI] = BCM_6338_SPI_BASE,
[RSET_OHCI0] = BCM_6338_OHCI0_BASE, [RSET_OHCI0] = BCM_6338_OHCI0_BASE,
...@@ -72,6 +73,7 @@ static const unsigned long bcm96345_regs_base[] = { ...@@ -72,6 +73,7 @@ static const unsigned long bcm96345_regs_base[] = {
[RSET_TIMER] = BCM_6345_TIMER_BASE, [RSET_TIMER] = BCM_6345_TIMER_BASE,
[RSET_WDT] = BCM_6345_WDT_BASE, [RSET_WDT] = BCM_6345_WDT_BASE,
[RSET_UART0] = BCM_6345_UART0_BASE, [RSET_UART0] = BCM_6345_UART0_BASE,
[RSET_UART1] = BCM_6345_UART1_BASE,
[RSET_GPIO] = BCM_6345_GPIO_BASE, [RSET_GPIO] = BCM_6345_GPIO_BASE,
[RSET_SPI] = BCM_6345_SPI_BASE, [RSET_SPI] = BCM_6345_SPI_BASE,
[RSET_UDC0] = BCM_6345_UDC0_BASE, [RSET_UDC0] = BCM_6345_UDC0_BASE,
...@@ -109,6 +111,7 @@ static const unsigned long bcm96348_regs_base[] = { ...@@ -109,6 +111,7 @@ static const unsigned long bcm96348_regs_base[] = {
[RSET_TIMER] = BCM_6348_TIMER_BASE, [RSET_TIMER] = BCM_6348_TIMER_BASE,
[RSET_WDT] = BCM_6348_WDT_BASE, [RSET_WDT] = BCM_6348_WDT_BASE,
[RSET_UART0] = BCM_6348_UART0_BASE, [RSET_UART0] = BCM_6348_UART0_BASE,
[RSET_UART1] = BCM_6348_UART1_BASE,
[RSET_GPIO] = BCM_6348_GPIO_BASE, [RSET_GPIO] = BCM_6348_GPIO_BASE,
[RSET_SPI] = BCM_6348_SPI_BASE, [RSET_SPI] = BCM_6348_SPI_BASE,
[RSET_OHCI0] = BCM_6348_OHCI0_BASE, [RSET_OHCI0] = BCM_6348_OHCI0_BASE,
...@@ -150,6 +153,7 @@ static const unsigned long bcm96358_regs_base[] = { ...@@ -150,6 +153,7 @@ static const unsigned long bcm96358_regs_base[] = {
[RSET_TIMER] = BCM_6358_TIMER_BASE, [RSET_TIMER] = BCM_6358_TIMER_BASE,
[RSET_WDT] = BCM_6358_WDT_BASE, [RSET_WDT] = BCM_6358_WDT_BASE,
[RSET_UART0] = BCM_6358_UART0_BASE, [RSET_UART0] = BCM_6358_UART0_BASE,
[RSET_UART1] = BCM_6358_UART1_BASE,
[RSET_GPIO] = BCM_6358_GPIO_BASE, [RSET_GPIO] = BCM_6358_GPIO_BASE,
[RSET_SPI] = BCM_6358_SPI_BASE, [RSET_SPI] = BCM_6358_SPI_BASE,
[RSET_OHCI0] = BCM_6358_OHCI0_BASE, [RSET_OHCI0] = BCM_6358_OHCI0_BASE,
...@@ -170,6 +174,7 @@ static const unsigned long bcm96358_regs_base[] = { ...@@ -170,6 +174,7 @@ static const unsigned long bcm96358_regs_base[] = {
static const int bcm96358_irqs[] = { static const int bcm96358_irqs[] = {
[IRQ_TIMER] = BCM_6358_TIMER_IRQ, [IRQ_TIMER] = BCM_6358_TIMER_IRQ,
[IRQ_UART0] = BCM_6358_UART0_IRQ, [IRQ_UART0] = BCM_6358_UART0_IRQ,
[IRQ_UART1] = BCM_6358_UART1_IRQ,
[IRQ_DSL] = BCM_6358_DSL_IRQ, [IRQ_DSL] = BCM_6358_DSL_IRQ,
[IRQ_ENET0] = BCM_6358_ENET0_IRQ, [IRQ_ENET0] = BCM_6358_ENET0_IRQ,
[IRQ_ENET1] = BCM_6358_ENET1_IRQ, [IRQ_ENET1] = BCM_6358_ENET1_IRQ,
......
arch/mips/bcm63xx/dev-uart.c
View file @ 524ef29c
...@@ -11,31 +11,65 @@ ...@@ -11,31 +11,65 @@
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <bcm63xx_cpu.h> #include <bcm63xx_cpu.h>
static struct resource uart_resources[] = { static struct resource uart0_resources[] = {
{ {
.start = -1, /* filled at runtime */ /* start & end filled at runtime */
.end = -1, /* filled at runtime */
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
{ {
.start = -1, /* filled at runtime */ /* start filled at runtime */
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
static struct platform_device bcm63xx_uart_device = { static struct resource uart1_resources[] = {
.name = "bcm63xx_uart", {
.id = 0, /* start & end filled at runtime */
.num_resources = ARRAY_SIZE(uart_resources), .flags = IORESOURCE_MEM,
.resource = uart_resources, },
{
/* start filled at runtime */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bcm63xx_uart_devices[] = {
{
.name = "bcm63xx_uart",
.id = 0,
.num_resources = ARRAY_SIZE(uart0_resources),
.resource = uart0_resources,
},
{
.name = "bcm63xx_uart",
.id = 1,
.num_resources = ARRAY_SIZE(uart1_resources),
.resource = uart1_resources,
}
}; };
int __init bcm63xx_uart_register(void) int __init bcm63xx_uart_register(unsigned int id)
{ {
uart_resources[0].start = bcm63xx_regset_address(RSET_UART0); if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
uart_resources[0].end = uart_resources[0].start; return -ENODEV;
uart_resources[0].end += RSET_UART_SIZE - 1;
uart_resources[1].start = bcm63xx_get_irq_number(IRQ_UART0); if (id == 1 && !BCMCPU_IS_6358())
return platform_device_register(&bcm63xx_uart_device); return -ENODEV;
if (id == 0) {
uart0_resources[0].start = bcm63xx_regset_address(RSET_UART0);
uart0_resources[0].end = uart0_resources[0].start +
RSET_UART_SIZE - 1;
uart0_resources[1].start = bcm63xx_get_irq_number(IRQ_UART0);
}
if (id == 1) {
uart1_resources[0].start = bcm63xx_regset_address(RSET_UART1);
uart1_resources[0].end = uart1_resources[0].start +
RSET_UART_SIZE - 1;
uart1_resources[1].start = bcm63xx_get_irq_number(IRQ_UART1);
}
return platform_device_register(&bcm63xx_uart_devices[id]);
} }
arch_initcall(bcm63xx_uart_register);
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
View file @ 524ef29c
...@@ -85,6 +85,7 @@ enum bcm63xx_regs_set { ...@@ -85,6 +85,7 @@ enum bcm63xx_regs_set {
RSET_TIMER, RSET_TIMER,
RSET_WDT, RSET_WDT,
RSET_UART0, RSET_UART0,
RSET_UART1,
RSET_GPIO, RSET_GPIO,
RSET_SPI, RSET_SPI,
RSET_UDC0, RSET_UDC0,
...@@ -123,6 +124,7 @@ enum bcm63xx_regs_set { ...@@ -123,6 +124,7 @@ enum bcm63xx_regs_set {
#define BCM_6338_TIMER_BASE (0xfffe0200) #define BCM_6338_TIMER_BASE (0xfffe0200)
#define BCM_6338_WDT_BASE (0xfffe021c) #define BCM_6338_WDT_BASE (0xfffe021c)
#define BCM_6338_UART0_BASE (0xfffe0300) #define BCM_6338_UART0_BASE (0xfffe0300)
#define BCM_6338_UART1_BASE (0xdeadbeef)
#define BCM_6338_GPIO_BASE (0xfffe0400) #define BCM_6338_GPIO_BASE (0xfffe0400)
#define BCM_6338_SPI_BASE (0xfffe0c00) #define BCM_6338_SPI_BASE (0xfffe0c00)
#define BCM_6338_UDC0_BASE (0xdeadbeef) #define BCM_6338_UDC0_BASE (0xdeadbeef)
...@@ -153,6 +155,7 @@ enum bcm63xx_regs_set { ...@@ -153,6 +155,7 @@ enum bcm63xx_regs_set {
#define BCM_6345_TIMER_BASE (0xfffe0200) #define BCM_6345_TIMER_BASE (0xfffe0200)
#define BCM_6345_WDT_BASE (0xfffe021c) #define BCM_6345_WDT_BASE (0xfffe021c)
#define BCM_6345_UART0_BASE (0xfffe0300) #define BCM_6345_UART0_BASE (0xfffe0300)
#define BCM_6345_UART1_BASE (0xdeadbeef)
#define BCM_6345_GPIO_BASE (0xfffe0400) #define BCM_6345_GPIO_BASE (0xfffe0400)
#define BCM_6345_SPI_BASE (0xdeadbeef) #define BCM_6345_SPI_BASE (0xdeadbeef)
#define BCM_6345_UDC0_BASE (0xdeadbeef) #define BCM_6345_UDC0_BASE (0xdeadbeef)
...@@ -182,6 +185,7 @@ enum bcm63xx_regs_set { ...@@ -182,6 +185,7 @@ enum bcm63xx_regs_set {
#define BCM_6348_TIMER_BASE (0xfffe0200) #define BCM_6348_TIMER_BASE (0xfffe0200)
#define BCM_6348_WDT_BASE (0xfffe021c) #define BCM_6348_WDT_BASE (0xfffe021c)
#define BCM_6348_UART0_BASE (0xfffe0300) #define BCM_6348_UART0_BASE (0xfffe0300)
#define BCM_6348_UART1_BASE (0xdeadbeef)
#define BCM_6348_GPIO_BASE (0xfffe0400) #define BCM_6348_GPIO_BASE (0xfffe0400)
#define BCM_6348_SPI_BASE (0xfffe0c00) #define BCM_6348_SPI_BASE (0xfffe0c00)
#define BCM_6348_UDC0_BASE (0xfffe1000) #define BCM_6348_UDC0_BASE (0xfffe1000)
...@@ -208,6 +212,7 @@ enum bcm63xx_regs_set { ...@@ -208,6 +212,7 @@ enum bcm63xx_regs_set {
#define BCM_6358_TIMER_BASE (0xfffe0040) #define BCM_6358_TIMER_BASE (0xfffe0040)
#define BCM_6358_WDT_BASE (0xfffe005c) #define BCM_6358_WDT_BASE (0xfffe005c)
#define BCM_6358_UART0_BASE (0xfffe0100) #define BCM_6358_UART0_BASE (0xfffe0100)
#define BCM_6358_UART1_BASE (0xfffe0120)
#define BCM_6358_GPIO_BASE (0xfffe0080) #define BCM_6358_GPIO_BASE (0xfffe0080)
#define BCM_6358_SPI_BASE (0xdeadbeef) #define BCM_6358_SPI_BASE (0xdeadbeef)
#define BCM_6358_UDC0_BASE (0xfffe0800) #define BCM_6358_UDC0_BASE (0xfffe0800)
...@@ -246,6 +251,8 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) ...@@ -246,6 +251,8 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
return BCM_6338_WDT_BASE; return BCM_6338_WDT_BASE;
case RSET_UART0: case RSET_UART0:
return BCM_6338_UART0_BASE; return BCM_6338_UART0_BASE;
case RSET_UART1:
return BCM_6338_UART1_BASE;
case RSET_GPIO: case RSET_GPIO:
return BCM_6338_GPIO_BASE; return BCM_6338_GPIO_BASE;
case RSET_SPI: case RSET_SPI:
...@@ -292,6 +299,8 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) ...@@ -292,6 +299,8 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
return BCM_6345_WDT_BASE; return BCM_6345_WDT_BASE;
case RSET_UART0: case RSET_UART0:
return BCM_6345_UART0_BASE; return BCM_6345_UART0_BASE;
case RSET_UART1:
return BCM_6345_UART1_BASE;
case RSET_GPIO: case RSET_GPIO:
return BCM_6345_GPIO_BASE; return BCM_6345_GPIO_BASE;
case RSET_SPI: case RSET_SPI:
...@@ -338,6 +347,8 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) ...@@ -338,6 +347,8 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
return BCM_6348_WDT_BASE; return BCM_6348_WDT_BASE;
case RSET_UART0: case RSET_UART0:
return BCM_6348_UART0_BASE; return BCM_6348_UART0_BASE;
case RSET_UART1:
return BCM_6348_UART1_BASE;
case RSET_GPIO: case RSET_GPIO:
return BCM_6348_GPIO_BASE; return BCM_6348_GPIO_BASE;
case RSET_SPI: case RSET_SPI:
...@@ -384,6 +395,8 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) ...@@ -384,6 +395,8 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
return BCM_6358_WDT_BASE; return BCM_6358_WDT_BASE;
case RSET_UART0: case RSET_UART0:
return BCM_6358_UART0_BASE; return BCM_6358_UART0_BASE;
case RSET_UART1:
return BCM_6358_UART1_BASE;
case RSET_GPIO: case RSET_GPIO:
return BCM_6358_GPIO_BASE; return BCM_6358_GPIO_BASE;
case RSET_SPI: case RSET_SPI:
...@@ -429,6 +442,7 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) ...@@ -429,6 +442,7 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
enum bcm63xx_irq { enum bcm63xx_irq {
IRQ_TIMER = 0, IRQ_TIMER = 0,
IRQ_UART0, IRQ_UART0,
IRQ_UART1,
IRQ_DSL, IRQ_DSL,
IRQ_ENET0, IRQ_ENET0,
IRQ_ENET1, IRQ_ENET1,
...@@ -510,6 +524,7 @@ enum bcm63xx_irq { ...@@ -510,6 +524,7 @@ enum bcm63xx_irq {
*/ */
#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
......
arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h 0 → 100644
View file @ 524ef29c
#ifndef BCM63XX_DEV_UART_H_
#define BCM63XX_DEV_UART_H_
int bcm63xx_uart_register(unsigned int id);
#endif /* BCM63XX_DEV_UART_H_ */
arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
View file @ 524ef29c
...@@ -45,6 +45,8 @@ struct board_info { ...@@ -45,6 +45,8 @@ struct board_info {
unsigned int has_ohci0:1; unsigned int has_ohci0:1;
unsigned int has_ehci0:1; unsigned int has_ehci0:1;
unsigned int has_dsp:1; unsigned int has_dsp:1;
unsigned int has_uart0:1;
unsigned int has_uart1:1;
/* ethernet config */ /* ethernet config */
struct bcm63xx_enet_platform_data enet0; struct bcm63xx_enet_platform_data enet0;
......
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