clk: sunxi-ng: a64: Add constraints on PLL-MIPI's n/m ratio and parent rate

The Allwinner A64 manual lists the following constraints for the
PLL-MIPI clock:
 - M/N <= 3
 - (PLL_VIDEO0)/M >= 24MHz

Use these constraints.
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20240310-pinephone-pll-fixes-v4-4-46fc80c83637@oltmanns.devSigned-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>

drivers/clk/sunxi-ng/ccu-sun50i-a64.c

@@ -176,6 +176,8 @@ static struct ccu_nkm pll_mipi_clk = {
 	.n			= _SUNXI_CCU_MULT(8, 4),
 	.k			= _SUNXI_CCU_MULT_MIN(4, 2, 2),
 	.m			= _SUNXI_CCU_DIV(0, 4),
+	.max_m_n_ratio		= 3,
+	.min_parent_m_ratio	= 24000000,
 	.common		= {
 		.reg		= 0x040,
 		.hw.init	= CLK_HW_INIT("pll-mipi", "pll-video0",