Commit 52b2416c authored by Changbin Du's avatar Changbin Du Committed by Joonas Lahtinen

drm/i915: Add new vGPU cap info bit VGT_CAPS_HUGE_GTT

This adds a new vGPU cap info bit VGT_CAPS_HUGE_GTT, which is to detect
whether the host supports shadowing of huge gtt pages. If host does
support it, remove the page sizes restriction for vGPU.
Signed-off-by: default avatarChangbin Du <changbin.du@intel.com>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1525770425-5373-1-git-send-email-changbin.du@intel.com
parent 6ceb7277
...@@ -5409,12 +5409,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv) ...@@ -5409,12 +5409,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
{ {
int ret; int ret;
/* /* We need to fallback to 4K pages if host doesn't support huge gtt. */
* We need to fallback to 4K pages since gvt gtt handling doesn't if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
* support huge page entries - we will need to check either hypervisor
* mm can support huge guest page or just do emulation in gvt.
*/
if (intel_vgpu_active(dev_priv))
mkwrite_device_info(dev_priv)->page_sizes = mkwrite_device_info(dev_priv)->page_sizes =
I915_GTT_PAGE_SIZE_4K; I915_GTT_PAGE_SIZE_4K;
......
...@@ -54,6 +54,7 @@ enum vgt_g2v_type { ...@@ -54,6 +54,7 @@ enum vgt_g2v_type {
*/ */
#define VGT_CAPS_FULL_48BIT_PPGTT BIT(2) #define VGT_CAPS_FULL_48BIT_PPGTT BIT(2)
#define VGT_CAPS_HWSP_EMULATION BIT(3) #define VGT_CAPS_HWSP_EMULATION BIT(3)
#define VGT_CAPS_HUGE_GTT BIT(4)
struct vgt_if { struct vgt_if {
u64 magic; /* VGT_MAGIC */ u64 magic; /* VGT_MAGIC */
......
...@@ -36,6 +36,12 @@ intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv) ...@@ -36,6 +36,12 @@ intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
return dev_priv->vgpu.caps & VGT_CAPS_HWSP_EMULATION; return dev_priv->vgpu.caps & VGT_CAPS_HWSP_EMULATION;
} }
static inline bool
intel_vgpu_has_huge_gtt(struct drm_i915_private *dev_priv)
{
return dev_priv->vgpu.caps & VGT_CAPS_HUGE_GTT;
}
int intel_vgt_balloon(struct drm_i915_private *dev_priv); int intel_vgt_balloon(struct drm_i915_private *dev_priv);
void intel_vgt_deballoon(struct drm_i915_private *dev_priv); void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
......
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