Commit 53263a1c authored by John Crispin's avatar John Crispin Committed by Ralf Baechle

MIPS: ralink: add mt7628an support

Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8031/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 1dc5c2cf
...@@ -13,6 +13,13 @@ ...@@ -13,6 +13,13 @@
#ifndef _MT7620_REGS_H_ #ifndef _MT7620_REGS_H_
#define _MT7620_REGS_H_ #define _MT7620_REGS_H_
enum mt762x_soc_type {
MT762X_SOC_UNKNOWN = 0,
MT762X_SOC_MT7620A,
MT762X_SOC_MT7620N,
MT762X_SOC_MT7628AN,
};
#define MT7620_SYSC_BASE 0x10000000 #define MT7620_SYSC_BASE 0x10000000
#define SYSC_REG_CHIP_NAME0 0x00 #define SYSC_REG_CHIP_NAME0 0x00
...@@ -27,6 +34,7 @@ ...@@ -27,6 +34,7 @@
#define MT7620_CHIP_NAME0 0x3637544d #define MT7620_CHIP_NAME0 0x3637544d
#define MT7620_CHIP_NAME1 0x20203032 #define MT7620_CHIP_NAME1 0x20203032
#define MT7628_CHIP_NAME1 0x20203832
#define SYSCFG0_XTAL_FREQ_SEL BIT(6) #define SYSCFG0_XTAL_FREQ_SEL BIT(6)
...@@ -71,6 +79,9 @@ ...@@ -71,6 +79,9 @@
#define SYSCFG0_DRAM_TYPE_DDR1 1 #define SYSCFG0_DRAM_TYPE_DDR1 1
#define SYSCFG0_DRAM_TYPE_DDR2 2 #define SYSCFG0_DRAM_TYPE_DDR2 2
#define SYSCFG0_DRAM_TYPE_DDR2_MT7628 0
#define SYSCFG0_DRAM_TYPE_DDR1_MT7628 1
#define MT7620_DRAM_BASE 0x0 #define MT7620_DRAM_BASE 0x0
#define MT7620_SDRAM_SIZE_MIN 2 #define MT7620_SDRAM_SIZE_MIN 2
#define MT7620_SDRAM_SIZE_MAX 64 #define MT7620_SDRAM_SIZE_MAX 64
......
...@@ -26,7 +26,7 @@ choice ...@@ -26,7 +26,7 @@ choice
select HW_HAS_PCI select HW_HAS_PCI
config SOC_MT7620 config SOC_MT7620
bool "MT7620" bool "MT7620/8"
endchoice endchoice
......
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