Commit 534baf55 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'next/move' of git://git.linaro.org/people/arnd/arm-soc

* 'next/move' of git://git.linaro.org/people/arnd/arm-soc:
  ARM: EXYNOS: Add ARCH_EXYNOS and reorganize arch/arm/mach-exynos
  ARM: EXYNOS4: convert MCT to percpu interrupt API
  ARM: SAMSUNG: Add clk enable/disable of pwm
  ARM: SAMSUNG: Fix compile error due to kfree
parents ddf8a0d3 83014579
...@@ -837,8 +837,8 @@ config ARCH_S5PV210 ...@@ -837,8 +837,8 @@ config ARCH_S5PV210
help help
Samsung S5PV210/S5PC110 series based systems Samsung S5PV210/S5PC110 series based systems
config ARCH_EXYNOS4 config ARCH_EXYNOS
bool "Samsung EXYNOS4" bool "SAMSUNG EXYNOS"
select CPU_V7 select CPU_V7
select ARCH_SPARSEMEM_ENABLE select ARCH_SPARSEMEM_ENABLE
select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_HAS_HOLES_MEMORYMODEL
...@@ -852,7 +852,7 @@ config ARCH_EXYNOS4 ...@@ -852,7 +852,7 @@ config ARCH_EXYNOS4
select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C2410_WATCHDOG if WATCHDOG
select NEED_MACH_MEMORY_H select NEED_MACH_MEMORY_H
help help
Samsung EXYNOS4 series based systems Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
config ARCH_SHARK config ARCH_SHARK
bool "Shark" bool "Shark"
...@@ -1079,7 +1079,7 @@ source "arch/arm/mach-s5pc100/Kconfig" ...@@ -1079,7 +1079,7 @@ source "arch/arm/mach-s5pc100/Kconfig"
source "arch/arm/mach-s5pv210/Kconfig" source "arch/arm/mach-s5pv210/Kconfig"
source "arch/arm/mach-exynos4/Kconfig" source "arch/arm/mach-exynos/Kconfig"
source "arch/arm/mach-shmobile/Kconfig" source "arch/arm/mach-shmobile/Kconfig"
......
...@@ -180,7 +180,7 @@ machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx ...@@ -180,7 +180,7 @@ machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx
machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0 machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
machine-$(CONFIG_ARCH_S5PC100) := s5pc100 machine-$(CONFIG_ARCH_S5PC100) := s5pc100
machine-$(CONFIG_ARCH_S5PV210) := s5pv210 machine-$(CONFIG_ARCH_S5PV210) := s5pv210
machine-$(CONFIG_ARCH_EXYNOS4) := exynos4 machine-$(CONFIG_ARCH_EXYNOS4) := exynos
machine-$(CONFIG_ARCH_SA1100) := sa1100 machine-$(CONFIG_ARCH_SA1100) := sa1100
machine-$(CONFIG_ARCH_SHARK) := shark machine-$(CONFIG_ARCH_SHARK) := shark
machine-$(CONFIG_ARCH_SHMOBILE) := shmobile machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
......
...@@ -4,19 +4,18 @@ CONFIG_KALLSYMS_ALL=y ...@@ -4,19 +4,18 @@ CONFIG_KALLSYMS_ALL=y
CONFIG_MODULES=y CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_EXYNOS4=y CONFIG_ARCH_EXYNOS=y
CONFIG_S3C_LOWLEVEL_UART_PORT=1 CONFIG_S3C_LOWLEVEL_UART_PORT=1
CONFIG_MACH_SMDKC210=y CONFIG_MACH_SMDKC210=y
CONFIG_MACH_SMDKV310=y
CONFIG_MACH_ARMLEX4210=y CONFIG_MACH_ARMLEX4210=y
CONFIG_MACH_UNIVERSAL_C210=y CONFIG_MACH_UNIVERSAL_C210=y
CONFIG_MACH_NURI=y CONFIG_MACH_NURI=y
CONFIG_MACH_ORIGEN=y CONFIG_MACH_ORIGEN=y
CONFIG_MACH_SMDK4412=y
CONFIG_NO_HZ=y CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y CONFIG_HIGH_RES_TIMERS=y
CONFIG_SMP=y CONFIG_SMP=y
CONFIG_NR_CPUS=2 CONFIG_NR_CPUS=2
CONFIG_HOTPLUG_CPU=y
CONFIG_PREEMPT=y CONFIG_PREEMPT=y
CONFIG_AEABI=y CONFIG_AEABI=y
CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M" CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
...@@ -61,13 +60,9 @@ CONFIG_DETECT_HUNG_TASK=y ...@@ -61,13 +60,9 @@ CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_SPINLOCK_SLEEP=y
CONFIG_DEBUG_INFO=y CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_DEBUG_USER=y CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
CONFIG_DEBUG_LL=y CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y CONFIG_EARLY_PRINTK=y
CONFIG_DEBUG_S3C_UART=1
CONFIG_CRC_CCITT=y CONFIG_CRC_CCITT=y
# arch/arm/mach-exynos4/Kconfig # arch/arm/mach-exynos/Kconfig
# #
# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. # Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
# http://www.samsung.com/ # http://www.samsung.com/
...@@ -7,10 +7,27 @@ ...@@ -7,10 +7,27 @@
# Configuration options for the EXYNOS4 # Configuration options for the EXYNOS4
if ARCH_EXYNOS4 if ARCH_EXYNOS
menu "SAMSUNG EXYNOS SoCs Support"
choice
prompt "EXYNOS System Type"
default ARCH_EXYNOS4
config ARCH_EXYNOS4
bool "SAMSUNG EXYNOS4"
help
Samsung EXYNOS4 SoCs based systems
endchoice
comment "EXYNOS SoCs"
config CPU_EXYNOS4210 config CPU_EXYNOS4210
bool bool "SAMSUNG EXYNOS4210"
default y
depends on ARCH_EXYNOS4
select SAMSUNG_DMADEV select SAMSUNG_DMADEV
select ARM_CPU_SUSPEND if PM select ARM_CPU_SUSPEND if PM
select S5P_PM if PM select S5P_PM if PM
...@@ -19,15 +36,18 @@ config CPU_EXYNOS4210 ...@@ -19,15 +36,18 @@ config CPU_EXYNOS4210
Enable EXYNOS4210 CPU support Enable EXYNOS4210 CPU support
config SOC_EXYNOS4212 config SOC_EXYNOS4212
bool bool "SAMSUNG EXYNOS4212"
select ARM_CPU_SUSPEND if PM default y
depends on ARCH_EXYNOS4
select S5P_PM if PM select S5P_PM if PM
select S5P_SLEEP if PM select S5P_SLEEP if PM
help help
Enable EXYNOS4212 SoC support Enable EXYNOS4212 SoC support
config SOC_EXYNOS4412 config SOC_EXYNOS4412
bool bool "SAMSUNG EXYNOS4412"
default y
depends on ARCH_EXYNOS4
help help
Enable EXYNOS4412 SoC support Enable EXYNOS4412 SoC support
...@@ -125,7 +145,7 @@ config EXYNOS4_SETUP_USB_PHY ...@@ -125,7 +145,7 @@ config EXYNOS4_SETUP_USB_PHY
# machine support # machine support
menu "EXYNOS4 Machines" if ARCH_EXYNOS4
comment "EXYNOS4210 Boards" comment "EXYNOS4210 Boards"
...@@ -305,12 +325,11 @@ config MACH_SMDK4412 ...@@ -305,12 +325,11 @@ config MACH_SMDK4412
select MACH_SMDK4212 select MACH_SMDK4212
help help
Machine support for Samsung SMDK4412 Machine support for Samsung SMDK4412
endif
endmenu if ARCH_EXYNOS4
comment "Configuration for HSMMC bus width"
menu "Use 8-bit bus width" comment "Configuration for HSMMC 8-bit bus width"
config EXYNOS4_SDHCI_CH0_8BIT config EXYNOS4_SDHCI_CH0_8BIT
bool "Channel 0 with 8-bit bus" bool "Channel 0 with 8-bit bus"
...@@ -323,6 +342,7 @@ config EXYNOS4_SDHCI_CH2_8BIT ...@@ -323,6 +342,7 @@ config EXYNOS4_SDHCI_CH2_8BIT
help help
Support HSMMC Channel 2 8-bit bus. Support HSMMC Channel 2 8-bit bus.
If selected, Channel 3 is disabled. If selected, Channel 3 is disabled.
endif
endmenu endmenu
......
# arch/arm/mach-exynos4/Makefile # arch/arm/mach-exynos/Makefile
# #
# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. # Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
# http://www.samsung.com/ # http://www.samsung.com/
...@@ -12,8 +12,8 @@ obj- := ...@@ -12,8 +12,8 @@ obj- :=
# Core support for EXYNOS4 system # Core support for EXYNOS4 system
obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o setup-i2c0.o
obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o irq-eint.o dma.o pmu.o obj-$(CONFIG_ARCH_EXYNOS4) += irq-eint.o dma.o pmu.o
obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_PM) += pm.o
...@@ -39,11 +39,11 @@ obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o ...@@ -39,11 +39,11 @@ obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o
# device support # device support
obj-y += dev-audio.o obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
...@@ -57,5 +57,4 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o ...@@ -57,5 +57,4 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o
/* linux/arch/arm/mach-exynos4/cpu.c /* linux/arch/arm/mach-exynos/cpu.c
* *
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com * http://www.samsung.com
...@@ -40,27 +40,46 @@ extern int combiner_init(unsigned int combiner_nr, void __iomem *base, ...@@ -40,27 +40,46 @@ extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq); extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
/* Initial IO mappings */ /* Initial IO mappings */
static struct map_desc exynos4_iodesc[] __initdata = { static struct map_desc exynos_iodesc[] __initdata = {
{ {
.virtual = (unsigned long)S5P_VA_SYSTIMER, .virtual = (unsigned long)S5P_VA_SYSTIMER,
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER), .pfn = __phys_to_pfn(EXYNOS_PA_SYSTIMER),
.length = SZ_4K, .length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_CMU,
.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
.length = SZ_128K,
.type = MT_DEVICE, .type = MT_DEVICE,
}, { }, {
.virtual = (unsigned long)S5P_VA_PMU, .virtual = (unsigned long)S5P_VA_PMU,
.pfn = __phys_to_pfn(EXYNOS4_PA_PMU), .pfn = __phys_to_pfn(EXYNOS_PA_PMU),
.length = SZ_64K, .length = SZ_64K,
.type = MT_DEVICE, .type = MT_DEVICE,
}, { }, {
.virtual = (unsigned long)S5P_VA_COMBINER_BASE, .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
.pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER), .pfn = __phys_to_pfn(EXYNOS_PA_COMBINER),
.length = SZ_4K, .length = SZ_4K,
.type = MT_DEVICE, .type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GIC_CPU,
.pfn = __phys_to_pfn(EXYNOS_PA_GIC_CPU),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GIC_DIST,
.pfn = __phys_to_pfn(EXYNOS_PA_GIC_DIST),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(S3C_PA_UART),
.length = SZ_512K,
.type = MT_DEVICE,
},
};
static struct map_desc exynos4_iodesc[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_CMU,
.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
.length = SZ_128K,
.type = MT_DEVICE,
}, { }, {
.virtual = (unsigned long)S5P_VA_COREPERI_BASE, .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
.pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI), .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
...@@ -91,11 +110,6 @@ static struct map_desc exynos4_iodesc[] __initdata = { ...@@ -91,11 +110,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS4_PA_DMC0), .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
.length = SZ_4K, .length = SZ_4K,
.type = MT_DEVICE, .type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(S3C_PA_UART),
.length = SZ_512K,
.type = MT_DEVICE,
}, { }, {
.virtual = (unsigned long)S5P_VA_SROMC, .virtual = (unsigned long)S5P_VA_SROMC,
.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC), .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
...@@ -106,16 +120,6 @@ static struct map_desc exynos4_iodesc[] __initdata = { ...@@ -106,16 +120,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY), .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
.length = SZ_4K, .length = SZ_4K,
.type = MT_DEVICE, .type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GIC_CPU,
.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GIC_DIST,
.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
.length = SZ_64K,
.type = MT_DEVICE,
}, },
}; };
...@@ -137,7 +141,7 @@ static struct map_desc exynos4_iodesc1[] __initdata = { ...@@ -137,7 +141,7 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
}, },
}; };
static void exynos4_idle(void) static void exynos_idle(void)
{ {
if (!need_resched()) if (!need_resched())
cpu_do_idle(); cpu_do_idle();
...@@ -151,12 +155,13 @@ static void exynos4_sw_reset(void) ...@@ -151,12 +155,13 @@ static void exynos4_sw_reset(void)
} }
/* /*
* exynos4_map_io * exynos_map_io
* *
* register the standard cpu IO areas * register the standard cpu IO areas
*/ */
void __init exynos4_map_io(void) void __init exynos4_map_io(void)
{ {
iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0) if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
...@@ -250,7 +255,6 @@ static int __init exynos4_core_init(void) ...@@ -250,7 +255,6 @@ static int __init exynos4_core_init(void)
{ {
return sysdev_class_register(&exynos4_sysclass); return sysdev_class_register(&exynos4_sysclass);
} }
core_initcall(exynos4_core_init); core_initcall(exynos4_core_init);
#ifdef CONFIG_CACHE_L2X0 #ifdef CONFIG_CACHE_L2X0
...@@ -279,15 +283,16 @@ static int __init exynos4_l2x0_cache_init(void) ...@@ -279,15 +283,16 @@ static int __init exynos4_l2x0_cache_init(void)
early_initcall(exynos4_l2x0_cache_init); early_initcall(exynos4_l2x0_cache_init);
#endif #endif
int __init exynos4_init(void) int __init exynos_init(void)
{ {
printk(KERN_INFO "EXYNOS4: Initializing architecture\n"); printk(KERN_INFO "EXYNOS: Initializing architecture\n");
/* set idle function */ /* set idle function */
pm_idle = exynos4_idle; pm_idle = exynos_idle;
/* set sw_reset function */ /* set sw_reset function */
s5p_reset_hook = exynos4_sw_reset; if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
s5p_reset_hook = exynos4_sw_reset;
return sysdev_register(&exynos4_sysdev); return sysdev_register(&exynos4_sysdev);
} }
/* linux/arch/arm/mach-exynos4/include/mach/map.h /* linux/arch/arm/mach-exynos/include/mach/map.h
* *
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/ * http://www.samsung.com/
...@@ -145,39 +145,45 @@ ...@@ -145,39 +145,45 @@
#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5) #define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6) #define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7) #define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
#define S3C_PA_RTC EXYNOS4_PA_RTC #define S3C_PA_RTC EXYNOS4_PA_RTC
#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG #define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
#define S3C_PA_UART EXYNOS4_PA_UART
#define S5P_PA_CHIPID EXYNOS4_PA_CHIPID #define S5P_PA_CHIPID EXYNOS4_PA_CHIPID
#define S5P_PA_EHCI EXYNOS4_PA_EHCI
#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0 #define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1 #define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2 #define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2
#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3 #define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
#define S5P_PA_HDMI EXYNOS4_PA_HDMI
#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
#define S5P_PA_MFC EXYNOS4_PA_MFC
#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0 #define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1 #define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0 #define S5P_PA_MIXER EXYNOS4_PA_MIXER
#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND #define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA #define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
#define S5P_PA_SDO EXYNOS4_PA_SDO
#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM #define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
#define S5P_PA_SROMC EXYNOS4_PA_SROMC #define S5P_PA_SROMC EXYNOS4_PA_SROMC
#define S5P_PA_MFC EXYNOS4_PA_MFC
#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON #define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
#define S5P_PA_TIMER EXYNOS4_PA_TIMER #define S5P_PA_TIMER EXYNOS4_PA_TIMER
#define S5P_PA_EHCI EXYNOS4_PA_EHCI
#define S5P_PA_SDO EXYNOS4_PA_SDO
#define S5P_PA_VP EXYNOS4_PA_VP #define S5P_PA_VP EXYNOS4_PA_VP
#define S5P_PA_MIXER EXYNOS4_PA_MIXER
#define S5P_PA_HDMI EXYNOS4_PA_HDMI
#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD #define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
/* UART */ #define EXYNOS_PA_COMBINER EXYNOS4_PA_COMBINER
#define EXYNOS_PA_GIC_CPU EXYNOS4_PA_GIC_CPU
#define EXYNOS_PA_GIC_DIST EXYNOS4_PA_GIC_DIST
#define EXYNOS_PA_PMU EXYNOS4_PA_PMU
#define EXYNOS_PA_SYSTIMER EXYNOS4_PA_SYSTIMER
#define S3C_PA_UART EXYNOS4_PA_UART /* Compatibility UART */
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) #define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_PA_UART0 S5P_PA_UART(0) #define S5P_PA_UART0 S5P_PA_UART(0)
......
...@@ -44,7 +44,7 @@ struct mct_clock_event_device { ...@@ -44,7 +44,7 @@ struct mct_clock_event_device {
char name[10]; char name[10];
}; };
struct mct_clock_event_device mct_tick[NR_CPUS]; static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
static void exynos4_mct_write(unsigned int value, void *addr) static void exynos4_mct_write(unsigned int value, void *addr)
{ {
...@@ -302,7 +302,7 @@ static void exynos4_mct_tick_start(unsigned long cycles, ...@@ -302,7 +302,7 @@ static void exynos4_mct_tick_start(unsigned long cycles,
static int exynos4_tick_set_next_event(unsigned long cycles, static int exynos4_tick_set_next_event(unsigned long cycles,
struct clock_event_device *evt) struct clock_event_device *evt)
{ {
struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()]; struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
exynos4_mct_tick_start(cycles, mevt); exynos4_mct_tick_start(cycles, mevt);
...@@ -312,7 +312,7 @@ static int exynos4_tick_set_next_event(unsigned long cycles, ...@@ -312,7 +312,7 @@ static int exynos4_tick_set_next_event(unsigned long cycles,
static inline void exynos4_tick_set_mode(enum clock_event_mode mode, static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt) struct clock_event_device *evt)
{ {
struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()]; struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
exynos4_mct_tick_stop(mevt); exynos4_mct_tick_stop(mevt);
...@@ -376,14 +376,16 @@ static struct irqaction mct_tick1_event_irq = { ...@@ -376,14 +376,16 @@ static struct irqaction mct_tick1_event_irq = {
static void exynos4_mct_tick_init(struct clock_event_device *evt) static void exynos4_mct_tick_init(struct clock_event_device *evt)
{ {
struct mct_clock_event_device *mevt;
unsigned int cpu = smp_processor_id(); unsigned int cpu = smp_processor_id();
mct_tick[cpu].evt = evt; mevt = this_cpu_ptr(&percpu_mct_tick);
mevt->evt = evt;
mct_tick[cpu].base = EXYNOS4_MCT_L_BASE(cpu); mevt->base = EXYNOS4_MCT_L_BASE(cpu);
sprintf(mct_tick[cpu].name, "mct_tick%d", cpu); sprintf(mevt->name, "mct_tick%d", cpu);
evt->name = mct_tick[cpu].name; evt->name = mevt->name;
evt->cpumask = cpumask_of(cpu); evt->cpumask = cpumask_of(cpu);
evt->set_next_event = exynos4_tick_set_next_event; evt->set_next_event = exynos4_tick_set_next_event;
evt->set_mode = exynos4_tick_set_mode; evt->set_mode = exynos4_tick_set_mode;
...@@ -398,21 +400,21 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt) ...@@ -398,21 +400,21 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
clockevents_register_device(evt); clockevents_register_device(evt);
exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET); exynos4_mct_write(0x1, mevt->base + MCT_L_TCNTB_OFFSET);
if (mct_int_type == MCT_INT_SPI) { if (mct_int_type == MCT_INT_SPI) {
if (cpu == 0) { if (cpu == 0) {
mct_tick0_event_irq.dev_id = &mct_tick[cpu]; mct_tick0_event_irq.dev_id = mevt;
evt->irq = IRQ_MCT_L0; evt->irq = IRQ_MCT_L0;
setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq); setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
} else { } else {
mct_tick1_event_irq.dev_id = &mct_tick[cpu]; mct_tick1_event_irq.dev_id = mevt;
evt->irq = IRQ_MCT_L1; evt->irq = IRQ_MCT_L1;
setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq); setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
irq_set_affinity(IRQ_MCT_L1, cpumask_of(1)); irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
} }
} else { } else {
gic_enable_ppi(IRQ_MCT_LOCALTIMER); enable_percpu_irq(IRQ_MCT_LOCALTIMER, 0);
} }
} }
...@@ -427,9 +429,11 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt) ...@@ -427,9 +429,11 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt)
void local_timer_stop(struct clock_event_device *evt) void local_timer_stop(struct clock_event_device *evt)
{ {
evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt); evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
disable_irq(evt->irq); if (mct_int_type == MCT_INT_SPI)
disable_irq(evt->irq);
else
disable_percpu_irq(IRQ_MCT_LOCALTIMER);
} }
#endif /* CONFIG_LOCAL_TIMERS */ #endif /* CONFIG_LOCAL_TIMERS */
static void __init exynos4_timer_resources(void) static void __init exynos4_timer_resources(void)
...@@ -438,6 +442,16 @@ static void __init exynos4_timer_resources(void) ...@@ -438,6 +442,16 @@ static void __init exynos4_timer_resources(void)
mct_clk = clk_get(NULL, "xtal"); mct_clk = clk_get(NULL, "xtal");
clk_rate = clk_get_rate(mct_clk); clk_rate = clk_get_rate(mct_clk);
if (mct_int_type == MCT_INT_PPI) {
int err;
err = request_percpu_irq(IRQ_MCT_LOCALTIMER,
exynos4_mct_tick_isr, "MCT",
&percpu_mct_tick);
WARN(err, "MCT: can't request IRQ %d (%d)\n",
IRQ_MCT_LOCALTIMER, err);
}
} }
static void __init exynos4_timer_init(void) static void __init exynos4_timer_init(void)
......
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
config PLAT_S5P config PLAT_S5P
bool bool
depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4) depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
default y default y
select ARM_VIC if !ARCH_EXYNOS4 select ARM_VIC if !ARCH_EXYNOS4
select ARM_GIC if ARCH_EXYNOS4 select ARM_GIC if ARCH_EXYNOS4
......
...@@ -75,7 +75,7 @@ static struct cpu_table cpu_ids[] __initdata = { ...@@ -75,7 +75,7 @@ static struct cpu_table cpu_ids[] __initdata = {
.map_io = exynos4_map_io, .map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks, .init_clocks = exynos4_init_clocks,
.init_uarts = exynos4_init_uarts, .init_uarts = exynos4_init_uarts,
.init = exynos4_init, .init = exynos_init,
.name = name_exynos4210, .name = name_exynos4210,
}, { }, {
.idcode = EXYNOS4212_CPU_ID, .idcode = EXYNOS4212_CPU_ID,
...@@ -83,7 +83,7 @@ static struct cpu_table cpu_ids[] __initdata = { ...@@ -83,7 +83,7 @@ static struct cpu_table cpu_ids[] __initdata = {
.map_io = exynos4_map_io, .map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks, .init_clocks = exynos4_init_clocks,
.init_uarts = exynos4_init_uarts, .init_uarts = exynos4_init_uarts,
.init = exynos4_init, .init = exynos_init,
.name = name_exynos4212, .name = name_exynos4212,
}, { }, {
.idcode = EXYNOS4412_CPU_ID, .idcode = EXYNOS4412_CPU_ID,
...@@ -91,7 +91,7 @@ static struct cpu_table cpu_ids[] __initdata = { ...@@ -91,7 +91,7 @@ static struct cpu_table cpu_ids[] __initdata = {
.map_io = exynos4_map_io, .map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks, .init_clocks = exynos4_init_clocks,
.init_uarts = exynos4_init_uarts, .init_uarts = exynos4_init_uarts,
.init = exynos4_init, .init = exynos_init,
.name = name_exynos4412, .name = name_exynos4412,
}, },
}; };
......
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/pwm_backlight.h> #include <linux/pwm_backlight.h>
#include <linux/slab.h>
#include <plat/devs.h> #include <plat/devs.h>
#include <plat/gpio-cfg.h> #include <plat/gpio-cfg.h>
......
...@@ -18,8 +18,8 @@ extern void exynos4210_register_clocks(void); ...@@ -18,8 +18,8 @@ extern void exynos4210_register_clocks(void);
extern void exynos4212_register_clocks(void); extern void exynos4212_register_clocks(void);
extern void exynos4_setup_clocks(void); extern void exynos4_setup_clocks(void);
#ifdef CONFIG_ARCH_EXYNOS4 #ifdef CONFIG_ARCH_EXYNOS
extern int exynos4_init(void); extern int exynos_init(void);
extern void exynos4_init_irq(void); extern void exynos4_init_irq(void);
extern void exynos4_map_io(void); extern void exynos4_map_io(void);
extern void exynos4_init_clocks(int xtal); extern void exynos4_init_clocks(int xtal);
...@@ -31,5 +31,5 @@ extern struct sys_timer exynos4_timer; ...@@ -31,5 +31,5 @@ extern struct sys_timer exynos4_timer;
#define exynos4_init_clocks NULL #define exynos4_init_clocks NULL
#define exynos4_init_uarts NULL #define exynos4_init_uarts NULL
#define exynos4_map_io NULL #define exynos4_map_io NULL
#define exynos4_init NULL #define exynos_init NULL
#endif #endif
...@@ -299,6 +299,9 @@ static int s3c_pwm_probe(struct platform_device *pdev) ...@@ -299,6 +299,9 @@ static int s3c_pwm_probe(struct platform_device *pdev)
goto err_clk_tin; goto err_clk_tin;
} }
clk_enable(pwm->clk);
clk_enable(pwm->clk_div);
local_irq_save(flags); local_irq_save(flags);
tcon = __raw_readl(S3C2410_TCON); tcon = __raw_readl(S3C2410_TCON);
...@@ -326,6 +329,8 @@ static int s3c_pwm_probe(struct platform_device *pdev) ...@@ -326,6 +329,8 @@ static int s3c_pwm_probe(struct platform_device *pdev)
return 0; return 0;
err_clk_tdiv: err_clk_tdiv:
clk_disable(pwm->clk_div);
clk_disable(pwm->clk);
clk_put(pwm->clk_div); clk_put(pwm->clk_div);
err_clk_tin: err_clk_tin:
...@@ -340,6 +345,8 @@ static int __devexit s3c_pwm_remove(struct platform_device *pdev) ...@@ -340,6 +345,8 @@ static int __devexit s3c_pwm_remove(struct platform_device *pdev)
{ {
struct pwm_device *pwm = platform_get_drvdata(pdev); struct pwm_device *pwm = platform_get_drvdata(pdev);
clk_disable(pwm->clk_div);
clk_disable(pwm->clk);
clk_put(pwm->clk_div); clk_put(pwm->clk_div);
clk_put(pwm->clk); clk_put(pwm->clk);
kfree(pwm); kfree(pwm);
......
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