Commit 544ae6b2 authored by Bo Shen's avatar Bo Shen Committed by Mark Brown

ARM: at91/dts: add pinctrl support for SSC peripheral

Add pinctrl support for SSC on AT91 dtsi files.
Signed-off-by: default avatarBo Shen <voice.shen@atmel.com>
[nicolas.ferre@atmel.com: split dtsi and driver changes]
Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
Reluctantly-acked-by: default avatarOlof Johansson <olof@lixom.net>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent 9931faca
...@@ -306,6 +306,22 @@ pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { ...@@ -306,6 +306,22 @@ pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
}; };
}; };
ssc0 {
pinctrl_ssc0_tx: ssc0_tx-0 {
atmel,pins =
<1 16 0x1 0x0 /* PB16 periph A */
1 17 0x1 0x0 /* PB17 periph A */
1 18 0x1 0x0>; /* PB18 periph A */
};
pinctrl_ssc0_rx: ssc0_rx-0 {
atmel,pins =
<1 19 0x1 0x0 /* PB19 periph A */
1 20 0x1 0x0 /* PB20 periph A */
1 21 0x1 0x0>; /* PB21 periph A */
};
};
pioA: gpio@fffff400 { pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio"; compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>; reg = <0xfffff400 0x200>;
...@@ -450,6 +466,8 @@ ssc0: ssc@fffbc000 { ...@@ -450,6 +466,8 @@ ssc0: ssc@fffbc000 {
compatible = "atmel,at91rm9200-ssc"; compatible = "atmel,at91rm9200-ssc";
reg = <0xfffbc000 0x4000>; reg = <0xfffbc000 0x4000>;
interrupts = <14 4 5>; interrupts = <14 4 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
status = "disabled"; status = "disabled";
}; };
......
...@@ -271,6 +271,38 @@ pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 { ...@@ -271,6 +271,38 @@ pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
}; };
}; };
ssc0 {
pinctrl_ssc0_tx: ssc0_tx-0 {
atmel,pins =
<1 0 0x2 0x0 /* PB0 periph B */
1 1 0x2 0x0 /* PB1 periph B */
1 2 0x2 0x0>; /* PB2 periph B */
};
pinctrl_ssc0_rx: ssc0_rx-0 {
atmel,pins =
<1 3 0x2 0x0 /* PB3 periph B */
1 4 0x2 0x0 /* PB4 periph B */
1 5 0x2 0x0>; /* PB5 periph B */
};
};
ssc1 {
pinctrl_ssc1_tx: ssc1_tx-0 {
atmel,pins =
<1 6 0x1 0x0 /* PB6 periph A */
1 7 0x1 0x0 /* PB7 periph A */
1 8 0x1 0x0>; /* PB8 periph A */
};
pinctrl_ssc1_rx: ssc1_rx-0 {
atmel,pins =
<1 9 0x1 0x0 /* PB9 periph A */
1 10 0x1 0x0 /* PB10 periph A */
1 11 0x1 0x0>; /* PB11 periph A */
};
};
pioA: gpio@fffff200 { pioA: gpio@fffff200 {
compatible = "atmel,at91rm9200-gpio"; compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x200>; reg = <0xfffff200 0x200>;
...@@ -368,6 +400,8 @@ ssc0: ssc@fff98000 { ...@@ -368,6 +400,8 @@ ssc0: ssc@fff98000 {
compatible = "atmel,at91rm9200-ssc"; compatible = "atmel,at91rm9200-ssc";
reg = <0xfff98000 0x4000>; reg = <0xfff98000 0x4000>;
interrupts = <16 4 5>; interrupts = <16 4 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
status = "disabled"; status = "disabled";
}; };
...@@ -375,6 +409,8 @@ ssc1: ssc@fff9c000 { ...@@ -375,6 +409,8 @@ ssc1: ssc@fff9c000 {
compatible = "atmel,at91rm9200-ssc"; compatible = "atmel,at91rm9200-ssc";
reg = <0xfff9c000 0x4000>; reg = <0xfff9c000 0x4000>;
interrupts = <17 4 5>; interrupts = <17 4 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
status = "disabled"; status = "disabled";
}; };
......
...@@ -290,6 +290,38 @@ pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 { ...@@ -290,6 +290,38 @@ pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
}; };
}; };
ssc0 {
pinctrl_ssc0_tx: ssc0_tx-0 {
atmel,pins =
<3 0 0x1 0x0 /* PD0 periph A */
3 1 0x1 0x0 /* PD1 periph A */
3 2 0x1 0x0>; /* PD2 periph A */
};
pinctrl_ssc0_rx: ssc0_rx-0 {
atmel,pins =
<3 3 0x1 0x0 /* PD3 periph A */
3 4 0x1 0x0 /* PD4 periph A */
3 5 0x1 0x0>; /* PD5 periph A */
};
};
ssc1 {
pinctrl_ssc1_tx: ssc1_tx-0 {
atmel,pins =
<3 10 0x1 0x0 /* PD10 periph A */
3 11 0x1 0x0 /* PD11 periph A */
3 12 0x1 0x0>; /* PD12 periph A */
};
pinctrl_ssc1_rx: ssc1_rx-0 {
atmel,pins =
<3 13 0x1 0x0 /* PD13 periph A */
3 14 0x1 0x0 /* PD14 periph A */
3 15 0x1 0x0>; /* PD15 periph A */
};
};
pioA: gpio@fffff200 { pioA: gpio@fffff200 {
compatible = "atmel,at91rm9200-gpio"; compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x200>; reg = <0xfffff200 0x200>;
...@@ -425,6 +457,8 @@ ssc0: ssc@fff9c000 { ...@@ -425,6 +457,8 @@ ssc0: ssc@fff9c000 {
compatible = "atmel,at91sam9g45-ssc"; compatible = "atmel,at91sam9g45-ssc";
reg = <0xfff9c000 0x4000>; reg = <0xfff9c000 0x4000>;
interrupts = <16 4 5>; interrupts = <16 4 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
status = "disabled"; status = "disabled";
}; };
...@@ -432,6 +466,8 @@ ssc1: ssc@fffa0000 { ...@@ -432,6 +466,8 @@ ssc1: ssc@fffa0000 {
compatible = "atmel,at91sam9g45-ssc"; compatible = "atmel,at91sam9g45-ssc";
reg = <0xfffa0000 0x4000>; reg = <0xfffa0000 0x4000>;
interrupts = <17 4 5>; interrupts = <17 4 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
status = "disabled"; status = "disabled";
}; };
......
...@@ -28,6 +28,7 @@ aliases { ...@@ -28,6 +28,7 @@ aliases {
tcb1 = &tcb1; tcb1 = &tcb1;
i2c0 = &i2c0; i2c0 = &i2c0;
i2c1 = &i2c1; i2c1 = &i2c1;
ssc0 = &ssc0;
}; };
cpus { cpus {
cpu@0 { cpu@0 {
...@@ -244,6 +245,22 @@ pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { ...@@ -244,6 +245,22 @@ pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
}; };
}; };
ssc0 {
pinctrl_ssc0_tx: ssc0_tx-0 {
atmel,pins =
<0 24 0x2 0x0 /* PA24 periph B */
0 25 0x2 0x0 /* PA25 periph B */
0 26 0x2 0x0>; /* PA26 periph B */
};
pinctrl_ssc0_rx: ssc0_rx-0 {
atmel,pins =
<0 27 0x2 0x0 /* PA27 periph B */
0 28 0x2 0x0 /* PA28 periph B */
0 29 0x2 0x0>; /* PA29 periph B */
};
};
pioA: gpio@fffff400 { pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>; reg = <0xfffff400 0x200>;
...@@ -294,6 +311,15 @@ dbgu: serial@fffff200 { ...@@ -294,6 +311,15 @@ dbgu: serial@fffff200 {
status = "disabled"; status = "disabled";
}; };
ssc0: ssc@f0010000 {
compatible = "atmel,at91sam9g45-ssc";
reg = <0xf0010000 0x4000>;
interrupts = <28 4 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
status = "disabled";
};
usart0: serial@f801c000 { usart0: serial@f801c000 {
compatible = "atmel,at91sam9260-usart"; compatible = "atmel,at91sam9260-usart";
reg = <0xf801c000 0x4000>; reg = <0xf801c000 0x4000>;
......
...@@ -88,13 +88,6 @@ pit: timer@fffffe30 { ...@@ -88,13 +88,6 @@ pit: timer@fffffe30 {
interrupts = <1 4 7>; interrupts = <1 4 7>;
}; };
ssc0: ssc@f0010000 {
compatible = "atmel,at91sam9g45-ssc";
reg = <0xf0010000 0x4000>;
interrupts = <28 4 5>;
status = "disabled";
};
tcb0: timer@f8008000 { tcb0: timer@f8008000 {
compatible = "atmel,at91sam9x5-tcb"; compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>; reg = <0xf8008000 0x100>;
...@@ -290,6 +283,22 @@ pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { ...@@ -290,6 +283,22 @@ pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
}; };
}; };
ssc0 {
pinctrl_ssc0_tx: ssc0_tx-0 {
atmel,pins =
<0 24 0x2 0x0 /* PA24 periph B */
0 25 0x2 0x0 /* PA25 periph B */
0 26 0x2 0x0>; /* PA26 periph B */
};
pinctrl_ssc0_rx: ssc0_rx-0 {
atmel,pins =
<0 27 0x2 0x0 /* PA27 periph B */
0 28 0x2 0x0 /* PA28 periph B */
0 29 0x2 0x0>; /* PA29 periph B */
};
};
pioA: gpio@fffff400 { pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>; reg = <0xfffff400 0x200>;
...@@ -333,6 +342,15 @@ pioD: gpio@fffffa00 { ...@@ -333,6 +342,15 @@ pioD: gpio@fffffa00 {
}; };
}; };
ssc0: ssc@f0010000 {
compatible = "atmel,at91sam9g45-ssc";
reg = <0xf0010000 0x4000>;
interrupts = <28 4 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
status = "disabled";
};
mmc0: mmc@f0008000 { mmc0: mmc@f0008000 {
compatible = "atmel,hsmci"; compatible = "atmel,hsmci";
reg = <0xf0008000 0x600>; reg = <0xf0008000 0x600>;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment