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Commit 54f5de6f authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
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perf vendor events intel: Update sapphirerapids to v1.12 

Summary from https://github.com/intel/perfmon/pull/68
 - Numerous uncore event additions and changes.
 - Description updates for core events XQ.FULL_CYCLES and MISC2_RETIRED.LFENCE.
 - Update ARITH.IDIV_ACTIVE counter mask.

This change also gets rid of uncore-other as a topic, derived from the
file name, breaking it apart in to more specific topics.
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: http://lore.kernel.org/lkml/20230413132949.3487664-2-irogers@google.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 4453deac
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Showing with 19122 additions and 221 deletions
tools/perf/pmu-events/arch/x86/mapfile.csv
View file @ 54f5de6f
......@@ -22,7 +22,7 @@ GenuineIntel-6-A[AC],v1.01,meteorlake,core
GenuineIntel-6-1[AEF],v3,nehalemep,core
GenuineIntel-6-2E,v3,nehalemex,core
GenuineIntel-6-2A,v19,sandybridge,core
GenuineIntel-6-(8F|CF),v1.11,sapphirerapids,core
GenuineIntel-6-(8F|CF),v1.12,sapphirerapids,core
GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v55,skylake,core
GenuineIntel-6-55-[01234],v1.29,skylakex,core
......
tools/perf/pmu-events/arch/x86/sapphirerapids/other.json
View file @ 54f5de6f
......@@ -331,10 +331,11 @@
"UMask": "0x7"
},
{
"BriefDescription": "XQ.FULL_CYCLES",
"BriefDescription": "Cycles the uncore cannot take further requests",
"CounterMask": "1",
"EventCode": "0x2d",
"EventName": "XQ.FULL_CYCLES",
"PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).",
"SampleAfterValue": "1000003",
"UMask": "0x1"
}
......
tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json
View file @ 54f5de6f
......@@ -44,6 +44,7 @@
},
{
"BriefDescription": "This event counts the cycles the integer divider is busy.",
"CounterMask": "1",
"EventCode": "0xb0",
"EventName": "ARITH.IDIV_ACTIVE",
"SampleAfterValue": "1000003",
......@@ -655,9 +656,10 @@
"UMask": "0x4"
},
{
"BriefDescription": "MISC2_RETIRED.LFENCE",
"BriefDescription": "LFENCE instructions retired",
"EventCode": "0xe0",
"EventName": "MISC2_RETIRED.LFENCE",
"PublicDescription": "number of LFENCE retired instructions",
"SampleAfterValue": "400009",
"UMask": "0x20"
},
......
tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cxl.json 0 → 100644
View file @ 54f5de6f
[
{
"BriefDescription": "Counts the number of lfclk ticks",
"EventCode": "0x01",
"EventName": "UNC_CXLCM_CLOCKTICKS",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Mem Rxx AGF 0",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_DATA",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Req AGF0",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_REQ0",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Rsp AGF",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_REQ1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Data AGF",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_RSP0",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Rsp AGF",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_RSP1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Req AGF 1",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.MEM_DATA",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Mem Data AGF",
"EventCode": "0x43",
"EventName": "UNC_CXLCM_RxC_AGF_INSERTS.MEM_REQ",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Flits with AK set",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.AK_HDR",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Flits with BE set",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.BE_HDR",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of control flits received",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.CTRL",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Headerless flits received",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.NO_HDR",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of protocol flits received",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.PROT",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Flits with SZ set",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.SZ_HDR",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of flits received",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.VALID",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of valid messages in the flit",
"EventCode": "0x4b",
"EventName": "UNC_CXLCM_RxC_FLITS.VALID_MSG",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of CRC errors detected",
"EventCode": "0x40",
"EventName": "UNC_CXLCM_RxC_MISC.CRC_ERRORS",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Init flits sent",
"EventCode": "0x40",
"EventName": "UNC_CXLCM_RxC_MISC.INIT",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of LLCRD flits sent",
"EventCode": "0x40",
"EventName": "UNC_CXLCM_RxC_MISC.LLCRD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Retry flits sent",
"EventCode": "0x40",
"EventName": "UNC_CXLCM_RxC_MISC.RETRY",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles the Packing Buffer is Full",
"EventCode": "0x52",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_DATA",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles the Packing Buffer is Full",
"EventCode": "0x52",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_REQ",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles the Packing Buffer is Full",
"EventCode": "0x52",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_RSP",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles the Packing Buffer is Full",
"EventCode": "0x52",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.MEM_DATA",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles the Packing Buffer is Full",
"EventCode": "0x52",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.MEM_REQ",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Data Packing buffer",
"EventCode": "0x41",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_DATA",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Req Packing buffer",
"EventCode": "0x41",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_REQ",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Rsp Packing buffer",
"EventCode": "0x41",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_RSP",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Mem Data Packing buffer",
"EventCode": "0x41",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Mem Rxx Packing buffer",
"EventCode": "0x41",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_REQ",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles of Not Empty for Cache Data Packing buffer",
"EventCode": "0x42",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_DATA",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles of Not Empty for Cache Req Packing buffer",
"EventCode": "0x42",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_REQ",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles of Not Empty for Cache Rsp Packing buffer",
"EventCode": "0x42",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_RSP",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles of Not Empty for Mem Data Packing buffer",
"EventCode": "0x42",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.MEM_DATA",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of cycles of Not Empty for Mem Rxx Packing buffer",
"EventCode": "0x42",
"EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.MEM_REQ",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Flits with AK set",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.AK_HDR",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Flits with BE set",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.BE_HDR",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of control flits packed",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.CTRL",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Headerless flits packed",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.NO_HDR",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of protocol flits packed",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.PROT",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of Flits with SZ set",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.SZ_HDR",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CXLCM"
},
{
"BriefDescription": "Count the number of flits packed",
"EventCode": "0x05",
"EventName": "UNC_CXLCM_TxC_FLITS.VALID",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Data Packing buffer",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_DATA",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Req Packing buffer",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_REQ0",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Rsp1 Packing buffer",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_REQ1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Rsp0 Packing buffer",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_RSP0",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Cache Req Packing buffer",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_RSP1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Mem Data Packing buffer",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.MEM_DATA",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLCM"
},
{
"BriefDescription": "Number of Allocation to Mem Rxx Packing buffer",
"EventCode": "0x02",
"EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.MEM_REQ",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLCM"
},
{
"BriefDescription": "Counts the number of uclk ticks",
"EventCode": "0x01",
"EventName": "UNC_CXLDP_CLOCKTICKS",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLDP"
},
{
"BriefDescription": "Number of Allocation to M2S Data AGF",
"EventCode": "0x02",
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_DATA",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CXLDP"
},
{
"BriefDescription": "Number of Allocation to M2S Req AGF",
"EventCode": "0x02",
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_REQ",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CXLDP"
},
{
"BriefDescription": "Number of Allocation to U2C Data AGF",
"EventCode": "0x02",
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_DATA",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CXLDP"
},
{
"BriefDescription": "Number of Allocation to U2C Req AGF",
"EventCode": "0x02",
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_REQ",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CXLDP"
},
{
"BriefDescription": "Number of Allocation to U2C Rsp AGF 0",
"EventCode": "0x02",
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_RSP0",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CXLDP"
},
{
"BriefDescription": "Number of Allocation to U2C Rsp AGF 1",
"EventCode": "0x02",
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_RSP1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CXLDP"
}
]
tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-interconnect.json 0 → 100644
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tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-io.json 0 → 100644
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tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-memory.json
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tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-power.json
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......@@ -7,6 +7,66 @@
"PublicDescription": "Number of PCU PCLK Clock cycles while the event is enabled",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES",
"EventCode": "0x60",
"EventName": "UNC_P_CORE_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_DEMOTIONS",
"EventCode": "0x30",
"EventName": "UNC_P_DEMOTIONS",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 0 Cycles",
"EventCode": "0x75",
"EventName": "UNC_P_FIVR_PS_PS0_CYCLES",
"PerPkg": "1",
"PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 1 Cycles",
"EventCode": "0x76",
"EventName": "UNC_P_FIVR_PS_PS1_CYCLES",
"PerPkg": "1",
"PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 2 Cycles",
"EventCode": "0x77",
"EventName": "UNC_P_FIVR_PS_PS2_CYCLES",
"PerPkg": "1",
"PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 3 Cycles",
"EventCode": "0x78",
"EventName": "UNC_P_FIVR_PS_PS3_CYCLES",
"PerPkg": "1",
"PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
"Unit": "PCU"
},
{
"BriefDescription": "AVX256 Frequency Clipping",
"EventCode": "0x49",
"EventName": "UNC_P_FREQ_CLIP_AVX256",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "AVX512 Frequency Clipping",
"EventCode": "0x4a",
"EventName": "UNC_P_FREQ_CLIP_AVX512",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
"EventCode": "0x04",
......@@ -23,6 +83,14 @@
"PublicDescription": "Power Strongest Upper Limit Cycles : Counts the number of cycles when power is the upper limit on frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
"EventCode": "0x73",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
"PerPkg": "1",
"PublicDescription": "IO P Limit Strongest Lower Limit Cycles : Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
"Unit": "PCU"
},
{
"BriefDescription": "Cycles spent changing Frequency",
"EventCode": "0x74",
......@@ -31,6 +99,22 @@
"PublicDescription": "Cycles spent changing Frequency : Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
"Unit": "PCU"
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
"EventCode": "0x2f",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"PerPkg": "1",
"PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C0",
"EventCode": "0x2a",
"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
"PerPkg": "1",
"PublicDescription": "Package C State Residency - C0 : Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C2E",
"EventCode": "0x2b",
......@@ -47,6 +131,13 @@
"PublicDescription": "Package C State Residency - C6 : Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES",
"EventCode": "0x06",
"EventName": "UNC_P_PMAX_THROTTLED_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C0",
"EventCode": "0x35",
......@@ -86,5 +177,21 @@
"PerPkg": "1",
"PublicDescription": "Internal Prochot : Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
"BriefDescription": "Total Core C State Transition Cycles",
"EventCode": "0x72",
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Total Core C State Transition Cycles : Number of cycles spent performing core C state transitions across all cores.",
"Unit": "PCU"
},
{
"BriefDescription": "VR Hot",
"EventCode": "0x42",
"EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",
"PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot. Does not cover DRAM VRs",
"Unit": "PCU"
}
]
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