Commit 562da8b4 authored by Thierry Reding's avatar Thierry Reding

arm64: tegra: Use valid PWM period for VDD_GPU on Tegra210

The PWM on Tegra210 can run at a maximum frequency of 48 MHz and cannot
reach the minimum period is 5334 ns. The currently configured period of
4880 ns is not within the valid range, so set it to 8000 ns. This value
was taken from the downstream DTS files and seems to work fine.
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 0cc6ba3c
......@@ -337,7 +337,7 @@ psci {
vdd_gpu: regulator@100 {
compatible = "pwm-regulator";
pwms = <&pwm 1 4880>;
pwms = <&pwm 1 8000>;
regulator-name = "VDD_GPU";
regulator-min-microvolt = <710000>;
regulator-max-microvolt = <1320000>;
......
......@@ -821,7 +821,7 @@ vdd_cpu: regulator@5 {
vdd_gpu: regulator@6 {
compatible = "pwm-regulator";
pwms = <&pwm 1 4880>;
pwms = <&pwm 1 8000>;
regulator-name = "VDD_GPU";
regulator-min-microvolt = <710000>;
......
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