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Commit 57d62c2d authored by David S. Miller's avatar David S. Miller
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Merge nuts.davemloft.net:/disk1/BK/network-2.6 

into nuts.davemloft.net:/disk1/BK/net-2.6
parents f9380ee9 edd2ffb9
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Documentation/powerpc/mpc52xx.txt
View file @ 57d62c2d
Linux 2.6.x on MPC52xx family
-----------------------------
For the latest info, go to http://www.246tNt.com/mpc52xx/state.txt
For the latest info, go to http://www.246tNt.com/mpc52xx/
To compile/use :
......@@ -37,12 +37,3 @@ Some remarks :
- Of course, I inspired myself from the 2.4 port. If you think I forgot to
mention you/your company in the copyright of some code, I'll correct it
ASAP.
- The codes wants the MBAR to be set at 0xf0000000 by the bootloader. It's
mapped 1:1 with the MMU. If for whatever reason, you want to change this,
beware that some code depends on the 0xf0000000 address and other depends
on the 1:1 mapping.
- Most of the code assumes that port multiplexing, frequency selection, ...
has already been done. IMHO this should be done as early as possible, in
the bootloader. If for whatever reason you can't do it there, do it in the
platform setup code (if U-Boot) or in the arch/ppc/boot/simple/... (if
DBug)
MAINTAINERS
View file @ 57d62c2d
......@@ -1301,6 +1301,15 @@ W: http://www.penguinppc.org/
L: linuxppc-dev@lists.linuxppc.org
S: Maintained
LINUX FOR POWERPC EMBEDDED MPC52XX
P: Sylvain Munaut
M: tnt@246tNt.com
W: http://www.246tNt.com/mpc52xx/
W: http://www.penguinppc.org/
L: linuxppc-dev@ozlabs.org
L: linuxppc-embedded@ozlabs.org
S: Maintained
LINUX FOR POWERPC EMBEDDED PPC4XX
P: Matt Porter
M: mporter@kernel.crashing.org
......
arch/arm/kernel/calls.S
View file @ 57d62c2d
/*
* linux/arch/arm/kernel/calls.S
*
* Copyright (C) 1995-2003 Russell King
* Copyright (C) 1995-2004 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......@@ -288,6 +288,13 @@ __syscall_start:
.long sys_pciconfig_iobase
.long sys_pciconfig_read
.long sys_pciconfig_write
.long sys_mq_open
/* 275 */ .long sys_mq_unlink
.long sys_mq_timedsend
.long sys_mq_timedreceive
.long sys_mq_notify
.long sys_mq_getsetattr
/* 280 */ .long sys_waitid
__syscall_end:
.rept NR_syscalls - (__syscall_end - __syscall_start) / 4
......
arch/arm/kernel/ecard.c
View file @ 57d62c2d
......@@ -224,7 +224,7 @@ static void ecard_do_request(struct ecard_request *req)
static pid_t ecard_pid;
static wait_queue_head_t ecard_wait;
static struct ecard_request *ecard_req;
static DECLARE_MUTEX(ecard_sem);
static DECLARE_COMPLETION(ecard_completion);
/*
......@@ -282,8 +282,6 @@ static int ecard_init_mm(void)
static int
ecard_task(void * unused)
{
struct task_struct *tsk = current;
daemonize("kecardd");
/*
......@@ -298,16 +296,11 @@ ecard_task(void * unused)
while (1) {
struct ecard_request *req;
do {
req = xchg(&ecard_req, NULL);
if (req == NULL) {
sigemptyset(&tsk->pending.signal);
interruptible_sleep_on(&ecard_wait);
}
} while (req == NULL);
wait_event_interruptible(ecard_wait, ecard_req != NULL);
ecard_do_request(req);
req = xchg(&ecard_req, NULL);
if (req != NULL)
ecard_do_request(req);
complete(&ecard_completion);
}
}
......@@ -330,6 +323,7 @@ ecard_call(struct ecard_request *req)
if (ecard_pid <= 0)
ecard_pid = kernel_thread(ecard_task, NULL, CLONE_KERNEL);
down(&ecard_sem);
ecard_req = req;
wake_up(&ecard_wait);
......@@ -337,6 +331,7 @@ ecard_call(struct ecard_request *req)
* Now wait for kecardd to run.
*/
wait_for_completion(&ecard_completion);
up(&ecard_sem);
}
/* ======================= Mid-level card control ===================== */
......
arch/arm/kernel/irq.c
View file @ 57d62c2d
......@@ -46,6 +46,7 @@
*/
#define MAX_IRQ_CNT 100000
static int noirqdebug;
static volatile unsigned long irq_err_count;
static spinlock_t irq_controller_lock = SPIN_LOCK_UNLOCKED;
static LIST_HEAD(irq_pending);
......@@ -235,7 +236,7 @@ report_bad_irq(unsigned int irq, struct pt_regs *regs, struct irqdesc *desc, int
static int count = 100;
struct irqaction *action;
if (!count)
if (!count || noirqdebug)
return;
count--;
......@@ -863,3 +864,11 @@ void __init init_IRQ(void)
init_arch_irq();
init_dma();
}
static int __init noirqdebug_setup(char *str)
{
noirqdebug = 1;
return 1;
}
__setup("noirqdebug", noirqdebug_setup);
arch/arm/kernel/signal.c
View file @ 57d62c2d
......@@ -409,6 +409,7 @@ static inline void __user *
get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, int framesize)
{
unsigned long sp = regs->ARM_sp;
void __user *frame;
#ifdef CONFIG_IWMMXT
if (test_thread_flag(TIF_USING_IWMMXT))
......@@ -424,7 +425,15 @@ get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, int framesize)
/*
* ATPCS B01 mandates 8-byte alignment
*/
return (void __user *)((sp - framesize) & ~7);
frame = (void __user *)((sp - framesize) & ~7);
/*
* Check that we can actually write to the signal frame.
*/
if (!access_ok(VERIFY_WRITE, frame, framesize))
frame = NULL;
return frame;
}
static int
......@@ -493,7 +502,7 @@ setup_frame(int usig, struct k_sigaction *ka, sigset_t *set, struct pt_regs *reg
struct sigframe __user *frame = get_sigframe(ka, regs, sizeof(*frame));
int err = 0;
if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame)))
if (!frame)
return 1;
err |= setup_sigcontext(&frame->sc, /*&frame->fpstate,*/ regs, set->sig[0]);
......@@ -522,7 +531,7 @@ setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info,
stack_t stack;
int err = 0;
if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame)))
if (!frame)
return 1;
__put_user_error(&frame->info, &frame->pinfo, err);
......
arch/arm/mach-imx/time.c
View file @ 57d62c2d
......@@ -25,7 +25,7 @@
#define TIMER_BASE IMX_TIM1_BASE
/*
* Returns number of ms since last clock interrupt. Note that interrupts
* Returns number of us since last clock interrupt. Note that interrupts
* will have been disabled by do_gettimeoffset()
*/
static unsigned long
......@@ -39,7 +39,7 @@ imx_gettimeoffset(void)
* an interrupt. We get around this by ensuring that the
* counter has not reloaded between our two reads.
*/
ticks = IMX_TCR(TIMER_BASE);
ticks = IMX_TCN(TIMER_BASE);
/*
* Interrupt pending? If so, we've reloaded once already.
......@@ -84,7 +84,7 @@ imx_init_time(void)
*/
IMX_TCTL(TIMER_BASE) = 0;
IMX_TPRER(TIMER_BASE) = 0;
IMX_TCMP(TIMER_BASE) = LATCH;
IMX_TCMP(TIMER_BASE) = LATCH - 1;
IMX_TCTL(TIMER_BASE) = TCTL_CLK_32 | TCTL_IRQEN | TCTL_TEN;
/*
......
arch/arm/mach-integrator/clock.c
View file @ 57d62c2d
......@@ -76,7 +76,10 @@ EXPORT_SYMBOL(clk_get_rate);
long clk_round_rate(struct clk *clk, unsigned long rate)
{
return rate;
struct icst525_vco vco;
vco = icst525_khz_to_vco(clk->params, rate / 1000);
return icst525_khz(clk->params, vco) * 1000;
}
EXPORT_SYMBOL(clk_round_rate);
......@@ -86,8 +89,8 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
if (clk->setvco) {
struct icst525_vco vco;
vco = icst525_khz_to_vco(clk->params, rate);
clk->rate = icst525_khz(clk->params, vco);
vco = icst525_khz_to_vco(clk->params, rate / 1000);
clk->rate = icst525_khz(clk->params, vco) * 1000;
printk("Clock %s: setting VCO reg params: S=%d R=%d V=%d\n",
clk->name, vco.s, vco.r, vco.v);
......
arch/arm/mach-iop3xx/iop331-pci.c
View file @ 57d62c2d
......@@ -208,12 +208,10 @@ void iop331_init(void)
DBG("\tATU: IOP331_IABAR2=0x%08x IOP331_IALR2=0x%08x IOP331_IATVR2=%08x\n", *IOP331_IABAR2, *IOP331_IALR2, *IOP331_IATVR2);
DBG("\tATU: IOP331_IABAR3=0x%08x IOP331_IALR3=0x%08x IOP331_IATVR3=%08x\n", *IOP331_IABAR3, *IOP331_IALR3, *IOP331_IATVR3);
#if 0
hook_fault_code(4, iop331_pci_abort, SIGBUS, "external abort on linefetch");
hook_fault_code(6, iop331_pci_abort, SIGBUS, "external abort on linefetch");
hook_fault_code(8, iop331_pci_abort, SIGBUS, "external abort on non-linefetch");
hook_fault_code(10, iop331_pci_abort, SIGBUS, "external abort on non-linefetch");
#endif
/* redboot changed, reset IABAR0 to something sane */
/* fixes master aborts in plugged in cards */
/* will clean up later and work nicely with redboot */
*IOP331_IABAR0 = 0x00000004;
hook_fault_code(16+6, iop331_pci_abort, SIGBUS, "imprecise external abort");
}
arch/arm/mach-s3c2410/Makefile
View file @ 57d62c2d
......@@ -21,8 +21,8 @@ obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o
# machine specific support
obj-$(CONFIG_ARCH_BAST) += mach-bast.o
obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o
obj-$(CONFIG_ARCH_H1940) += mach-h1940.o
obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o
obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o
obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o usb-simtec.o
arch/arm/mach-s3c2410/gpio.c
View file @ 57d62c2d
......@@ -24,6 +24,9 @@
* 14-Sep-2004 BJD Added getpin call
* 14-Sep-2004 BJD Fixed bug in setpin() call
* 30-Sep-2004 BJD Fixed cfgpin() mask bug
* 01-Oct-2004 BJD Added getcfg() to get pin configuration
* 01-Oct-2004 BJD Fixed mask bug in pullup() call
* 01-Oct-2004 BJD Added getoirq() to turn pin into irqno
*/
......@@ -62,6 +65,20 @@ void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
local_irq_restore(flags);
}
unsigned int s3c2410_gpio_getcfg(unsigned int pin)
{
unsigned long base = S3C2410_GPIO_BASE(pin);
unsigned long mask;
if (pin < S3C2410_GPIO_BANKB) {
mask = 1 << S3C2410_GPIO_OFFSET(pin);
} else {
mask = 3 << S3C2410_GPIO_OFFSET(pin)*2;
}
return __raw_readl(base) & mask;
}
void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
{
unsigned long base = S3C2410_GPIO_BASE(pin);
......@@ -75,7 +92,7 @@ void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
local_irq_save(flags);
up = __raw_readl(base + 0x08);
up &= 1 << offs;
up &= ~(1L << offs);
up |= to << offs;
__raw_writel(up, base + 0x08);
......@@ -121,3 +138,20 @@ unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
return misccr;
}
int s3c2410_gpio_getirq(unsigned int pin)
{
if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15_EINT23)
return -1; /* not valid interrupts */
if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7)
return -1; /* not valid pin */
if (pin < S3C2410_GPF4)
return (pin - S3C2410_GPF0) + IRQ_EINT0;
if (pin < S3C2410_GPG0)
return (pin - S3C2410_GPF4) + IRQ_EINT4;
return (pin - S3C2410_GPG0) + IRQ_EINT8;
}
arch/arm/mach-s3c2410/mach-bast.c
View file @ 57d62c2d
......@@ -10,6 +10,7 @@
* published by the Free Software Foundation.
*
* Modifications:
* 14-Sep-2004 BJD USB power control
* 20-Aug-2004 BJD Added s3c2410_board struct
* 18-Aug-2004 BJD Added platform devices from default set
* 16-May-2003 BJD Created initial version
......@@ -44,6 +45,7 @@
#include "s3c2410.h"
#include "devs.h"
#include "cpu.h"
#include "usb-simtec.h"
/* macros for virtual address mods for the io space entries */
#define VA_C5(item) ((item) + BAST_VAM_CS5)
......@@ -215,6 +217,7 @@ void __init bast_map_io(void)
s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
s3c2410_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
s3c2410_set_board(&bast_board);
usb_simtec_init();
}
void __init bast_init_irq(void)
......
arch/arm/mach-s3c2410/mach-vr1000.c
View file @ 57d62c2d
......@@ -11,6 +11,7 @@
* published by the Free Software Foundation.
*
* Modifications:
* 14-Sep-2004 BJD USB Power control
* 04-Sep-2004 BJD Added new uart init, and io init
* 21-Aug-2004 BJD Added struct s3c2410_board
* 06-Aug-2004 BJD Fixed call to time initialisation
......@@ -42,6 +43,7 @@
#include "s3c2410.h"
#include "devs.h"
#include "cpu.h"
#include "usb-simtec.h"
/* macros for virtual address mods for the io space entries */
#define VA_C5(item) ((item) + BAST_VAM_CS5)
......@@ -160,6 +162,7 @@ void __init vr1000_map_io(void)
s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
s3c2410_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
s3c2410_set_board(&vr1000_board);
usb_simtec_init();
}
void __init vr1000_init_irq(void)
......
arch/arm/mach-s3c2410/usb-simtec.c 0 → 100644
View file @ 57d62c2d
/* linux/arch/arm/mach-s3c2410/usb-simtec.c
*
* Copyright (c) 2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* http://www.simtec.co.uk/products/EB2410ITX/
*
* Simtec BAST and Thorcom VR1000 USB port support functions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Modifications:
* 14-Sep-2004 BJD Created
*/
#define DEBUG
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/device.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/arch/bast-map.h>
#include <asm/arch/bast-irq.h>
#include <asm/arch/usb-control.h>
#include <asm/arch/regs-gpio.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include "devs.h"
#include "usb-simtec.h"
/* control power and monitor over-current events on various Simtec
* designed boards.
*/
static void
usb_simtec_powercontrol(int port, int to)
{
pr_debug("usb_simtec_powercontrol(%d,%d)\n", port, to);
if (port == 1) {
s3c2410_gpio_setpin(S3C2410_GPB4, to ? 0:1);
pr_debug("GPBDAT now %08x\n", __raw_readl(S3C2410_GPBDAT));
}
}
static irqreturn_t
usb_simtec_ocirq(int irq, void *pw, struct pt_regs *regs)
{
struct s3c2410_hcd_info *info = (struct s3c2410_hcd_info *)pw;
if (s3c2410_gpio_getpin(S3C2410_GPG10) == 0) {
pr_debug("usb_simtec: over-current irq (oc detected)\n");
s3c2410_report_oc(info, 3);
} else {
pr_debug("usb_simtec: over-current irq (oc cleared)\n");
}
return IRQ_HANDLED;
}
static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on)
{
int ret;
if (on) {
pr_debug("claiming usb overccurent\n");
ret = request_irq(IRQ_USBOC, usb_simtec_ocirq, SA_INTERRUPT,
"usb-oc", info);
if (ret != 0) {
printk(KERN_ERR "failed to request usb oc irq\n");
}
set_irq_type(IRQ_USBOC, IRQT_BOTHEDGE);
} else {
free_irq(IRQ_USBOC, NULL);
}
}
static struct s3c2410_hcd_info usb_simtec_info = {
.port[0] = {
.flags = S3C_HCDFLG_USED
},
.port[1] = {
.flags = S3C_HCDFLG_USED
},
.power_control = usb_simtec_powercontrol,
.enable_oc = usb_simtec_enableoc,
};
int usb_simtec_init(void)
{
printk("USB Power Control, (c) 2004 Simtec Electronics\n");
s3c_device_usb.dev.platform_data = &usb_simtec_info;
s3c2410_gpio_cfgpin(S3C2410_GPB4, S3C2410_GPB4_OUTP);
s3c2410_gpio_setpin(S3C2410_GPB4, 1);
pr_debug("GPB: CON=%08x, DAT=%08x\n",
__raw_readl(S3C2410_GPBCON), __raw_readl(S3C2410_GPBDAT));
if (0) {
s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST,
S3C2410_MISCCR_USBDEV);
}
return 0;
}
arch/arm/mach-s3c2410/usb-simtec.h 0 → 100644
View file @ 57d62c2d
/* linux/arch/arm/mach-s3c2410/usb-simtec.c
*
* Copyright (c) 2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* http://www.simtec.co.uk/products/EB2410ITX/
*
* Simtec BAST and Thorcom VR1000 USB port support functions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Modifications:
* 20-Aug-2004 BJD Created
*/
extern int usb_simtec_init(void);
arch/arm/mach-versatile/clock.c
View file @ 57d62c2d
......@@ -87,8 +87,8 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
if (clk->setvco) {
struct icst525_vco vco;
vco = icst525_khz_to_vco(clk->params, rate);
clk->rate = icst525_khz(clk->params, vco);
vco = icst525_khz_to_vco(clk->params, rate / 1000);
clk->rate = icst525_khz(clk->params, vco) * 1000;
printk("Clock %s: setting VCO reg params: S=%d R=%d V=%d\n",
clk->name, vco.s, vco.r, vco.v);
......
arch/arm/mm/consistent.c
View file @ 57d62c2d
......@@ -138,7 +138,7 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, int gfp,
struct page *page;
struct vm_region *c;
unsigned long order;
u64 mask = 0x00ffffff, limit; /* ISA default */
u64 mask = ISA_DMA_THRESHOLD, limit;
if (!consistent_pte) {
printk(KERN_ERR "%s: not initialised\n", __func__);
......@@ -148,19 +148,34 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, int gfp,
if (dev) {
mask = dev->coherent_dma_mask;
/*
* Sanity check the DMA mask - it must be non-zero, and
* must be able to be satisfied by a DMA allocation.
*/
if (mask == 0) {
dev_warn(dev, "coherent DMA mask is unset\n");
return NULL;
goto no_page;
}
if ((~mask) & ISA_DMA_THRESHOLD) {
dev_warn(dev, "coherent DMA mask %#llx is smaller "
"than system GFP_DMA mask %#llx\n",
mask, (unsigned long long)ISA_DMA_THRESHOLD);
goto no_page;
}
}
/*
* Sanity check the allocation size.
*/
size = PAGE_ALIGN(size);
limit = (mask + 1) & ~mask;
if ((limit && size >= limit) || size >= (CONSISTENT_END - CONSISTENT_BASE)) {
printk(KERN_WARNING "coherent allocation too big (requested %#x mask %#Lx)\n",
size, mask);
*handle = ~0;
return NULL;
if ((limit && size >= limit) ||
size >= (CONSISTENT_END - CONSISTENT_BASE)) {
printk(KERN_WARNING "coherent allocation too big "
"(requested %#x mask %#llx)\n", size, mask);
goto no_page;
}
order = get_order(size);
......@@ -221,6 +236,7 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, int gfp,
if (page)
__free_pages(page, order);
no_page:
*handle = ~0;
return NULL;
}
......
arch/arm/tools/mach-types
View file @ 57d62c2d
......@@ -6,7 +6,7 @@
# To add an entry into this database, please see Documentation/arm/README,
# or contact rmk@arm.linux.org.uk
#
# Last update: Mon Aug 16 19:22:37 2004
# Last update: Thu Sep 30 15:23:21 2004
#
# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
#
......@@ -519,7 +519,7 @@ scb9328 MACH_SCB9328 SCB9328 508
omap_h3 MACH_OMAP_H3 OMAP_H3 509
omap_h4 MACH_OMAP_H4 OMAP_H4 510
n10 MACH_N10 N10 511
montajade MACH_MONTAJADE MONTAJADE 512
montejade MACH_MONTAJADE MONTAJADE 512
sg560 MACH_SG560 SG560 513
dp1000 MACH_DP1000 DP1000 514
omap_osk MACH_OMAP_OSK OMAP_OSK 515
......@@ -582,7 +582,36 @@ cx2351x MACH_CX2351X CX2351X 571
computime MACH_COMPUTIME COMPUTIME 572
izarus MACH_IZARUS IZARUS 573
pxa_rts MACH_RTS RTS 574
netgate5100 MACH_NETGATE5100 NETGATE5100 575
se5100 MACH_SE5100 SE5100 575
s3c2510 MACH_S3C2510 S3C2510 576
csb437tl MACH_CSB437TL CSB437TL 577
slauson MACH_SLAUSON SLAUSON 578
pearlriver MACH_PEARLRIVER PEARLRIVER 579
tdc_p210 MACH_TDC_P210 TDC_P210 580
sg580 MACH_SG580 SG580 581
wrsbcarm7 MACH_WRSBCARM7 WRSBCARM7 582
ipd MACH_IPD IPD 583
pxa_dnp2110 MACH_PXA_DNP2110 PXA_DNP2110 584
xaeniax MACH_XAENIAX XAENIAX 585
somn4250 MACH_SOMN4250 SOMN4250 586
pleb2 MACH_PLEB2 PLEB2 587
cwl MACH_CWL CWL 588
gd MACH_GD GD 589
chaffee MACH_CHAFFEE CHAFFEE 590
rms101 MACH_RMS101 RMS101 591
rx3715 MACH_RX3715 RX3715 592
swift MACH_SWIFT SWIFT 593
roverp7 MACH_ROVERP7 ROVERP7 594
pr818s MACH_PR818S PR818S 595
trxpro MACH_TRXPRO TRXPRO 596
nslu2 MACH_NSLU2 NSLU2 597
e400 MACH_E400 E400 598
trab MACH_TRAB TRAB 599
cmc_pu2 MACH_CMC_PU2 CMC_PU2 600
fulcrum MACH_FULCRUM FULCRUM 601
netgate42x MACH_NETGATE42X NETGATE42X 602
str710 MACH_STR710 STR710 603
ixdpg425 MACH_IXDPG425 IXDPG425 604
tomtomgo MACH_TOMTOMGO TOMTOMGO 605
versatile_ab MACH_VERSATILE_AB VERSATILE_AB 606
edb9307 MACH_EDB9307 EDB9307 607
arch/ppc/boot/simple/misc.c
View file @ 57d62c2d
......@@ -48,7 +48,9 @@
* Val Henson has requested that Gemini doesn't wait for the
* user to edit the cmdline or not.
*/
#if (defined(CONFIG_SERIAL_8250_CONSOLE) || defined(CONFIG_VGA_CONSOLE)) \
#if (defined(CONFIG_SERIAL_8250_CONSOLE) \
|| defined(CONFIG_VGA_CONSOLE) \
|| defined(CONFIG_SERIAL_MPC52xx_CONSOLE)) \
&& !defined(CONFIG_GEMINI)
#define INTERACTIVE_CONSOLE 1
#endif
......
arch/ppc/kernel/cputable.c
View file @ 57d62c2d
......@@ -63,6 +63,17 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe
#define CPU_FTR_COMMON 0
#endif
/* The powersave features NAP & DOZE seems to confuse BDI when
debugging. So if a BDI is used, disable theses
*/
#ifndef CONFIG_BDI_SWITCH
#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
#else
#define CPU_FTR_MAYBE_CAN_DOZE 0
#define CPU_FTR_MAYBE_CAN_NAP 0
#endif
struct cpu_spec cpu_specs[] = {
#if CLASSIC_PPC
{ /* 601 */
......@@ -76,8 +87,8 @@ struct cpu_spec cpu_specs[] = {
{ /* 603 */
0xffff0000, 0x00030000, "603",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_CAN_NAP,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP,
COMMON_PPC,
32, 32,
__setup_cpu_603
......@@ -85,8 +96,8 @@ struct cpu_spec cpu_specs[] = {
{ /* 603e */
0xffff0000, 0x00060000, "603e",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_CAN_NAP,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP,
COMMON_PPC,
32, 32,
__setup_cpu_603
......@@ -94,8 +105,8 @@ struct cpu_spec cpu_specs[] = {
{ /* 603ev */
0xffff0000, 0x00070000, "603ev",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_CAN_NAP,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP,
COMMON_PPC,
32, 32,
__setup_cpu_603
......@@ -139,8 +150,8 @@ struct cpu_spec cpu_specs[] = {
{ /* 740/750 (0x4202, don't support TAU ?) */
0xffffffff, 0x00084202, "740/750",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
COMMON_PPC,
32, 32,
__setup_cpu_750
......@@ -148,8 +159,8 @@ struct cpu_spec cpu_specs[] = {
{ /* 745/755 */
0xfffff000, 0x00083000, "745/755",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
COMMON_PPC,
32, 32,
__setup_cpu_750
......@@ -157,8 +168,8 @@ struct cpu_spec cpu_specs[] = {
{ /* 750CX (80100 and 8010x?) */
0xfffffff0, 0x00080100, "750CX",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
COMMON_PPC,
32, 32,
__setup_cpu_750cx
......@@ -166,8 +177,8 @@ struct cpu_spec cpu_specs[] = {
{ /* 750CX (82201 and 82202) */
0xfffffff0, 0x00082200, "750CX",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
COMMON_PPC,
32, 32,
__setup_cpu_750cx
......@@ -175,8 +186,8 @@ struct cpu_spec cpu_specs[] = {
{ /* 750CXe (82214) */
0xfffffff0, 0x00082210, "750CXe",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
COMMON_PPC,
32, 32,
__setup_cpu_750cx
......@@ -184,8 +195,8 @@ struct cpu_spec cpu_specs[] = {
{ /* 750FX rev 1.x */
0xffffff00, 0x70000100, "750FX",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
COMMON_PPC,
32, 32,
......@@ -194,8 +205,8 @@ struct cpu_spec cpu_specs[] = {
{ /* 750FX rev 2.0 must disable HID0[DPM] */
0xffffffff, 0x70000200, "750FX",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_NO_DPM,
COMMON_PPC,
32, 32,
......@@ -204,8 +215,8 @@ struct cpu_spec cpu_specs[] = {
{ /* 750FX (All revs except 2.0) */
0xffff0000, 0x70000000, "750FX",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
COMMON_PPC,
32, 32,
......@@ -213,8 +224,8 @@ struct cpu_spec cpu_specs[] = {
},
{ /* 750GX */
0xffff0000, 0x70020000, "750GX",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
COMMON_PPC,
32, 32,
......@@ -223,8 +234,8 @@ struct cpu_spec cpu_specs[] = {
{ /* 740/750 (L2CR bit need fixup for 740) */
0xffff0000, 0x00080000, "740/750",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
COMMON_PPC,
32, 32,
__setup_cpu_750
......@@ -232,9 +243,9 @@ struct cpu_spec cpu_specs[] = {
{ /* 7400 rev 1.1 ? (no TAU) */
0xffffffff, 0x000c1101, "7400 (1.1)",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
CPU_FTR_CAN_NAP,
CPU_FTR_MAYBE_CAN_NAP,
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
32, 32,
__setup_cpu_7400
......@@ -242,9 +253,9 @@ struct cpu_spec cpu_specs[] = {
{ /* 7400 */
0xffff0000, 0x000c0000, "7400",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
CPU_FTR_CAN_NAP,
CPU_FTR_MAYBE_CAN_NAP,
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
32, 32,
__setup_cpu_7400
......@@ -252,9 +263,9 @@ struct cpu_spec cpu_specs[] = {
{ /* 7410 */
0xffff0000, 0x800c0000, "7410",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
CPU_FTR_CAN_NAP,
CPU_FTR_MAYBE_CAN_NAP,
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
32, 32,
__setup_cpu_7410
......@@ -272,7 +283,7 @@ struct cpu_spec cpu_specs[] = {
{ /* 7450 2.1 */
0xffffffff, 0x80000201, "7450",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT,
......@@ -283,7 +294,7 @@ struct cpu_spec cpu_specs[] = {
{ /* 7450 2.3 and newer */
0xffff0000, 0x80000000, "7450",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
CPU_FTR_NEED_COHERENT,
......@@ -305,7 +316,7 @@ struct cpu_spec cpu_specs[] = {
{ /* 7455 rev 2.0 */
0xffffffff, 0x80010200, "7455",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
......@@ -316,7 +327,7 @@ struct cpu_spec cpu_specs[] = {
{ /* 7455 others */
0xffff0000, 0x80010000, "7455",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
......@@ -327,7 +338,7 @@ struct cpu_spec cpu_specs[] = {
{ /* 7447/7457 Rev 1.0 */
0xffffffff, 0x80020100, "7447/7457",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
......@@ -338,7 +349,7 @@ struct cpu_spec cpu_specs[] = {
{ /* 7447/7457 Rev 1.1 */
0xffffffff, 0x80020101, "7447/7457",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
......@@ -349,7 +360,7 @@ struct cpu_spec cpu_specs[] = {
{ /* 7447/7457 Rev 1.2 and later */
0xffff0000, 0x80020000, "7447/7457",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
......@@ -360,7 +371,7 @@ struct cpu_spec cpu_specs[] = {
{ /* 7447A */
0xffff0000, 0x80030000, "7447A",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
......@@ -371,15 +382,15 @@ struct cpu_spec cpu_specs[] = {
{ /* 82xx (8240, 8245, 8260 are all 603e cores) */
0x7fff0000, 0x00810000, "82xx",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
COMMON_PPC,
32, 32,
__setup_cpu_603
},
{ /* All G2_LE (603e core, plus some) have the same pvr */
0x7fff0000, 0x00820000, "G2_LE",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
COMMON_PPC,
32, 32,
__setup_cpu_603
......@@ -440,7 +451,7 @@ struct cpu_spec cpu_specs[] = {
0xffff0000, 0x00390000, "PPC970",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP,
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP,
128, 128,
__setup_cpu_ppc970
......@@ -449,7 +460,7 @@ struct cpu_spec cpu_specs[] = {
0xffff0000, 0x003c0000, "PPC970FX",
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP,
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP,
128, 128,
__setup_cpu_ppc970
......@@ -458,7 +469,8 @@ struct cpu_spec cpu_specs[] = {
#ifdef CONFIG_8xx
{ /* 8xx */
0xffff0000, 0x00500000, "8xx",
/* CPU_FTR_CAN_DOZE is possible, if the 8xx code is there.... */
/* CPU_FTR_MAYBE_CAN_DOZE is possible,
* if the 8xx code is there.... */
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
16, 16,
......@@ -599,7 +611,7 @@ struct cpu_spec cpu_specs[] = {
#ifdef CONFIG_E500
{ /* e500 */
0xffff0000, 0x80200000, "e500",
/* xxx - galak: add CPU_FTR_CAN_DOZE */
/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
32, 32,
......
arch/ppc/platforms/lite5200.c
View file @ 57d62c2d
......@@ -36,6 +36,8 @@
#include <asm/mpc52xx.h>
extern int powersave_nap;
/* Board data given by U-Boot */
bd_t __res;
EXPORT_SYMBOL(__res); /* For modules */
......@@ -64,25 +66,55 @@ struct ocp_def board_ocp[] = {
.vendor = OCP_VENDOR_INVALID
}
};
/* ======================================================================== */
/* Platform specific code */
/* ======================================================================== */
static int
icecube_show_cpuinfo(struct seq_file *m)
lite5200_show_cpuinfo(struct seq_file *m)
{
seq_printf(m, "machine\t\t: Freescale LITE5200\n");
return 0;
}
static void __init
icecube_setup_arch(void)
lite5200_setup_cpu(void)
{
struct mpc52xx_intr *intr;
u32 intr_ctrl;
/* Map zones */
intr = (struct mpc52xx_intr *)
ioremap(MPC52xx_INTR,sizeof(struct mpc52xx_intr));
if (!intr) {
printk("lite5200.c: Error while mapping INTR during lite5200_setup_cpu\n");
goto unmap_regs;
}
/* IRQ[0-3] setup : IRQ0 - Level Active Low */
/* IRQ[1-3] - Level Active High */
intr_ctrl = in_be32(&intr->ctrl);
intr_ctrl &= ~0x00ff0000;
intr_ctrl |= 0x00c00000;
out_be32(&intr->ctrl, intr_ctrl);
/* Unmap reg zone */
unmap_regs:
if (intr) iounmap(intr);
}
static void __init
lite5200_setup_arch(void)
{
/* Add board OCP definitions */
mpc52xx_add_board_devices(board_ocp);
/* CPU & Port mux setup */
lite5200_setup_cpu();
}
void __init
......@@ -110,7 +142,7 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
initrd_end = r5 + KERNELBASE;
}
#endif
/* Load the command line */
if (r6) {
*(char *)(r7+KERNELBASE) = 0;
......@@ -120,14 +152,17 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
/* BAT setup */
mpc52xx_set_bat();
/* No ISA bus AFAIK */
isa_io_base = 0;
isa_mem_base = 0;
/* Powersave */
powersave_nap = 1; /* We allow this platform to NAP */
/* Setup the ppc_md struct */
ppc_md.setup_arch = icecube_setup_arch;
ppc_md.show_cpuinfo = icecube_show_cpuinfo;
ppc_md.setup_arch = lite5200_setup_arch;
ppc_md.show_cpuinfo = lite5200_show_cpuinfo;
ppc_md.show_percpuinfo = NULL;
ppc_md.init_IRQ = mpc52xx_init_irq;
ppc_md.get_irq = mpc52xx_get_irq;
......@@ -138,12 +173,12 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
ppc_md.restart = mpc52xx_restart;
ppc_md.power_off = mpc52xx_power_off;
ppc_md.halt = mpc52xx_halt;
/* No time keeper on the IceCube */
/* No time keeper on the LITE5200 */
ppc_md.time_init = NULL;
ppc_md.get_rtc_time = NULL;
ppc_md.set_rtc_time = NULL;
ppc_md.calibrate_decr = mpc52xx_calibrate_decr;
#ifdef CONFIG_SERIAL_TEXT_DEBUG
ppc_md.progress = mpc52xx_progress;
......
arch/ppc/platforms/mpc5200.c
View file @ 57d62c2d
......@@ -16,6 +16,12 @@
#include <asm/ocp.h>
#include <asm/mpc52xx.h>
struct ocp_fs_i2c_data mpc5200_i2c_def = {
.flags = FS_I2C_CLOCK_5200,
};
/* Here is the core_ocp struct.
* With all the devices common to all board. Even if port multiplexing is
* not setup for them (if the user don't want them, just don't select the
......@@ -23,6 +29,24 @@
* board specific file.
*/
struct ocp_def core_ocp[] = {
{
.vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_IIC,
.index = 0,
.paddr = MPC52xx_I2C1,
.irq = OCP_IRQ_NA, /* MPC52xx_IRQ_I2C1 - Buggy */
.pm = OCP_CPM_NA,
.additions = &mpc5200_i2c_def,
},
{
.vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_IIC,
.index = 1,
.paddr = MPC52xx_I2C2,
.irq = OCP_IRQ_NA, /* MPC52xx_IRQ_I2C2 - Buggy */
.pm = OCP_CPM_NA,
.additions = &mpc5200_i2c_def,
},
{ /* Terminating entry */
.vendor = OCP_VENDOR_INVALID
}
......
arch/ppc/syslib/mpc52xx_pic.c
View file @ 57d62c2d
......@@ -114,7 +114,7 @@ mpc52xx_ic_ack(unsigned int irq)
/*
* Only some irqs are reset here, others in interrupting hardware.
*/
switch (irq) {
case MPC52xx_IRQ0:
val = in_be32(&intr->ctrl);
......@@ -180,13 +180,14 @@ void __init
mpc52xx_init_irq(void)
{
int i;
u32 intr_ctrl;
/* Remap the necessary zones */
intr = (struct mpc52xx_intr *)
ioremap(MPC52xx_INTR, sizeof(struct mpc52xx_intr));
sdma = (struct mpc52xx_sdma *)
ioremap(MPC52xx_SDMA, sizeof(struct mpc52xx_sdma));
if ((intr==NULL) || (sdma==NULL))
panic("Can't ioremap PIC/SDMA register for init_irq !");
......@@ -195,12 +196,13 @@ mpc52xx_init_irq(void)
out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
out_be32(&intr->ctrl,
0x0f000000 | /* clear IRQ 0-3 */
0x00c00000 | /* IRQ0: level-sensitive, active low */
intr_ctrl = in_be32(&intr->ctrl);
intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
0x00001000 | /* MEE master external enable */
0x00000000 | /* 0 means disable IRQ 0-3 */
0x00000001); /* CEb route critical normally */
0x00000001; /* CEb route critical normally */
out_be32(&intr->ctrl, intr_ctrl);
/* Zero a bunch of the priority settings. */
out_be32(&intr->per_pri1, 0);
......@@ -214,6 +216,14 @@ mpc52xx_init_irq(void)
irq_desc[i].handler = &mpc52xx_ic;
irq_desc[i].status = IRQ_LEVEL;
}
#define IRQn_MODE(intr_ctrl,irq) (((intr_ctrl) >> (22-(i<<1))) & 0x03)
for (i=0 ; i<4 ; i++) {
int mode;
mode = IRQn_MODE(intr_ctrl,i);
if ((mode == 0x1) || (mode == 0x2))
irq_desc[i?MPC52xx_IRQ1+i-1:MPC52xx_IRQ0].status = 0;
}
}
int
......
arch/ppc/syslib/mpc52xx_setup.c
View file @ 57d62c2d
/*
* arch/ppc/syslib/mpc52xx_common.c
* arch/ppc/syslib/mpc52xx_setup.c
*
* Common code for the boards based on Freescale MPC52xx embedded CPU.
*
......@@ -23,6 +23,7 @@
#include <asm/mpc52xx.h>
#include <asm/mpc52xx_psc.h>
#include <asm/ocp.h>
#include <asm/pgtable.h>
#include <asm/ppcboot.h>
extern bd_t __res;
......@@ -38,9 +39,9 @@ void
mpc52xx_restart(char *cmd)
{
struct mpc52xx_gpt* gpt0 = (struct mpc52xx_gpt*) MPC52xx_GPTx(0);
local_irq_disable();
/* Turn on the watchdog and wait for it to expire. It effectively
does a reset */
if (gpt0 != NULL) {
......@@ -99,24 +100,28 @@ mpc52xx_map_io(void)
#error "mpc52xx PSC for console not selected"
#endif
static void
mpc52xx_psc_putc(struct mpc52xx_psc * psc, unsigned char c)
{
while (!(in_be16(&psc->mpc52xx_psc_status) &
MPC52xx_PSC_SR_TXRDY));
out_8(&psc->mpc52xx_psc_buffer_8, c);
}
void
mpc52xx_progress(char *s, unsigned short hex)
{
struct mpc52xx_psc *psc = (struct mpc52xx_psc *)MPC52xx_CONSOLE;
char c;
/* Don't we need to disable serial interrupts ? */
while ((c = *s++) != 0) {
if (c == '\n') {
while (!(in_be16(&psc->mpc52xx_psc_status) &
MPC52xx_PSC_SR_TXRDY)) ;
out_8(&psc->mpc52xx_psc_buffer_8, '\r');
}
while (!(in_be16(&psc->mpc52xx_psc_status) &
MPC52xx_PSC_SR_TXRDY)) ;
out_8(&psc->mpc52xx_psc_buffer_8, c);
if (c == '\n')
mpc52xx_psc_putc(psc, '\r');
mpc52xx_psc_putc(psc, c);
}
mpc52xx_psc_putc(psc, '\r');
mpc52xx_psc_putc(psc, '\n');
}
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
......@@ -137,7 +142,7 @@ mpc52xx_find_end_of_memory(void)
/* Temp BAT2 mapping active when this is called ! */
mmap_ctl = (struct mpc52xx_mmap_ctl*) MPC52xx_MMAP_CTL;
sdram_config_0 = in_be32(&mmap_ctl->sdram0);
sdram_config_1 = in_be32(&mmap_ctl->sdram1);
......@@ -147,10 +152,8 @@ mpc52xx_find_end_of_memory(void)
if (((sdram_config_1 & 0x1f) >= 0x13) &&
((sdram_config_1 & 0xfff00000) == ramsize))
ramsize += 1 << ((sdram_config_1 & 0xf) + 17);
iounmap(mmap_ctl);
}
return ramsize;
}
......@@ -167,7 +170,7 @@ mpc52xx_calibrate_decr(void)
/* Get RTC & Clock manager modules */
struct mpc52xx_rtc *rtc;
struct mpc52xx_cdm *cdm;
rtc = (struct mpc52xx_rtc*)
ioremap(MPC52xx_RTC, sizeof(struct mpc52xx_rtc));
cdm = (struct mpc52xx_cdm*)
......@@ -206,7 +209,7 @@ mpc52xx_calibrate_decr(void)
__res.bi_intfreq = cpufreq;
__res.bi_ipbfreq = ipbfreq;
__res.bi_pcifreq = pcifreq;
/* Release mapping */
iounmap((void*)rtc);
iounmap((void*)cdm);
......
drivers/s390/char/sclp_tty.c
View file @ 57d62c2d
......@@ -277,7 +277,7 @@ sclp_ttybuf_callback(struct sclp_buffer *buffer, int rc)
wake_up(&sclp_tty_waitq);
/* check if the tty needs a wake up call */
if (sclp_tty != NULL) {
tty_wakeup(tty);
tty_wakeup(sclp_tty);
}
}
......
drivers/s390/char/sclp_vt220.c
View file @ 57d62c2d
......@@ -139,7 +139,7 @@ sclp_vt220_process_queue(struct sclp_vt220_request *request)
wake_up(&sclp_vt220_waitq);
/* Check if the tty needs a wake up call */
if (sclp_vt220_tty != NULL) {
tty_wakeup(tty);
tty_wakeup(sclp_vt220_tty);
}
}
......
drivers/video/amba-clcd.c
View file @ 57d62c2d
......@@ -207,7 +207,7 @@ static int clcdfb_set_par(struct fb_info *info)
clcdfb_set_start(fb);
clk_set_rate(fb->clk, 1000000000 / regs.pixclock);
clk_set_rate(fb->clk, (1000000000 / regs.pixclock) * 1000);
fb->clcd_cntl = regs.cntl;
......
include/asm-arm/arch-s3c2410/hardware.h
View file @ 57d62c2d
......@@ -15,6 +15,7 @@
* 03-Sep-2003 BJD Linux v2.6 support
* 12-Mar-2004 BJD Fixed include protection, fixed type of clock vars
* 14-Sep-2004 BJD Added misccr and getpin to gpio
* 01-Oct-2004 BJD Added the new gpio functions
*/
#ifndef __ASM_ARCH_HARDWARE_H
......@@ -45,6 +46,20 @@ extern unsigned long s3c2410_fclk;
extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
/* s3c2410_gpio_getirq
*
* turn the given pin number into the corresponding IRQ number
*
* returns:
* < 0 = no interrupt for this pin
* >=0 = interrupt number for the pin
*/
extern int s3c2410_gpio_getirq(unsigned int pin);
/* s3c2410_gpio_pullup
*
* configure the pull-up control on the given pin
......
include/asm-arm/arch-s3c2410/regs-gpio.h
View file @ 57d62c2d
......@@ -623,25 +623,25 @@
#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
#define S3C2410_GPG12_INP (0x00 << 24)
#define S3C2410_GPG12_OUTP (0x01 << 24)
#define S3C2410_GPG12_EINT18 (0x02 << 24)
#define S3C2410_GPG12_EINT20 (0x02 << 24)
#define S3C2410_GPG12_XMON (0x03 << 24)
#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
#define S3C2410_GPG13_INP (0x00 << 26)
#define S3C2410_GPG13_OUTP (0x01 << 26)
#define S3C2410_GPG13_EINT18 (0x02 << 26)
#define S3C2410_GPG13_EINT21 (0x02 << 26)
#define S3C2410_GPG13_nXPON (0x03 << 26)
#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
#define S3C2410_GPG14_INP (0x00 << 28)
#define S3C2410_GPG14_OUTP (0x01 << 28)
#define S3C2410_GPG14_EINT18 (0x02 << 28)
#define S3C2410_GPG14_EINT22 (0x02 << 28)
#define S3C2410_GPG14_YMON (0x03 << 28)
#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
#define S3C2410_GPG15_INP (0x00 << 30)
#define S3C2410_GPG15_OUTP (0x01 << 30)
#define S3C2410_GPG15_EINT18 (0x02 << 30)
#define S3C2410_GPG15_EINT23 (0x02 << 30)
#define S3C2410_GPG15_nYPON (0x03 << 30)
......@@ -751,6 +751,11 @@
#define S3C2410_MISCCR_nRSTCON (1<<16)
#define S3C2410_MISCCR_nEN_SCLK0 (1<<17)
#define S3C2410_MISCCR_nEN_SCLK1 (1<<18)
#define S3C2410_MISCCR_nEN_SCLKE (1<<19)
#define S3C2410_MISCCR_SDSLEEP (7<<17)
/* external interrupt control... */
/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
* S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
......
include/asm-arm/arch-s3c2410/regs-iic.h 0 → 100644
View file @ 57d62c2d
/* linux/include/asm-arm/arch-s3c2410/regs-iic.h
*
* Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2410 I2C Controller
*
* Changelog:
* 03-Oct-2004 BJD Initial include for Linux
*/
#ifndef __ASM_ARCH_IIC_H
#define __ASM_ARCH_IIC_H __FILE__
/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
#define S3C2410_IICREG(x) (x)
#define S3C2410_IICCON S3C2410_IICREG(0x00)
#define S3C2410_IICSTAT S3C2410_IICREG(0x04)
#define S3C2410_IICADD S3C2410_IICREG(0x08)
#define S3C2410_IICDS S3C2410_IICREG(0x0C)
#define S3C2410_IICCON_ACKEN (1<<7)
#define S3C2410_IICCON_TXDIV_16 (0<<6)
#define S3C2410_IICCON_TXDIV_512 (1<<6)
#define S3C2410_IICCON_IRQEN (1<<5)
#define S3C2410_IICCON_IRQPEND (1<<4)
#define S3C2410_IICCON_SCALE(x) ((x)&15)
#define S3C2410_IICCON_SCALEMASK (0xf)
#define S3C2410_IICSTAT_MASTER_RX (2<<6)
#define S3C2410_IICSTAT_MASTER_TX (3<<6)
#define S3C2410_IICSTAT_SLAVE_RX (0<<6)
#define S3C2410_IICSTAT_SLAVE_TX (1<<6)
#define S3C2410_IICSTAT_MODEMASK (3<<6)
#define S3C2410_IICSTAT_START (1<<5)
#define S3C2410_IICSTAT_BUSBUSY (1<<5)
#define S3C2410_IICSTAT_TXRXEN (1<<4)
#define S3C2410_IICSTAT_ARBITR (1<<3)
#define S3C2410_IICSTAT_ASSLAVE (1<<2)
#define S3C2410_IICSTAT_ADDR0 (1<<1)
#define S3C2410_IICSTAT_LASTBIT (1<<0)
#endif /* __ASM_ARCH_IIC_H */
include/asm-arm/arch-s3c2410/regs-mem.h 0 → 100644
View file @ 57d62c2d
/* linux/include/asm-arm/arch-s3c2410/regs-mem.h
*
* Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2410 Memory Control register definitions
*
* Changelog:
* 29-Sep-2004 BJD Initial include for Linux
*
*/
#ifndef __ASM_ARM_MEMREGS_H
#define __ASM_ARM_MEMREGS_H "$Id: regs.h,v 1.8 2003/05/01 15:55:41 ben Exp $"
#ifndef S3C2410_MEMREG
#define S3C2410_MEMREG(x) (S3C2410_VA_MEMCTRL + (x))
#endif
/* bus width, and wait state control */
#define S3C2410_BWSCON S3C2410_MEMREG(0x0000)
/* bank zero config - note, pinstrapped from OM pins! */
#define S3C2410_BWSCON_DW0_16 (1<<1)
#define S3C2410_BWSCON_DW0_32 (2<<1)
/* bank one configs */
#define S3C2410_BWSCON_DW1_8 (0<<4)
#define S3C2410_BWSCON_DW1_16 (1<<4)
#define S3C2410_BWSCON_DW1_32 (2<<4)
#define S3C2410_BWSCON_WS1 (1<<6)
#define S3C2410_BWSCON_ST1 (1<<7)
/* bank 2 configurations */
#define S3C2410_BWSCON_DW2_8 (0<<8)
#define S3C2410_BWSCON_DW2_16 (1<<8)
#define S3C2410_BWSCON_DW2_32 (2<<8)
#define S3C2410_BWSCON_WS2 (1<<10)
#define S3C2410_BWSCON_ST2 (1<<11)
/* bank 3 configurations */
#define S3C2410_BWSCON_DW3_8 (0<<12)
#define S3C2410_BWSCON_DW3_16 (1<<12)
#define S3C2410_BWSCON_DW3_32 (2<<12)
#define S3C2410_BWSCON_WS3 (1<<14)
#define S3C2410_BWSCON_ST3 (1<<15)
/* bank 4 configurations */
#define S3C2410_BWSCON_DW4_8 (0<<16)
#define S3C2410_BWSCON_DW4_16 (1<<16)
#define S3C2410_BWSCON_DW4_32 (2<<16)
#define S3C2410_BWSCON_WS4 (1<<18)
#define S3C2410_BWSCON_ST4 (1<<19)
/* bank 5 configurations */
#define S3C2410_BWSCON_DW5_8 (0<<20)
#define S3C2410_BWSCON_DW5_16 (1<<20)
#define S3C2410_BWSCON_DW5_32 (2<<20)
#define S3C2410_BWSCON_WS5 (1<<22)
#define S3C2410_BWSCON_ST5 (1<<23)
/* bank 6 configurations */
#define S3C2410_BWSCON_DW6_8 (0<<24)
#define S3C2410_BWSCON_DW6_16 (1<<24)
#define S3C2410_BWSCON_DW6_32 (2<<24)
#define S3C2410_BWSCON_WS6 (1<<26)
#define S3C2410_BWSCON_ST6 (1<<27)
/* bank 7 configurations */
#define S3C2410_BWSCON_DW7_8 (0<<28)
#define S3C2410_BWSCON_DW7_16 (1<<28)
#define S3C2410_BWSCON_DW7_32 (2<<28)
#define S3C2410_BWSCON_WS7 (1<<30)
#define S3C2410_BWSCON_ST7 (1<<31)
/* memory set (rom, ram) */
#define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004)
#define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008)
#define S3C2410_BANKCON2 S3C2410_MEMREG(0x000C)
#define S3C2410_BANKCON3 S3C2410_MEMREG(0x0010)
#define S3C2410_BANKCON4 S3C2410_MEMREG(0x0014)
#define S3C2410_BANKCON5 S3C2410_MEMREG(0x0018)
#define S3C2410_BANKCON6 S3C2410_MEMREG(0x001C)
#define S3C2410_BANKCON7 S3C2410_MEMREG(0x0020)
/* bank configuration registers */
#define S3C2410_BANKCON_PMCnorm (0x00)
#define S3C2410_BANKCON_PMC4 (0x01)
#define S3C2410_BANKCON_PMC8 (0x02)
#define S3C2410_BANKCON_PMC16 (0x03)
/* bank configurations for banks 0..7, note banks
* 6 and 7 have differnt configurations depending on
* the memory type bits */
#define S3C2410_BANKCON_Tacp2 (0x0 << 2)
#define S3C2410_BANKCON_Tacp3 (0x1 << 2)
#define S3C2410_BANKCON_Tacp4 (0x2 << 2)
#define S3C2410_BANKCON_Tacp6 (0x3 << 2)
#define S3C2410_BANKCON_Tcah0 (0x0 << 4)
#define S3C2410_BANKCON_Tcah1 (0x1 << 4)
#define S3C2410_BANKCON_Tcah2 (0x2 << 4)
#define S3C2410_BANKCON_Tcah4 (0x3 << 4)
#define S3C2410_BANKCON_Tcoh0 (0x0 << 6)
#define S3C2410_BANKCON_Tcoh1 (0x1 << 6)
#define S3C2410_BANKCON_Tcoh2 (0x2 << 6)
#define S3C2410_BANKCON_Tcoh4 (0x3 << 6)
#define S3C2410_BANKCON_Tacc1 (0x0 << 8)
#define S3C2410_BANKCON_Tacc2 (0x1 << 8)
#define S3C2410_BANKCON_Tacc3 (0x2 << 8)
#define S3C2410_BANKCON_Tacc4 (0x3 << 8)
#define S3C2410_BANKCON_Tacc6 (0x4 << 8)
#define S3C2410_BANKCON_Tacc8 (0x5 << 8)
#define S3C2410_BANKCON_Tacc10 (0x6 << 8)
#define S3C2410_BANKCON_Tacc14 (0x7 << 8)
#define S3C2410_BANKCON_Tcos0 (0x0 << 11)
#define S3C2410_BANKCON_Tcos1 (0x1 << 11)
#define S3C2410_BANKCON_Tcos2 (0x2 << 11)
#define S3C2410_BANKCON_Tcos4 (0x3 << 11)
#define S3C2410_BANKCON_Tacs0 (0x0 << 13)
#define S3C2410_BANKCON_Tacs1 (0x1 << 13)
#define S3C2410_BANKCON_Tacs2 (0x2 << 13)
#define S3C2410_BANKCON_Tacs4 (0x3 << 13)
#define S3C2410_BANKCON_SRAM (0x0 << 15)
#define S3C2410_BANKCON_SDRAM (0x3 << 15)
/* next bits only for SDRAM in 6,7 */
#define S3C2410_BANKCON_Trdc2 (0x00 << 2)
#define S3C2410_BANKCON_Trdc3 (0x01 << 2)
#define S3C2410_BANKCON_Trdc4 (0x02 << 2)
/* control column address select */
#define S3C2410_BANKCON_SCANb8 (0x00 << 0)
#define S3C2410_BANKCON_SCANb9 (0x01 << 0)
#define S3C2410_BANKCON_SCANb10 (0x02 << 0)
#define S3C2410_REFRESH S3C2410_MEMREG(0x0024)
#define S3C2410_BANKSIZE S3C2410_MEMREG(0x0028)
#define S3C2410_MRSRB6 S3C2410_MEMREG(0x002C)
#define S3C2410_MRSRB7 S3C2410_MEMREG(0x0030)
/* refresh control */
#define S3C2410_REFRESH_REFEN (1<<23)
#define S3C2410_REFRESH_SELF (1<<22)
#define S3C2410_REFRESH_REFCOUNTER ((1<<11)-1)
#define S3C2410_REFRESH_TRP_MASK (3<<20)
#define S3C2410_REFRESH_TRP_2clk (0<<20)
#define S3C2410_REFRESH_TRP_3clk (1<<20)
#define S3C2410_REFRESH_TRP_4clk (2<<20)
#define S3C2410_REFRESH_TSRC_MASK (3<<18)
#define S3C2410_REFRESH_TSRC_4clk (0<<18)
#define S3C2410_REFRESH_TSRC_5clk (1<<18)
#define S3C2410_REFRESH_TSRC_6clk (2<<18)
#define S3C2410_REFRESH_TSRC_7clk (3<<18)
/* mode select register(s) */
#define S3C2410_MRSRB_CL1 (0x00 << 4)
#define S3C2410_MRSRB_CL2 (0x02 << 4)
#define S3C2410_MRSRB_CL3 (0x03 << 4)
/* bank size register */
#define S3C2410_BANKSIZE_128M (0x2 << 0)
#define S3C2410_BANKSIZE_64M (0x1 << 0)
#define S3C2410_BANKSIZE_32M (0x0 << 0)
#define S3C2410_BANKSIZE_16M (0x7 << 0)
#define S3C2410_BANKSIZE_8M (0x6 << 0)
#define S3C2410_BANKSIZE_4M (0x5 << 0)
#define S3C2410_BANKSIZE_2M (0x4 << 0)
#define S3C2410_BANKSIZE_MASK (0x7 << 0)
#define S3C2410_BANKSIZE_SCLK_EN (1<<4)
#define S3C2410_BANKSIZE_SCKE_EN (1<<5)
#define S3C2410_BANKSIZE_BURST (1<<7)
#endif /* __ASM_ARM_MEMREGS_H */
include/asm-arm/arch-s3c2410/usb-control.h 0 → 100644
View file @ 57d62c2d
/* linux/include/asm-arm/arch-s3c2410/usb-control.h
*
* (c) 2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - usb port information
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 11-Sep-2004 BJD Created file
* 21-Sep-2004 BJD Updated port info
*/
#ifndef __ASM_ARCH_USBCONTROL_H
#define __ASM_ARCH_USBCONTROL_H "include/asm-arm/arch-s3c2410/usb-control.h"
#define S3C_HCDFLG_USED (1)
struct s3c2410_hcd_port {
unsigned char flags;
unsigned char power;
unsigned char oc_status;
unsigned char oc_changed;
};
struct s3c2410_hcd_info {
struct usb_hcd *hcd;
struct s3c2410_hcd_port port[2];
void (*power_control)(int port, int to);
void (*enable_oc)(struct s3c2410_hcd_info *, int on);
void (*report_oc)(struct s3c2410_hcd_info *, int ports);
};
static void inline s3c2410_report_oc(struct s3c2410_hcd_info *info, int ports)
{
if (info->report_oc != NULL) {
(info->report_oc)(info, ports);
}
}
#endif /*__ASM_ARCH_USBCONTROL_H */
include/asm-arm/bitops.h
View file @ 57d62c2d
......@@ -345,7 +345,7 @@ static inline unsigned long __ffs(unsigned long word)
extern __inline__ int generic_fls(int x);
#define fls(x) \
( __builtin_constant_p(x) ? generic_fls(x) : \
({ int __r; asm("clz%?\t%0, %1" : "=r"(__r) : "r"(x)); 32-__r; }) )
({ int __r; asm("clz\t%0, %1" : "=r"(__r) : "r"(x) : "cc"); 32-__r; }) )
#define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); })
#define __ffs(x) (ffs(x) - 1)
#define ffz(x) __ffs( ~(x) )
......
include/asm-arm/hardware/clock.h
View file @ 57d62c2d
......@@ -64,7 +64,7 @@ int clk_use(struct clk *clk);
void clk_unuse(struct clk *clk);
/**
* clk_get_rate - obtain the current clock rate for a clock source.
* clk_get_rate - obtain the current clock rate (in Hz) for a clock source.
* This is only valid once the clock source has been enabled.
* @clk: clock source
*/
......@@ -85,16 +85,16 @@ void clk_put(struct clk *clk);
/**
* clk_round_rate - adjust a rate to the exact rate a clock can provide
* @clk: clock source
* @rate: desired clock rate in kHz
* @rate: desired clock rate in Hz
*
* Returns rounded clock rate, or negative errno.
* Returns rounded clock rate in Hz, or negative errno.
*/
long clk_round_rate(struct clk *clk, unsigned long rate);
/**
* clk_set_rate - set the clock rate for a clock source
* @clk: clock source
* @rate: desired clock rate in kHz
* @rate: desired clock rate in Hz
*
* Returns success (0) or negative errno.
*/
......
include/asm-arm/system.h
View file @ 57d62c2d
......@@ -50,8 +50,10 @@
#define read_cpuid(reg) \
({ \
unsigned int __val; \
asm("mrc%? p15, 0, %0, c0, c0, " __stringify(reg) \
: "=r" (__val)); \
asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
: "=r" (__val) \
: \
: "cc"); \
__val; \
})
......
include/asm-arm/unistd.h
View file @ 57d62c2d
......@@ -299,6 +299,13 @@
#define __NR_pciconfig_iobase (__NR_SYSCALL_BASE+271)
#define __NR_pciconfig_read (__NR_SYSCALL_BASE+272)
#define __NR_pciconfig_write (__NR_SYSCALL_BASE+273)
#define __NR_mq_open (__NR_SYSCALL_BASE+274)
#define __NR_mq_unlink (__NR_SYSCALL_BASE+275)
#define __NR_mq_timedsend (__NR_SYSCALL_BASE+276)
#define __NR_mq_timedreceive (__NR_SYSCALL_BASE+277)
#define __NR_mq_notify (__NR_SYSCALL_BASE+278)
#define __NR_mq_getsetattr (__NR_SYSCALL_BASE+279)
#define __NR_waitid (__NR_SYSCALL_BASE+280)
/*
* The following SWIs are ARM private.
......
include/asm-ppc/mpc52xx.h
View file @ 57d62c2d
......@@ -42,6 +42,7 @@ struct ocp_def;
#define MPC52xx_MBAR_VIRT 0xf0000000 /* Virt address */
#define MPC52xx_MMAP_CTL (MPC52xx_MBAR + 0x0000)
#define MPC52xx_SDRAM (MPC52xx_MBAR + 0x0100)
#define MPC52xx_CDM (MPC52xx_MBAR + 0x0200)
#define MPC52xx_SFTRST (MPC52xx_MBAR + 0x0220)
#define MPC52xx_SFTRST_BIT 0x01000000
......@@ -51,6 +52,7 @@ struct ocp_def;
#define MPC52xx_MSCAN1 (MPC52xx_MBAR + 0x0900)
#define MPC52xx_MSCAN2 (MPC52xx_MBAR + 0x0980)
#define MPC52xx_GPIO (MPC52xx_MBAR + 0x0b00)
#define MPC52xx_GPIO_WKUP (MPC52xx_MBAR + 0x0c00)
#define MPC52xx_PCI (MPC52xx_MBAR + 0x0d00)
#define MPC52xx_USB_OHCI (MPC52xx_MBAR + 0x1000)
#define MPC52xx_SDMA (MPC52xx_MBAR + 0x1200)
......@@ -71,10 +73,6 @@ struct ocp_def;
/* SRAM used for SDMA */
#define MPC52xx_SRAM (MPC52xx_MBAR + 0x8000)
#define MPC52xx_SRAM_SIZE (16*1024)
#define MPC52xx_SDMA_MAX_TASKS 16
/* Memory allocation block size */
#define MPC52xx_SDRAM_UNIT 0x8000 /* 32K byte */
/* ======================================================================== */
......@@ -137,206 +135,240 @@ struct ocp_def;
/* Memory Mapping Control */
struct mpc52xx_mmap_ctl {
volatile u32 mbar; /* MMAP_CTRL + 0x00 */
volatile u32 cs0_start; /* MMAP_CTRL + 0x04 */
volatile u32 cs0_stop; /* MMAP_CTRL + 0x08 */
volatile u32 cs1_start; /* MMAP_CTRL + 0x0c */
volatile u32 cs1_stop; /* MMAP_CTRL + 0x10 */
volatile u32 cs2_start; /* MMAP_CTRL + 0x14 */
volatile u32 cs2_stop; /* MMAP_CTRL + 0x18 */
volatile u32 cs3_start; /* MMAP_CTRL + 0x1c */
volatile u32 cs3_stop; /* MMAP_CTRL + 0x20 */
volatile u32 cs4_start; /* MMAP_CTRL + 0x24 */
volatile u32 cs4_stop; /* MMAP_CTRL + 0x28 */
volatile u32 cs5_start; /* MMAP_CTRL + 0x2c */
volatile u32 cs5_stop; /* MMAP_CTRL + 0x30 */
volatile u32 sdram0; /* MMAP_CTRL + 0x34 */
volatile u32 sdram1; /* MMAP_CTRL + 0X38 */
volatile u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
volatile u32 boot_start; /* MMAP_CTRL + 0x4c */
volatile u32 boot_stop; /* MMAP_CTRL + 0x50 */
volatile u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */
volatile u32 cs6_start; /* MMAP_CTRL + 0x58 */
volatile u32 cs6_stop; /* MMAP_CTRL + 0x5c */
volatile u32 cs7_start; /* MMAP_CTRL + 0x60 */
volatile u32 cs7_stop; /* MMAP_CTRL + 0x60 */
u32 mbar; /* MMAP_CTRL + 0x00 */
u32 cs0_start; /* MMAP_CTRL + 0x04 */
u32 cs0_stop; /* MMAP_CTRL + 0x08 */
u32 cs1_start; /* MMAP_CTRL + 0x0c */
u32 cs1_stop; /* MMAP_CTRL + 0x10 */
u32 cs2_start; /* MMAP_CTRL + 0x14 */
u32 cs2_stop; /* MMAP_CTRL + 0x18 */
u32 cs3_start; /* MMAP_CTRL + 0x1c */
u32 cs3_stop; /* MMAP_CTRL + 0x20 */
u32 cs4_start; /* MMAP_CTRL + 0x24 */
u32 cs4_stop; /* MMAP_CTRL + 0x28 */
u32 cs5_start; /* MMAP_CTRL + 0x2c */
u32 cs5_stop; /* MMAP_CTRL + 0x30 */
u32 sdram0; /* MMAP_CTRL + 0x34 */
u32 sdram1; /* MMAP_CTRL + 0X38 */
u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
u32 boot_start; /* MMAP_CTRL + 0x4c */
u32 boot_stop; /* MMAP_CTRL + 0x50 */
u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */
u32 cs6_start; /* MMAP_CTRL + 0x58 */
u32 cs6_stop; /* MMAP_CTRL + 0x5c */
u32 cs7_start; /* MMAP_CTRL + 0x60 */
u32 cs7_stop; /* MMAP_CTRL + 0x60 */
};
/* SDRAM control */
struct mpc52xx_sdram {
u32 mode; /* SDRAM + 0x00 */
u32 ctrl; /* SDRAM + 0x04 */
u32 config1; /* SDRAM + 0x08 */
u32 config2; /* SDRAM + 0x0c */
};
/* Interrupt controller */
struct mpc52xx_intr {
volatile u32 per_mask; /* INTR + 0x00 */
volatile u32 per_pri1; /* INTR + 0x04 */
volatile u32 per_pri2; /* INTR + 0x08 */
volatile u32 per_pri3; /* INTR + 0x0c */
volatile u32 ctrl; /* INTR + 0x10 */
volatile u32 main_mask; /* INTR + 0x14 */
volatile u32 main_pri1; /* INTR + 0x18 */
volatile u32 main_pri2; /* INTR + 0x1c */
volatile u32 reserved1; /* INTR + 0x20 */
volatile u32 enc_status; /* INTR + 0x24 */
volatile u32 crit_status; /* INTR + 0x28 */
volatile u32 main_status; /* INTR + 0x2c */
volatile u32 per_status; /* INTR + 0x30 */
volatile u32 reserved2; /* INTR + 0x34 */
volatile u32 per_error; /* INTR + 0x38 */
u32 per_mask; /* INTR + 0x00 */
u32 per_pri1; /* INTR + 0x04 */
u32 per_pri2; /* INTR + 0x08 */
u32 per_pri3; /* INTR + 0x0c */
u32 ctrl; /* INTR + 0x10 */
u32 main_mask; /* INTR + 0x14 */
u32 main_pri1; /* INTR + 0x18 */
u32 main_pri2; /* INTR + 0x1c */
u32 reserved1; /* INTR + 0x20 */
u32 enc_status; /* INTR + 0x24 */
u32 crit_status; /* INTR + 0x28 */
u32 main_status; /* INTR + 0x2c */
u32 per_status; /* INTR + 0x30 */
u32 reserved2; /* INTR + 0x34 */
u32 per_error; /* INTR + 0x38 */
};
/* SDMA */
struct mpc52xx_sdma {
volatile u32 taskBar; /* SDMA + 0x00 */
volatile u32 currentPointer; /* SDMA + 0x04 */
volatile u32 endPointer; /* SDMA + 0x08 */
volatile u32 variablePointer;/* SDMA + 0x0c */
volatile u8 IntVect1; /* SDMA + 0x10 */
volatile u8 IntVect2; /* SDMA + 0x11 */
volatile u16 PtdCntrl; /* SDMA + 0x12 */
volatile u32 IntPend; /* SDMA + 0x14 */
volatile u32 IntMask; /* SDMA + 0x18 */
volatile u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */
volatile u8 ipr[31]; /* SDMA + 0x3c .. 5b */
volatile u32 res1; /* SDMA + 0x5c */
volatile u32 task_size0; /* SDMA + 0x60 */
volatile u32 task_size1; /* SDMA + 0x64 */
volatile u32 MDEDebug; /* SDMA + 0x68 */
volatile u32 ADSDebug; /* SDMA + 0x6c */
volatile u32 Value1; /* SDMA + 0x70 */
volatile u32 Value2; /* SDMA + 0x74 */
volatile u32 Control; /* SDMA + 0x78 */
volatile u32 Status; /* SDMA + 0x7c */
u32 taskBar; /* SDMA + 0x00 */
u32 currentPointer; /* SDMA + 0x04 */
u32 endPointer; /* SDMA + 0x08 */
u32 variablePointer;/* SDMA + 0x0c */
u8 IntVect1; /* SDMA + 0x10 */
u8 IntVect2; /* SDMA + 0x11 */
u16 PtdCntrl; /* SDMA + 0x12 */
u32 IntPend; /* SDMA + 0x14 */
u32 IntMask; /* SDMA + 0x18 */
u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */
u8 ipr[32]; /* SDMA + 0x3c .. 5b */
u32 cReqSelect; /* SDMA + 0x5c */
u32 task_size0; /* SDMA + 0x60 */
u32 task_size1; /* SDMA + 0x64 */
u32 MDEDebug; /* SDMA + 0x68 */
u32 ADSDebug; /* SDMA + 0x6c */
u32 Value1; /* SDMA + 0x70 */
u32 Value2; /* SDMA + 0x74 */
u32 Control; /* SDMA + 0x78 */
u32 Status; /* SDMA + 0x7c */
u32 PTDDebug; /* SDMA + 0x80 */
};
/* GPT */
struct mpc52xx_gpt {
volatile u32 mode; /* GPTx + 0x00 */
volatile u32 count; /* GPTx + 0x04 */
volatile u32 pwm; /* GPTx + 0x08 */
volatile u32 status; /* GPTx + 0X0c */
u32 mode; /* GPTx + 0x00 */
u32 count; /* GPTx + 0x04 */
u32 pwm; /* GPTx + 0x08 */
u32 status; /* GPTx + 0X0c */
};
/* RTC */
struct mpc52xx_rtc {
volatile u32 time_set; /* RTC + 0x00 */
volatile u32 date_set; /* RTC + 0x04 */
volatile u32 stopwatch; /* RTC + 0x08 */
volatile u32 int_enable; /* RTC + 0x0c */
volatile u32 time; /* RTC + 0x10 */
volatile u32 date; /* RTC + 0x14 */
volatile u32 stopwatch_intr; /* RTC + 0x18 */
volatile u32 bus_error; /* RTC + 0x1c */
volatile u32 dividers; /* RTC + 0x20 */
u32 time_set; /* RTC + 0x00 */
u32 date_set; /* RTC + 0x04 */
u32 stopwatch; /* RTC + 0x08 */
u32 int_enable; /* RTC + 0x0c */
u32 time; /* RTC + 0x10 */
u32 date; /* RTC + 0x14 */
u32 stopwatch_intr; /* RTC + 0x18 */
u32 bus_error; /* RTC + 0x1c */
u32 dividers; /* RTC + 0x20 */
};
/* GPIO */
struct mpc52xx_gpio {
volatile u32 port_config; /* GPIO + 0x00 */
volatile u32 simple_gpioe; /* GPIO + 0x04 */
volatile u32 simple_ode; /* GPIO + 0x08 */
volatile u32 simple_ddr; /* GPIO + 0x0c */
volatile u32 simple_dvo; /* GPIO + 0x10 */
volatile u32 simple_ival; /* GPIO + 0x14 */
volatile u8 outo_gpioe; /* GPIO + 0x18 */
volatile u8 reserved1[3]; /* GPIO + 0x19 */
volatile u8 outo_dvo; /* GPIO + 0x1c */
volatile u8 reserved2[3]; /* GPIO + 0x1d */
volatile u8 sint_gpioe; /* GPIO + 0x20 */
volatile u8 reserved3[3]; /* GPIO + 0x21 */
volatile u8 sint_ode; /* GPIO + 0x24 */
volatile u8 reserved4[3]; /* GPIO + 0x25 */
volatile u8 sint_ddr; /* GPIO + 0x28 */
volatile u8 reserved5[3]; /* GPIO + 0x29 */
volatile u8 sint_dvo; /* GPIO + 0x2c */
volatile u8 reserved6[3]; /* GPIO + 0x2d */
volatile u8 sint_inten; /* GPIO + 0x30 */
volatile u8 reserved7[3]; /* GPIO + 0x31 */
volatile u16 sint_itype; /* GPIO + 0x34 */
volatile u16 reserved8; /* GPIO + 0x36 */
volatile u8 gpio_control; /* GPIO + 0x38 */
volatile u8 reserved9[3]; /* GPIO + 0x39 */
volatile u8 sint_istat; /* GPIO + 0x3c */
volatile u8 sint_ival; /* GPIO + 0x3d */
volatile u8 bus_errs; /* GPIO + 0x3e */
volatile u8 reserved10; /* GPIO + 0x3f */
u32 port_config; /* GPIO + 0x00 */
u32 simple_gpioe; /* GPIO + 0x04 */
u32 simple_ode; /* GPIO + 0x08 */
u32 simple_ddr; /* GPIO + 0x0c */
u32 simple_dvo; /* GPIO + 0x10 */
u32 simple_ival; /* GPIO + 0x14 */
u8 outo_gpioe; /* GPIO + 0x18 */
u8 reserved1[3]; /* GPIO + 0x19 */
u8 outo_dvo; /* GPIO + 0x1c */
u8 reserved2[3]; /* GPIO + 0x1d */
u8 sint_gpioe; /* GPIO + 0x20 */
u8 reserved3[3]; /* GPIO + 0x21 */
u8 sint_ode; /* GPIO + 0x24 */
u8 reserved4[3]; /* GPIO + 0x25 */
u8 sint_ddr; /* GPIO + 0x28 */
u8 reserved5[3]; /* GPIO + 0x29 */
u8 sint_dvo; /* GPIO + 0x2c */
u8 reserved6[3]; /* GPIO + 0x2d */
u8 sint_inten; /* GPIO + 0x30 */
u8 reserved7[3]; /* GPIO + 0x31 */
u16 sint_itype; /* GPIO + 0x34 */
u16 reserved8; /* GPIO + 0x36 */
u8 gpio_control; /* GPIO + 0x38 */
u8 reserved9[3]; /* GPIO + 0x39 */
u8 sint_istat; /* GPIO + 0x3c */
u8 sint_ival; /* GPIO + 0x3d */
u8 bus_errs; /* GPIO + 0x3e */
u8 reserved10; /* GPIO + 0x3f */
};
#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5
#define MPC52xx_GPIO_PCI_DIS (1<<15)
/* GPIO with WakeUp*/
struct mpc52xx_gpio_wkup {
u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */
u8 reserved1[3]; /* GPIO_WKUP + 0x03 */
u8 wkup_ode; /* GPIO_WKUP + 0x04 */
u8 reserved2[3]; /* GPIO_WKUP + 0x05 */
u8 wkup_ddr; /* GPIO_WKUP + 0x08 */
u8 reserved3[3]; /* GPIO_WKUP + 0x09 */
u8 wkup_dvo; /* GPIO_WKUP + 0x0C */
u8 reserved4[3]; /* GPIO_WKUP + 0x0D */
u8 wkup_inten; /* GPIO_WKUP + 0x10 */
u8 reserved5[3]; /* GPIO_WKUP + 0x11 */
u8 wkup_iinten; /* GPIO_WKUP + 0x14 */
u8 reserved6[3]; /* GPIO_WKUP + 0x15 */
u16 wkup_itype; /* GPIO_WKUP + 0x18 */
u8 reserved7[2]; /* GPIO_WKUP + 0x1A */
u8 wkup_maste; /* GPIO_WKUP + 0x1C */
u8 reserved8[3]; /* GPIO_WKUP + 0x1D */
u8 wkup_ival; /* GPIO_WKUP + 0x20 */
u8 reserved9[3]; /* GPIO_WKUP + 0x21 */
u8 wkup_istat; /* GPIO_WKUP + 0x24 */
u8 reserved10[3]; /* GPIO_WKUP + 0x25 */
};
/* XLB Bus control */
struct mpc52xx_xlb {
volatile u8 reserved[0x40];
volatile u32 config; /* XLB + 0x40 */
volatile u32 version; /* XLB + 0x44 */
volatile u32 status; /* XLB + 0x48 */
volatile u32 int_enable; /* XLB + 0x4c */
volatile u32 addr_capture; /* XLB + 0x50 */
volatile u32 bus_sig_capture; /* XLB + 0x54 */
volatile u32 addr_timeout; /* XLB + 0x58 */
volatile u32 data_timeout; /* XLB + 0x5c */
volatile u32 bus_act_timeout; /* XLB + 0x60 */
volatile u32 master_pri_enable; /* XLB + 0x64 */
volatile u32 master_priority; /* XLB + 0x68 */
volatile u32 base_address; /* XLB + 0x6c */
volatile u32 snoop_window; /* XLB + 0x70 */
u8 reserved[0x40];
u32 config; /* XLB + 0x40 */
u32 version; /* XLB + 0x44 */
u32 status; /* XLB + 0x48 */
u32 int_enable; /* XLB + 0x4c */
u32 addr_capture; /* XLB + 0x50 */
u32 bus_sig_capture; /* XLB + 0x54 */
u32 addr_timeout; /* XLB + 0x58 */
u32 data_timeout; /* XLB + 0x5c */
u32 bus_act_timeout; /* XLB + 0x60 */
u32 master_pri_enable; /* XLB + 0x64 */
u32 master_priority; /* XLB + 0x68 */
u32 base_address; /* XLB + 0x6c */
u32 snoop_window; /* XLB + 0x70 */
};
#define MPC52xx_XLB_CFG_SNOOP (1 << 15)
/* Clock Distribution control */
struct mpc52xx_cdm {
volatile u32 jtag_id; /* MBAR_CDM + 0x00 reg0 read only */
volatile u32 rstcfg; /* MBAR_CDM + 0x04 reg1 read only */
volatile u32 breadcrumb; /* MBAR_CDM + 0x08 reg2 */
volatile u8 mem_clk_sel; /* MBAR_CDM + 0x0c reg3 byte0 */
volatile u8 xlb_clk_sel; /* MBAR_CDM + 0x0d reg3 byte1 read only */
volatile u8 ipb_clk_sel; /* MBAR_CDM + 0x0e reg3 byte2 */
volatile u8 pci_clk_sel; /* MBAR_CDM + 0x0f reg3 byte3 */
volatile u8 ext_48mhz_en; /* MBAR_CDM + 0x10 reg4 byte0 */
volatile u8 fd_enable; /* MBAR_CDM + 0x11 reg4 byte1 */
volatile u16 fd_counters; /* MBAR_CDM + 0x12 reg4 byte2,3 */
volatile u32 clk_enables; /* MBAR_CDM + 0x14 reg5 */
volatile u8 osc_disable; /* MBAR_CDM + 0x18 reg6 byte0 */
volatile u8 reserved0[3]; /* MBAR_CDM + 0x19 reg6 byte1,2,3 */
volatile u8 ccs_sleep_enable;/* MBAR_CDM + 0x1c reg7 byte0 */
volatile u8 osc_sleep_enable;/* MBAR_CDM + 0x1d reg7 byte1 */
volatile u8 reserved1; /* MBAR_CDM + 0x1e reg7 byte2 */
volatile u8 ccs_qreq_test; /* MBAR_CDM + 0x1f reg7 byte3 */
volatile u8 soft_reset; /* MBAR_CDM + 0x20 u8 byte0 */
volatile u8 no_ckstp; /* MBAR_CDM + 0x21 u8 byte0 */
volatile u8 reserved2[2]; /* MBAR_CDM + 0x22 u8 byte1,2,3 */
volatile u8 pll_lock; /* MBAR_CDM + 0x24 reg9 byte0 */
volatile u8 pll_looselock; /* MBAR_CDM + 0x25 reg9 byte1 */
volatile u8 pll_sm_lockwin; /* MBAR_CDM + 0x26 reg9 byte2 */
volatile u8 reserved3; /* MBAR_CDM + 0x27 reg9 byte3 */
volatile u16 reserved4; /* MBAR_CDM + 0x28 reg10 byte0,1 */
volatile u16 mclken_div_psc1;/* MBAR_CDM + 0x2a reg10 byte2,3 */
volatile u16 reserved5; /* MBAR_CDM + 0x2c reg11 byte0,1 */
volatile u16 mclken_div_psc2;/* MBAR_CDM + 0x2e reg11 byte2,3 */
volatile u16 reserved6; /* MBAR_CDM + 0x30 reg12 byte0,1 */
volatile u16 mclken_div_psc3;/* MBAR_CDM + 0x32 reg12 byte2,3 */
volatile u16 reserved7; /* MBAR_CDM + 0x34 reg13 byte0,1 */
volatile u16 mclken_div_psc6;/* MBAR_CDM + 0x36 reg13 byte2,3 */
u32 jtag_id; /* CDM + 0x00 reg0 read only */
u32 rstcfg; /* CDM + 0x04 reg1 read only */
u32 breadcrumb; /* CDM + 0x08 reg2 */
u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */
u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */
u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */
u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */
u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */
u8 fd_enable; /* CDM + 0x11 reg4 byte1 */
u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */
u32 clk_enables; /* CDM + 0x14 reg5 */
u8 osc_disable; /* CDM + 0x18 reg6 byte0 */
u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */
u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */
u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */
u8 reserved1; /* CDM + 0x1e reg7 byte2 */
u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */
u8 soft_reset; /* CDM + 0x20 u8 byte0 */
u8 no_ckstp; /* CDM + 0x21 u8 byte0 */
u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */
u8 pll_lock; /* CDM + 0x24 reg9 byte0 */
u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */
u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */
u8 reserved3; /* CDM + 0x27 reg9 byte3 */
u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */
u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */
u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */
u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */
u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */
u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */
u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */
u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */
};
#endif /* __ASSEMBLY__ */
......
include/asm-ppc/mpc52xx_psc.h
View file @ 57d62c2d
......@@ -19,8 +19,8 @@
* kind, whether express or implied.
*/
#ifndef __MPC52xx_PSC_H__
#define __MPC52xx_PSC_H__
#ifndef __ASM_MPC52xx_PSC_H__
#define __ASM_MPC52xx_PSC_H__
#include <asm/types.h>
......@@ -95,97 +95,97 @@
/* Structure of the hardware registers */
struct mpc52xx_psc {
volatile u8 mode; /* PSC + 0x00 */
volatile u8 reserved0[3];
union { /* PSC + 0x04 */
volatile u16 status;
volatile u16 clock_select;
u8 mode; /* PSC + 0x00 */
u8 reserved0[3];
union { /* PSC + 0x04 */
u16 status;
u16 clock_select;
} sr_csr;
#define mpc52xx_psc_status sr_csr.status
#define mpc52xx_psc_clock_select sr_csr.clock_select
volatile u16 reserved1;
volatile u8 command; /* PSC + 0x08 */
volatile u8 reserved2[3];
union { /* PSC + 0x0c */
volatile u8 buffer_8;
volatile u16 buffer_16;
volatile u32 buffer_32;
#define mpc52xx_psc_clock_select sr_csr.clock_select
u16 reserved1;
u8 command; /* PSC + 0x08 */
u8 reserved2[3];
union { /* PSC + 0x0c */
u8 buffer_8;
u16 buffer_16;
u32 buffer_32;
} buffer;
#define mpc52xx_psc_buffer_8 buffer.buffer_8
#define mpc52xx_psc_buffer_16 buffer.buffer_16
#define mpc52xx_psc_buffer_32 buffer.buffer_32
union { /* PSC + 0x10 */
volatile u8 ipcr;
volatile u8 acr;
union { /* PSC + 0x10 */
u8 ipcr;
u8 acr;
} ipcr_acr;
#define mpc52xx_psc_ipcr ipcr_acr.ipcr
#define mpc52xx_psc_acr ipcr_acr.acr
volatile u8 reserved3[3];
union { /* PSC + 0x14 */
volatile u16 isr;
volatile u16 imr;
u8 reserved3[3];
union { /* PSC + 0x14 */
u16 isr;
u16 imr;
} isr_imr;
#define mpc52xx_psc_isr isr_imr.isr
#define mpc52xx_psc_imr isr_imr.imr
volatile u16 reserved4;
volatile u8 ctur; /* PSC + 0x18 */
volatile u8 reserved5[3];
volatile u8 ctlr; /* PSC + 0x1c */
volatile u8 reserved6[3];
volatile u16 ccr; /* PSC + 0x20 */
volatile u8 reserved7[14];
volatile u8 ivr; /* PSC + 0x30 */
volatile u8 reserved8[3];
volatile u8 ip; /* PSC + 0x34 */
volatile u8 reserved9[3];
volatile u8 op1; /* PSC + 0x38 */
volatile u8 reserved10[3];
volatile u8 op0; /* PSC + 0x3c */
volatile u8 reserved11[3];
volatile u32 sicr; /* PSC + 0x40 */
volatile u8 ircr1; /* PSC + 0x44 */
volatile u8 reserved13[3];
volatile u8 ircr2; /* PSC + 0x44 */
volatile u8 reserved14[3];
volatile u8 irsdr; /* PSC + 0x4c */
volatile u8 reserved15[3];
volatile u8 irmdr; /* PSC + 0x50 */
volatile u8 reserved16[3];
volatile u8 irfdr; /* PSC + 0x54 */
volatile u8 reserved17[3];
volatile u16 rfnum; /* PSC + 0x58 */
volatile u16 reserved18;
volatile u16 tfnum; /* PSC + 0x5c */
volatile u16 reserved19;
volatile u32 rfdata; /* PSC + 0x60 */
volatile u16 rfstat; /* PSC + 0x64 */
volatile u16 reserved20;
volatile u8 rfcntl; /* PSC + 0x68 */
volatile u8 reserved21[5];
volatile u16 rfalarm; /* PSC + 0x6e */
volatile u16 reserved22;
volatile u16 rfrptr; /* PSC + 0x72 */
volatile u16 reserved23;
volatile u16 rfwptr; /* PSC + 0x76 */
volatile u16 reserved24;
volatile u16 rflrfptr; /* PSC + 0x7a */
volatile u16 reserved25;
volatile u16 rflwfptr; /* PSC + 0x7e */
volatile u32 tfdata; /* PSC + 0x80 */
volatile u16 tfstat; /* PSC + 0x84 */
volatile u16 reserved26;
volatile u8 tfcntl; /* PSC + 0x88 */
volatile u8 reserved27[5];
volatile u16 tfalarm; /* PSC + 0x8e */
volatile u16 reserved28;
volatile u16 tfrptr; /* PSC + 0x92 */
volatile u16 reserved29;
volatile u16 tfwptr; /* PSC + 0x96 */
volatile u16 reserved30;
volatile u16 tflrfptr; /* PSC + 0x9a */
volatile u16 reserved31;
volatile u16 tflwfptr; /* PSC + 0x9e */
u16 reserved4;
u8 ctur; /* PSC + 0x18 */
u8 reserved5[3];
u8 ctlr; /* PSC + 0x1c */
u8 reserved6[3];
u16 ccr; /* PSC + 0x20 */
u8 reserved7[14];
u8 ivr; /* PSC + 0x30 */
u8 reserved8[3];
u8 ip; /* PSC + 0x34 */
u8 reserved9[3];
u8 op1; /* PSC + 0x38 */
u8 reserved10[3];
u8 op0; /* PSC + 0x3c */
u8 reserved11[3];
u32 sicr; /* PSC + 0x40 */
u8 ircr1; /* PSC + 0x44 */
u8 reserved13[3];
u8 ircr2; /* PSC + 0x44 */
u8 reserved14[3];
u8 irsdr; /* PSC + 0x4c */
u8 reserved15[3];
u8 irmdr; /* PSC + 0x50 */
u8 reserved16[3];
u8 irfdr; /* PSC + 0x54 */
u8 reserved17[3];
u16 rfnum; /* PSC + 0x58 */
u16 reserved18;
u16 tfnum; /* PSC + 0x5c */
u16 reserved19;
u32 rfdata; /* PSC + 0x60 */
u16 rfstat; /* PSC + 0x64 */
u16 reserved20;
u8 rfcntl; /* PSC + 0x68 */
u8 reserved21[5];
u16 rfalarm; /* PSC + 0x6e */
u16 reserved22;
u16 rfrptr; /* PSC + 0x72 */
u16 reserved23;
u16 rfwptr; /* PSC + 0x76 */
u16 reserved24;
u16 rflrfptr; /* PSC + 0x7a */
u16 reserved25;
u16 rflwfptr; /* PSC + 0x7e */
u32 tfdata; /* PSC + 0x80 */
u16 tfstat; /* PSC + 0x84 */
u16 reserved26;
u8 tfcntl; /* PSC + 0x88 */
u8 reserved27[5];
u16 tfalarm; /* PSC + 0x8e */
u16 reserved28;
u16 tfrptr; /* PSC + 0x92 */
u16 reserved29;
u16 tfwptr; /* PSC + 0x96 */
u16 reserved30;
u16 tflrfptr; /* PSC + 0x9a */
u16 reserved31;
u16 tflwfptr; /* PSC + 0x9e */
};
#endif /* __MPC52xx_PSC_H__ */
#endif /* __ASM_MPC52xx_PSC_H__ */
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