Commit 57ff9d73 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman

ARM: dts: r8a7794: Add Z2 clock

Add the Z2 clock (Cortex-A7 CPU core clock), which uses a fixed divider,
and link the first CPU node to it.
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 7b39e985
...@@ -43,6 +43,7 @@ cpu0: cpu@0 { ...@@ -43,6 +43,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a7"; compatible = "arm,cortex-a7";
reg = <0>; reg = <0>;
clock-frequency = <1000000000>; clock-frequency = <1000000000>;
clocks = <&z2_clk>;
power-domains = <&sysc R8A7794_PD_CA7_CPU0>; power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
next-level-cache = <&L2_CA7>; next-level-cache = <&L2_CA7>;
}; };
...@@ -1064,6 +1065,13 @@ pll1_div2_clk: pll1_div2 { ...@@ -1064,6 +1065,13 @@ pll1_div2_clk: pll1_div2 {
clock-div = <2>; clock-div = <2>;
clock-mult = <1>; clock-mult = <1>;
}; };
z2_clk: z2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL0>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
};
zg_clk: zg { zg_clk: zg {
compatible = "fixed-factor-clock"; compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL1>; clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
......
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