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Commit 5841f6c0 authored by Maxime Ripard's avatar Maxime Ripard
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ARM: dts: sunxi: Remove leading zeros from unit-addresses 

Most of our device trees have had leading zeros for padding as part of
the nodes unit-addresses.

Remove all these useless zeros that generate warnings
Acked-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 23edc168
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Showing with 323 additions and 323 deletions
arch/arm/boot/dts/sun4i-a10.dtsi
View file @ 5841f6c0
This diff is collapsed.
arch/arm/boot/dts/sun5i-a10s.dtsi
View file @ 5841f6c0
......@@ -76,8 +76,8 @@ display-engine {
allwinner,pipelines = <&fe0>;
};
soc@01c00000 {
hdmi: hdmi@01c16000 {
soc@1c00000 {
hdmi: hdmi@1c16000 {
compatible = "allwinner,sun5i-a10s-hdmi";
reg = <0x01c16000 0x1000>;
interrupts = <58>;
......@@ -111,7 +111,7 @@ hdmi_out: port@1 {
};
};
pwm: pwm@01c20e00 {
pwm: pwm@1c20e00 {
compatible = "allwinner,sun5i-a10s-pwm";
reg = <0x01c20e00 0xc>;
clocks = <&ccu CLK_HOSC>;
......
arch/arm/boot/dts/sun5i-a13.dtsi
View file @ 5841f6c0
......@@ -88,8 +88,8 @@ display-engine {
allwinner,pipelines = <&fe0>;
};
soc@01c00000 {
pwm: pwm@01c20e00 {
soc@1c00000 {
pwm: pwm@1c20e00 {
compatible = "allwinner,sun5i-a13-pwm";
reg = <0x01c20e00 0xc>;
clocks = <&ccu CLK_HOSC>;
......
arch/arm/boot/dts/sun5i-gr8.dtsi
View file @ 5841f6c0
......@@ -54,8 +54,8 @@ display-engine {
allwinner,pipelines = <&fe0>;
};
soc@01c00000 {
pwm: pwm@01c20e00 {
soc@1c00000 {
pwm: pwm@1c20e00 {
compatible = "allwinner,sun5i-a10s-pwm";
reg = <0x01c20e00 0xc>;
clocks = <&ccu CLK_HOSC>;
......@@ -63,7 +63,7 @@ pwm: pwm@01c20e00 {
status = "disabled";
};
spdif: spdif@01c21000 {
spdif: spdif@1c21000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun4i-a10-spdif";
reg = <0x01c21000 0x400>;
......@@ -76,7 +76,7 @@ spdif: spdif@01c21000 {
status = "disabled";
};
i2s0: i2s@01c22400 {
i2s0: i2s@1c22400 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun4i-a10-i2s";
reg = <0x01c22400 0x400>;
......
arch/arm/boot/dts/sun5i.dtsi
View file @ 5841f6c0
......@@ -93,7 +93,7 @@ clocks {
#size-cells = <1>;
ranges;
osc24M: clk@01c20050 {
osc24M: clk@1c20050 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
......@@ -108,13 +108,13 @@ osc32k: clk@0 {
};
};
soc@01c00000 {
soc@1c00000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram-controller@01c00000 {
sram-controller@1c00000 {
compatible = "allwinner,sun4i-a10-sram-controller";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
......@@ -135,7 +135,7 @@ emac_sram: sram-section@8000 {
status = "disabled";
};
sram_d: sram@00010000 {
sram_d: sram@10000 {
compatible = "mmio-sram";
reg = <0x00010000 0x1000>;
#address-cells = <1>;
......@@ -150,7 +150,7 @@ otg_sram: sram-section@0000 {
};
};
dma: dma-controller@01c02000 {
dma: dma-controller@1c02000 {
compatible = "allwinner,sun4i-a10-dma";
reg = <0x01c02000 0x1000>;
interrupts = <27>;
......@@ -158,7 +158,7 @@ dma: dma-controller@01c02000 {
#dma-cells = <2>;
};
nfc: nand@01c03000 {
nfc: nand@1c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <37>;
......@@ -171,7 +171,7 @@ nfc: nand@01c03000 {
#size-cells = <0>;
};
spi0: spi@01c05000 {
spi0: spi@1c05000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c05000 0x1000>;
interrupts = <10>;
......@@ -185,7 +185,7 @@ spi0: spi@01c05000 {
#size-cells = <0>;
};
spi1: spi@01c06000 {
spi1: spi@1c06000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c06000 0x1000>;
interrupts = <11>;
......@@ -199,7 +199,7 @@ spi1: spi@01c06000 {
#size-cells = <0>;
};
tve0: tv-encoder@01c0a000 {
tve0: tv-encoder@1c0a000 {
compatible = "allwinner,sun4i-a10-tv-encoder";
reg = <0x01c0a000 0x1000>;
clocks = <&ccu CLK_AHB_TVE>;
......@@ -217,7 +217,7 @@ tve0_in_tcon0: endpoint@0 {
};
};
emac: ethernet@01c0b000 {
emac: ethernet@1c0b000 {
compatible = "allwinner,sun4i-a10-emac";
reg = <0x01c0b000 0x1000>;
interrupts = <55>;
......@@ -226,7 +226,7 @@ emac: ethernet@01c0b000 {
status = "disabled";
};
mdio: mdio@01c0b080 {
mdio: mdio@1c0b080 {
compatible = "allwinner,sun4i-a10-mdio";
reg = <0x01c0b080 0x14>;
status = "disabled";
......@@ -234,7 +234,7 @@ mdio: mdio@01c0b080 {
#size-cells = <0>;
};
tcon0: lcd-controller@01c0c000 {
tcon0: lcd-controller@1c0c000 {
compatible = "allwinner,sun5i-a13-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <44>;
......@@ -278,7 +278,7 @@ tcon0_out_tve0: endpoint@1 {
};
};
mmc0: mmc@01c0f000 {
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
......@@ -289,7 +289,7 @@ mmc0: mmc@01c0f000 {
#size-cells = <0>;
};
mmc1: mmc@01c10000 {
mmc1: mmc@1c10000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
......@@ -300,7 +300,7 @@ mmc1: mmc@01c10000 {
#size-cells = <0>;
};
mmc2: mmc@01c11000 {
mmc2: mmc@1c11000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c11000 0x1000>;
clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
......@@ -311,7 +311,7 @@ mmc2: mmc@01c11000 {
#size-cells = <0>;
};
usb_otg: usb@01c13000 {
usb_otg: usb@1c13000 {
compatible = "allwinner,sun4i-a10-musb";
reg = <0x01c13000 0x0400>;
clocks = <&ccu CLK_AHB_OTG>;
......@@ -324,7 +324,7 @@ usb_otg: usb@01c13000 {
status = "disabled";
};
usbphy: phy@01c13400 {
usbphy: phy@1c13400 {
#phy-cells = <1>;
compatible = "allwinner,sun5i-a13-usb-phy";
reg = <0x01c13400 0x10 0x01c14800 0x4>;
......@@ -336,7 +336,7 @@ usbphy: phy@01c13400 {
status = "disabled";
};
ehci0: usb@01c14000 {
ehci0: usb@1c14000 {
compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
reg = <0x01c14000 0x100>;
interrupts = <39>;
......@@ -346,7 +346,7 @@ ehci0: usb@01c14000 {
status = "disabled";
};
ohci0: usb@01c14400 {
ohci0: usb@1c14400 {
compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
reg = <0x01c14400 0x100>;
interrupts = <40>;
......@@ -356,7 +356,7 @@ ohci0: usb@01c14400 {
status = "disabled";
};
crypto: crypto-engine@01c15000 {
crypto: crypto-engine@1c15000 {
compatible = "allwinner,sun5i-a13-crypto",
"allwinner,sun4i-a10-crypto";
reg = <0x01c15000 0x1000>;
......@@ -365,7 +365,7 @@ crypto: crypto-engine@01c15000 {
clock-names = "ahb", "mod";
};
spi2: spi@01c17000 {
spi2: spi@1c17000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c17000 0x1000>;
interrupts = <12>;
......@@ -379,7 +379,7 @@ spi2: spi@01c17000 {
#size-cells = <0>;
};
ccu: clock@01c20000 {
ccu: clock@1c20000 {
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&osc32k>;
clock-names = "hosc", "losc";
......@@ -387,14 +387,14 @@ ccu: clock@01c20000 {
#reset-cells = <1>;
};
intc: interrupt-controller@01c20400 {
intc: interrupt-controller@1c20400 {
compatible = "allwinner,sun4i-a10-ic";
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
};
pio: pinctrl@01c20800 {
pio: pinctrl@1c20800 {
reg = <0x01c20800 0x400>;
interrupts = <28>;
clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
......@@ -538,19 +538,19 @@ pwm0_pins: pwm0 {
};
};
timer@01c20c00 {
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0x90>;
interrupts = <22>;
clocks = <&ccu CLK_HOSC>;
};
wdt: watchdog@01c20c90 {
wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
};
ir0: ir@01c21800 {
ir0: ir@1c21800 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
clock-names = "apb", "ir";
......@@ -559,14 +559,14 @@ ir0: ir@01c21800 {
status = "disabled";
};
lradc: lradc@01c22800 {
lradc: lradc@1c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x100>;
interrupts = <31>;
status = "disabled";
};
codec: codec@01c22c00 {
codec: codec@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun4i-a10-codec";
reg = <0x01c22c00 0x40>;
......@@ -579,19 +579,19 @@ codec: codec@01c22c00 {
status = "disabled";
};
sid: eeprom@01c23800 {
sid: eeprom@1c23800 {
compatible = "allwinner,sun4i-a10-sid";
reg = <0x01c23800 0x10>;
};
rtp: rtp@01c25000 {
rtp: rtp@1c25000 {
compatible = "allwinner,sun5i-a13-ts";
reg = <0x01c25000 0x100>;
interrupts = <29>;
#thermal-sensor-cells = <0>;
};
uart0: serial@01c28000 {
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <1>;
......@@ -601,7 +601,7 @@ uart0: serial@01c28000 {
status = "disabled";
};
uart1: serial@01c28400 {
uart1: serial@1c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <2>;
......@@ -611,7 +611,7 @@ uart1: serial@01c28400 {
status = "disabled";
};
uart2: serial@01c28800 {
uart2: serial@1c28800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28800 0x400>;
interrupts = <3>;
......@@ -621,7 +621,7 @@ uart2: serial@01c28800 {
status = "disabled";
};
uart3: serial@01c28c00 {
uart3: serial@1c28c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>;
interrupts = <4>;
......@@ -631,7 +631,7 @@ uart3: serial@01c28c00 {
status = "disabled";
};
i2c0: i2c@01c2ac00 {
i2c0: i2c@1c2ac00 {
compatible = "allwinner,sun4i-a10-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <7>;
......@@ -641,7 +641,7 @@ i2c0: i2c@01c2ac00 {
#size-cells = <0>;
};
i2c1: i2c@01c2b000 {
i2c1: i2c@1c2b000 {
compatible = "allwinner,sun4i-a10-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <8>;
......@@ -651,7 +651,7 @@ i2c1: i2c@01c2b000 {
#size-cells = <0>;
};
i2c2: i2c@01c2b400 {
i2c2: i2c@1c2b400 {
compatible = "allwinner,sun4i-a10-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <9>;
......@@ -661,14 +661,14 @@ i2c2: i2c@01c2b400 {
#size-cells = <0>;
};
timer@01c60000 {
timer@1c60000 {
compatible = "allwinner,sun5i-a13-hstimer";
reg = <0x01c60000 0x1000>;
interrupts = <82>, <83>;
clocks = <&ccu CLK_AHB_HSTIMER>;
};
fe0: display-frontend@01e00000 {
fe0: display-frontend@1e00000 {
compatible = "allwinner,sun5i-a13-display-frontend";
reg = <0x01e00000 0x20000>;
interrupts = <47>;
......@@ -696,7 +696,7 @@ fe0_out_be0: endpoint@0 {
};
};
be0: display-backend@01e60000 {
be0: display-backend@1e60000 {
compatible = "allwinner,sun5i-a13-display-backend";
reg = <0x01e60000 0x10000>;
interrupts = <47>;
......
arch/arm/boot/dts/sun6i-a31.dtsi
View file @ 5841f6c0
This diff is collapsed.
arch/arm/boot/dts/sun7i-a20.dtsi
View file @ 5841f6c0
This diff is collapsed.
arch/arm/boot/dts/sun8i-a23-a33.dtsi
View file @ 5841f6c0
......@@ -118,13 +118,13 @@ ext_osc32k: ext_osc32k_clk {
};
};
soc@01c00000 {
soc@1c00000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
dma: dma-controller@01c02000 {
dma: dma-controller@1c02000 {
compatible = "allwinner,sun8i-a23-dma";
reg = <0x01c02000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
......@@ -133,7 +133,7 @@ dma: dma-controller@01c02000 {
#dma-cells = <1>;
};
mmc0: mmc@01c0f000 {
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ccu CLK_BUS_MMC0>,
......@@ -152,7 +152,7 @@ mmc0: mmc@01c0f000 {
#size-cells = <0>;
};
mmc1: mmc@01c10000 {
mmc1: mmc@1c10000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&ccu CLK_BUS_MMC1>,
......@@ -171,7 +171,7 @@ mmc1: mmc@01c10000 {
#size-cells = <0>;
};
mmc2: mmc@01c11000 {
mmc2: mmc@1c11000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c11000 0x1000>;
clocks = <&ccu CLK_BUS_MMC2>,
......@@ -190,7 +190,7 @@ mmc2: mmc@01c11000 {
#size-cells = <0>;
};
nfc: nand@01c03000 {
nfc: nand@1c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
......@@ -203,7 +203,7 @@ nfc: nand@01c03000 {
#size-cells = <0>;
};
usb_otg: usb@01c19000 {
usb_otg: usb@1c19000 {
/* compatible gets set in SoC specific dtsi file */
reg = <0x01c19000 0x0400>;
clocks = <&ccu CLK_BUS_OTG>;
......@@ -216,7 +216,7 @@ usb_otg: usb@01c19000 {
status = "disabled";
};
usbphy: phy@01c19400 {
usbphy: phy@1c19400 {
/*
* compatible and address regions get set in
* SoC specific dtsi file
......@@ -233,7 +233,7 @@ usbphy: phy@01c19400 {
#phy-cells = <1>;
};
ehci0: usb@01c1a000 {
ehci0: usb@1c1a000 {
compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
reg = <0x01c1a000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
......@@ -244,7 +244,7 @@ ehci0: usb@01c1a000 {
status = "disabled";
};
ohci0: usb@01c1a400 {
ohci0: usb@1c1a400 {
compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
reg = <0x01c1a400 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
......@@ -255,7 +255,7 @@ ohci0: usb@01c1a400 {
status = "disabled";
};
ccu: clock@01c20000 {
ccu: clock@1c20000 {
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&rtc 0>;
clock-names = "hosc", "losc";
......@@ -263,7 +263,7 @@ ccu: clock@01c20000 {
#reset-cells = <1>;
};
pio: pinctrl@01c20800 {
pio: pinctrl@1c20800 {
/* compatible gets set in SoC specific dtsi file */
reg = <0x01c20800 0x400>;
/* interrupts get set in SoC specific dtsi file */
......@@ -344,7 +344,7 @@ lcd_rgb666_pins: lcd-rgb666@0 {
};
};
timer@01c20c00 {
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
......@@ -352,13 +352,13 @@ timer@01c20c00 {
clocks = <&osc24M>;
};
wdt0: watchdog@01c20ca0 {
wdt0: watchdog@1c20ca0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
};
pwm: pwm@01c21400 {
pwm: pwm@1c21400 {
compatible = "allwinner,sun7i-a20-pwm";
reg = <0x01c21400 0xc>;
clocks = <&osc24M>;
......@@ -366,14 +366,14 @@ pwm: pwm@01c21400 {
status = "disabled";
};
lradc: lradc@01c22800 {
lradc: lradc@1c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x100>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart0: serial@01c28000 {
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
......@@ -386,7 +386,7 @@ uart0: serial@01c28000 {
status = "disabled";
};
uart1: serial@01c28400 {
uart1: serial@1c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
......@@ -399,7 +399,7 @@ uart1: serial@01c28400 {
status = "disabled";
};
uart2: serial@01c28800 {
uart2: serial@1c28800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28800 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
......@@ -412,7 +412,7 @@ uart2: serial@01c28800 {
status = "disabled";
};
uart3: serial@01c28c00 {
uart3: serial@1c28c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
......@@ -425,7 +425,7 @@ uart3: serial@01c28c00 {
status = "disabled";
};
uart4: serial@01c29000 {
uart4: serial@1c29000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29000 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
......@@ -438,7 +438,7 @@ uart4: serial@01c29000 {
status = "disabled";
};
i2c0: i2c@01c2ac00 {
i2c0: i2c@1c2ac00 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
......@@ -449,7 +449,7 @@ i2c0: i2c@01c2ac00 {
#size-cells = <0>;
};
i2c1: i2c@01c2b000 {
i2c1: i2c@1c2b000 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
......@@ -460,7 +460,7 @@ i2c1: i2c@01c2b000 {
#size-cells = <0>;
};
i2c2: i2c@01c2b400 {
i2c2: i2c@1c2b400 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
......@@ -498,7 +498,7 @@ mali: gpu@1c40000 {
assigned-clock-rates = <384000000>;
};
gic: interrupt-controller@01c81000 {
gic: interrupt-controller@1c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
<0x01c82000 0x2000>,
......@@ -509,7 +509,7 @@ gic: interrupt-controller@01c81000 {
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
rtc: rtc@01f00000 {
rtc: rtc@1f00000 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
......@@ -527,7 +527,7 @@ nmi_intc: interrupt-controller@1f00c00 {
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
prcm@01f01400 {
prcm@1f01400 {
compatible = "allwinner,sun8i-a23-prcm";
reg = <0x01f01400 0x200>;
......@@ -575,12 +575,12 @@ codec_analog: codec-analog {
};
};
cpucfg@01f01c00 {
cpucfg@1f01c00 {
compatible = "allwinner,sun8i-a23-cpuconfig";
reg = <0x01f01c00 0x300>;
};
r_uart: serial@01f02800 {
r_uart: serial@1f02800 {
compatible = "snps,dw-apb-uart";
reg = <0x01f02800 0x400>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
......@@ -591,7 +591,7 @@ r_uart: serial@01f02800 {
status = "disabled";
};
r_pio: pinctrl@01f02c00 {
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a23-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
......@@ -618,7 +618,7 @@ r_uart_pins_a: r_uart@0 {
};
};
r_rsb: rsb@01f03400 {
r_rsb: rsb@1f03400 {
compatible = "allwinner,sun8i-a23-rsb";
reg = <0x01f03400 0x400>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
......
arch/arm/boot/dts/sun8i-a23.dtsi
View file @ 5841f6c0
......@@ -49,8 +49,8 @@ memory {
reg = <0x40000000 0x40000000>;
};
soc@01c00000 {
codec: codec@01c22c00 {
soc@1c00000 {
codec: codec@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun8i-a23-codec";
reg = <0x01c22c00 0x400>;
......
arch/arm/boot/dts/sun8i-a33.dtsi
View file @ 5841f6c0
......@@ -203,8 +203,8 @@ link_codec: simple-audio-card,codec {
};
};
soc@01c00000 {
tcon0: lcd-controller@01c0c000 {
soc@1c00000 {
tcon0: lcd-controller@1c0c000 {
compatible = "allwinner,sun8i-a33-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
......@@ -240,7 +240,7 @@ tcon0_out: port@1 {
};
};
crypto: crypto-engine@01c15000 {
crypto: crypto-engine@1c15000 {
compatible = "allwinner,sun4i-a10-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
......@@ -250,7 +250,7 @@ crypto: crypto-engine@01c15000 {
reset-names = "ahb";
};
dai: dai@01c22c00 {
dai: dai@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun6i-a31-i2s";
reg = <0x01c22c00 0x200>;
......@@ -263,7 +263,7 @@ dai: dai@01c22c00 {
status = "disabled";
};
codec: codec@01c22e00 {
codec: codec@1c22e00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun8i-a33-codec";
reg = <0x01c22e00 0x400>;
......@@ -273,14 +273,14 @@ codec: codec@01c22e00 {
status = "disabled";
};
ths: ths@01c25000 {
ths: ths@1c25000 {
compatible = "allwinner,sun8i-a33-ths";
reg = <0x01c25000 0x100>;
#thermal-sensor-cells = <0>;
#io-channel-cells = <0>;
};
fe0: display-frontend@01e00000 {
fe0: display-frontend@1e00000 {
compatible = "allwinner,sun8i-a33-display-frontend";
reg = <0x01e00000 0x20000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
......@@ -308,7 +308,7 @@ fe0_out_be0: endpoint@0 {
};
};
be0: display-backend@01e60000 {
be0: display-backend@1e60000 {
compatible = "allwinner,sun8i-a33-display-backend";
reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
reg-names = "be", "sat";
......@@ -350,7 +350,7 @@ be0_out_drc0: endpoint@0 {
};
};
drc0: drc@01e70000 {
drc0: drc@1e70000 {
compatible = "allwinner,sun8i-a33-drc";
reg = <0x01e70000 0x10000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
......
arch/arm/boot/dts/sun8i-v3s.dtsi
View file @ 5841f6c0
......@@ -178,7 +178,7 @@ tcon0_out: port@1 {
};
mmc0: mmc@01c0f000 {
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ccu CLK_BUS_MMC0>,
......@@ -197,7 +197,7 @@ mmc0: mmc@01c0f000 {
#size-cells = <0>;
};
mmc1: mmc@01c10000 {
mmc1: mmc@1c10000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&ccu CLK_BUS_MMC1>,
......@@ -218,7 +218,7 @@ mmc1: mmc@01c10000 {
#size-cells = <0>;
};
mmc2: mmc@01c11000 {
mmc2: mmc@1c11000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c11000 0x1000>;
clocks = <&ccu CLK_BUS_MMC2>,
......@@ -237,7 +237,7 @@ mmc2: mmc@01c11000 {
#size-cells = <0>;
};
usb_otg: usb@01c19000 {
usb_otg: usb@1c19000 {
compatible = "allwinner,sun8i-h3-musb";
reg = <0x01c19000 0x0400>;
clocks = <&ccu CLK_BUS_OTG>;
......@@ -250,7 +250,7 @@ usb_otg: usb@01c19000 {
status = "disabled";
};
usbphy: phy@01c19400 {
usbphy: phy@1c19400 {
compatible = "allwinner,sun8i-v3s-usb-phy";
reg = <0x01c19400 0x2c>,
<0x01c1a800 0x4>;
......@@ -264,7 +264,7 @@ usbphy: phy@01c19400 {
#phy-cells = <1>;
};
ccu: clock@01c20000 {
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-v3s-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&osc32k>;
......@@ -273,14 +273,14 @@ ccu: clock@01c20000 {
#reset-cells = <1>;
};
rtc: rtc@01c20400 {
rtc: rtc@1c20400 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01c20400 0x54>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
pio: pinctrl@01c20800 {
pio: pinctrl@1c20800 {
compatible = "allwinner,sun8i-v3s-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
......@@ -324,7 +324,7 @@ spi0_pins: spi0 {
};
};
timer@01c20c00 {
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
......@@ -332,7 +332,7 @@ timer@01c20c00 {
clocks = <&osc24M>;
};
wdt0: watchdog@01c20ca0 {
wdt0: watchdog@1c20ca0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
......@@ -345,7 +345,7 @@ lradc: lradc@1c22800 {
status = "disabled";
};
uart0: serial@01c28000 {
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
......@@ -356,7 +356,7 @@ uart0: serial@01c28000 {
status = "disabled";
};
uart1: serial@01c28400 {
uart1: serial@1c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
......@@ -367,7 +367,7 @@ uart1: serial@01c28400 {
status = "disabled";
};
uart2: serial@01c28800 {
uart2: serial@1c28800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28800 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
......@@ -378,7 +378,7 @@ uart2: serial@01c28800 {
status = "disabled";
};
i2c0: i2c@01c2ac00 {
i2c0: i2c@1c2ac00 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
......@@ -391,7 +391,7 @@ i2c0: i2c@01c2ac00 {
#size-cells = <0>;
};
i2c1: i2c@01c2b000 {
i2c1: i2c@1c2b000 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
......@@ -416,7 +416,7 @@ spi0: spi@1c68000 {
#size-cells = <0>;
};
gic: interrupt-controller@01c81000 {
gic: interrupt-controller@1c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
<0x01c82000 0x1000>,
......
arch/arm/boot/dts/sun9i-a80.dtsi
View file @ 5841f6c0
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