Commit 5886fae1 authored by Jeff Garzik's avatar Jeff Garzik

[netdrvr ixgb] more cleanups

- support new 2.5 irqreturn_t
- s/usec_delay/udelay/
- remove two stored-but-never-used members of struct ixgb_hw
- read PCI vendor/device ids from struct pci_dev, not h/w
- remove some unused wrappers from ixgb_osdep.h
parent 9df5b0d8
...@@ -52,7 +52,7 @@ ixgb_raise_clock(struct ixgb_hw *hw, u32 * eecd_reg) ...@@ -52,7 +52,7 @@ ixgb_raise_clock(struct ixgb_hw *hw, u32 * eecd_reg)
*/ */
*eecd_reg = *eecd_reg | IXGB_EECD_SK; *eecd_reg = *eecd_reg | IXGB_EECD_SK;
IXGB_WRITE_REG(hw, EECD, *eecd_reg); IXGB_WRITE_REG(hw, EECD, *eecd_reg);
usec_delay(50); udelay(50);
return; return;
} }
...@@ -70,7 +70,7 @@ ixgb_lower_clock(struct ixgb_hw *hw, u32 * eecd_reg) ...@@ -70,7 +70,7 @@ ixgb_lower_clock(struct ixgb_hw *hw, u32 * eecd_reg)
*/ */
*eecd_reg = *eecd_reg & ~IXGB_EECD_SK; *eecd_reg = *eecd_reg & ~IXGB_EECD_SK;
IXGB_WRITE_REG(hw, EECD, *eecd_reg); IXGB_WRITE_REG(hw, EECD, *eecd_reg);
usec_delay(50); udelay(50);
return; return;
} }
...@@ -107,7 +107,7 @@ ixgb_shift_out_bits(struct ixgb_hw *hw, u16 data, u16 count) ...@@ -107,7 +107,7 @@ ixgb_shift_out_bits(struct ixgb_hw *hw, u16 data, u16 count)
IXGB_WRITE_REG(hw, EECD, eecd_reg); IXGB_WRITE_REG(hw, EECD, eecd_reg);
usec_delay(50); udelay(50);
ixgb_raise_clock(hw, &eecd_reg); ixgb_raise_clock(hw, &eecd_reg);
ixgb_lower_clock(hw, &eecd_reg); ixgb_lower_clock(hw, &eecd_reg);
...@@ -202,22 +202,22 @@ ixgb_standby_eeprom(struct ixgb_hw *hw) ...@@ -202,22 +202,22 @@ ixgb_standby_eeprom(struct ixgb_hw *hw)
/* Deselct EEPROM */ /* Deselct EEPROM */
eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_SK); eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_SK);
IXGB_WRITE_REG(hw, EECD, eecd_reg); IXGB_WRITE_REG(hw, EECD, eecd_reg);
usec_delay(50); udelay(50);
/* Clock high */ /* Clock high */
eecd_reg |= IXGB_EECD_SK; eecd_reg |= IXGB_EECD_SK;
IXGB_WRITE_REG(hw, EECD, eecd_reg); IXGB_WRITE_REG(hw, EECD, eecd_reg);
usec_delay(50); udelay(50);
/* Select EEPROM */ /* Select EEPROM */
eecd_reg |= IXGB_EECD_CS; eecd_reg |= IXGB_EECD_CS;
IXGB_WRITE_REG(hw, EECD, eecd_reg); IXGB_WRITE_REG(hw, EECD, eecd_reg);
usec_delay(50); udelay(50);
/* Clock low */ /* Clock low */
eecd_reg &= ~IXGB_EECD_SK; eecd_reg &= ~IXGB_EECD_SK;
IXGB_WRITE_REG(hw, EECD, eecd_reg); IXGB_WRITE_REG(hw, EECD, eecd_reg);
usec_delay(50); udelay(50);
return; return;
} }
...@@ -236,12 +236,12 @@ ixgb_clock_eeprom(struct ixgb_hw *hw) ...@@ -236,12 +236,12 @@ ixgb_clock_eeprom(struct ixgb_hw *hw)
/* Rising edge of clock */ /* Rising edge of clock */
eecd_reg |= IXGB_EECD_SK; eecd_reg |= IXGB_EECD_SK;
IXGB_WRITE_REG(hw, EECD, eecd_reg); IXGB_WRITE_REG(hw, EECD, eecd_reg);
usec_delay(50); udelay(50);
/* Falling edge of clock */ /* Falling edge of clock */
eecd_reg &= ~IXGB_EECD_SK; eecd_reg &= ~IXGB_EECD_SK;
IXGB_WRITE_REG(hw, EECD, eecd_reg); IXGB_WRITE_REG(hw, EECD, eecd_reg);
usec_delay(50); udelay(50);
return; return;
} }
...@@ -297,7 +297,7 @@ ixgb_wait_eeprom_command(struct ixgb_hw *hw) ...@@ -297,7 +297,7 @@ ixgb_wait_eeprom_command(struct ixgb_hw *hw)
if (eecd_reg & IXGB_EECD_DO) if (eecd_reg & IXGB_EECD_DO)
return (TRUE); return (TRUE);
usec_delay(50); udelay(50);
} }
ASSERT(0); ASSERT(0);
return (FALSE); return (FALSE);
......
...@@ -636,7 +636,7 @@ ixgb_read_phy_reg(struct ixgb_hw * hw, ...@@ -636,7 +636,7 @@ ixgb_read_phy_reg(struct ixgb_hw * hw,
**************************************************************/ **************************************************************/
for (i = 0; i < 10; i++) { for (i = 0; i < 10; i++) {
usec_delay(10); udelay(10);
command = IXGB_READ_REG(hw, MSCA); command = IXGB_READ_REG(hw, MSCA);
...@@ -662,7 +662,7 @@ ixgb_read_phy_reg(struct ixgb_hw * hw, ...@@ -662,7 +662,7 @@ ixgb_read_phy_reg(struct ixgb_hw * hw,
**************************************************************/ **************************************************************/
for (i = 0; i < 10; i++) { for (i = 0; i < 10; i++) {
usec_delay(10); udelay(10);
command = IXGB_READ_REG(hw, MSCA); command = IXGB_READ_REG(hw, MSCA);
...@@ -727,7 +727,7 @@ ixgb_write_phy_reg(struct ixgb_hw *hw, ...@@ -727,7 +727,7 @@ ixgb_write_phy_reg(struct ixgb_hw *hw,
**************************************************************/ **************************************************************/
for (i = 0; i < 10; i++) { for (i = 0; i < 10; i++) {
usec_delay(10); udelay(10);
command = IXGB_READ_REG(hw, MSCA); command = IXGB_READ_REG(hw, MSCA);
...@@ -753,7 +753,7 @@ ixgb_write_phy_reg(struct ixgb_hw *hw, ...@@ -753,7 +753,7 @@ ixgb_write_phy_reg(struct ixgb_hw *hw,
**************************************************************/ **************************************************************/
for (i = 0; i < 10; i++) { for (i = 0; i < 10; i++) {
usec_delay(10); udelay(10);
command = IXGB_READ_REG(hw, MSCA); command = IXGB_READ_REG(hw, MSCA);
...@@ -1024,7 +1024,7 @@ ixgb_link_reset(struct ixgb_hw * hw) ...@@ -1024,7 +1024,7 @@ ixgb_link_reset(struct ixgb_hw * hw)
IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST); IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
do { do {
usec_delay(IXGB_DELAY_USECS_AFTER_LINK_RESET); udelay(IXGB_DELAY_USECS_AFTER_LINK_RESET);
link_status = link_status =
((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU) ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU)
&& (IXGB_READ_REG(hw, XPCSS) & && (IXGB_READ_REG(hw, XPCSS) &
......
...@@ -498,10 +498,8 @@ struct ixgb_hw { ...@@ -498,10 +498,8 @@ struct ixgb_hw {
boolean_t adapter_stopped; /* State of adapter */ boolean_t adapter_stopped; /* State of adapter */
u16 device_id; /* device id from PCI configuration space */ u16 device_id; /* device id from PCI configuration space */
u16 vendor_id; /* vendor id from PCI configuration space */ u16 vendor_id; /* vendor id from PCI configuration space */
u8 revision_id; /* revision id from PCI configuration space */
u16 subsystem_vendor_id; /* subsystem vendor id from PCI configuration space */ u16 subsystem_vendor_id; /* subsystem vendor id from PCI configuration space */
u16 subsystem_id; /* subsystem id from PCI configuration space */ u16 subsystem_id; /* subsystem id from PCI configuration space */
u16 pci_cmd_word; /* PCI command register id from PCI configuration space */
u16 eeprom[IXGB_EEPROM_SIZE]; /* EEPROM contents read at init time */ u16 eeprom[IXGB_EEPROM_SIZE]; /* EEPROM contents read at init time */
uint64_t io_base; /* Our I/O mapped location */ uint64_t io_base; /* Our I/O mapped location */
u32 lastLFC; u32 lastLFC;
......
...@@ -31,7 +31,7 @@ ...@@ -31,7 +31,7 @@
char ixgb_driver_name[] = "ixgb"; char ixgb_driver_name[] = "ixgb";
char ixgb_driver_string[] = "Intel(R) PRO/10GbE Network Driver"; char ixgb_driver_string[] = "Intel(R) PRO/10GbE Network Driver";
char ixgb_driver_version[] = "1.0.47-k1"; char ixgb_driver_version[] = "1.0.47-k1jg";
char ixgb_copyright[] = "Copyright (c) 2001-2003 Intel Corporation."; char ixgb_copyright[] = "Copyright (c) 2001-2003 Intel Corporation.";
/* ixgb_pci_tbl - PCI Device ID Table /* ixgb_pci_tbl - PCI Device ID Table
...@@ -104,7 +104,7 @@ static int ixgb_set_mac(struct net_device *netdev, void *p); ...@@ -104,7 +104,7 @@ static int ixgb_set_mac(struct net_device *netdev, void *p);
static void ixgb_update_stats(struct ixgb_adapter *adapter); static void ixgb_update_stats(struct ixgb_adapter *adapter);
static inline void ixgb_irq_disable(struct ixgb_adapter *adapter); static inline void ixgb_irq_disable(struct ixgb_adapter *adapter);
static inline void ixgb_irq_enable(struct ixgb_adapter *adapter); static inline void ixgb_irq_enable(struct ixgb_adapter *adapter);
static void ixgb_intr(int irq, void *data, struct pt_regs *regs); static irqreturn_t ixgb_intr(int irq, void *data, struct pt_regs *regs);
static void ixgb_clean_tx_irq(struct ixgb_adapter *adapter); static void ixgb_clean_tx_irq(struct ixgb_adapter *adapter);
#ifdef CONFIG_IXGB_NAPI #ifdef CONFIG_IXGB_NAPI
static int ixgb_poll(struct net_device *netdev, int *budget); static int ixgb_poll(struct net_device *netdev, int *budget);
...@@ -500,13 +500,13 @@ ixgb_sw_init(struct ixgb_adapter *adapter) ...@@ -500,13 +500,13 @@ ixgb_sw_init(struct ixgb_adapter *adapter)
/* PCI config space info */ /* PCI config space info */
pci_read_config_word(pdev, PCI_VENDOR_ID, &hw->vendor_id); /* FIXME: do not store, instead directly use struct pci_dev
pci_read_config_word(pdev, PCI_DEVICE_ID, &hw->device_id); * where needed
pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id); */
pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, hw->vendor_id = pdev->vendor;
&hw->subsystem_vendor_id); hw->device_id = pdev->device;
pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); hw->subsystem_vendor_id = pdev->subsystem_vendor;
pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); hw->subsystem_id = pdev->subsystem_device;
adapter->rx_buffer_len = IXGB_RXBUFFER_2048; adapter->rx_buffer_len = IXGB_RXBUFFER_2048;
...@@ -1715,7 +1715,7 @@ ixgb_irq_enable(struct ixgb_adapter *adapter) ...@@ -1715,7 +1715,7 @@ ixgb_irq_enable(struct ixgb_adapter *adapter)
* @param regs CPU registers structure * @param regs CPU registers structure
**/ **/
static void static irqreturn_t
ixgb_intr(int irq, void *data, struct pt_regs *regs) ixgb_intr(int irq, void *data, struct pt_regs *regs)
{ {
struct net_device *netdev = (struct net_device *) data; struct net_device *netdev = (struct net_device *) data;
...@@ -1725,13 +1725,18 @@ ixgb_intr(int irq, void *data, struct pt_regs *regs) ...@@ -1725,13 +1725,18 @@ ixgb_intr(int irq, void *data, struct pt_regs *regs)
ixgb_irq_disable(adapter); ixgb_irq_disable(adapter);
__netif_rx_schedule(netdev); __netif_rx_schedule(netdev);
} }
return IRQ_HANDLED; /* FIXME: check for shared interrupts */
#else #else
struct ixgb_hw *hw = &adapter->hw; struct ixgb_hw *hw = &adapter->hw;
u32 icr; u32 icr;
uint i = IXGB_MAX_INTR; uint i = IXGB_MAX_INTR;
boolean_t rxdmt0 = FALSE; boolean_t rxdmt0 = FALSE;
int handled = 0;
while (i && (icr = IXGB_READ_REG(hw, ICR))) { while (i && (icr = IXGB_READ_REG(hw, ICR))) {
handled = 1;
if (icr & IXGB_INT_RXDMT0) if (icr & IXGB_INT_RXDMT0)
rxdmt0 = TRUE; rxdmt0 = TRUE;
...@@ -1755,6 +1760,8 @@ ixgb_intr(int irq, void *data, struct pt_regs *regs) ...@@ -1755,6 +1760,8 @@ ixgb_intr(int irq, void *data, struct pt_regs *regs)
/* now restart it, h/w will decide if its necessary */ /* now restart it, h/w will decide if its necessary */
IXGB_WRITE_REG(hw, IMS, IXGB_INT_RXDMT0); IXGB_WRITE_REG(hw, IMS, IXGB_INT_RXDMT0);
} }
return IRQ_RETVAL(handled);
#endif // NAPI else #endif // NAPI else
} }
......
...@@ -39,7 +39,7 @@ ...@@ -39,7 +39,7 @@
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/sched.h> #include <linux/sched.h>
#define usec_delay(x) udelay(x) /* FIXME: eliminate me */
#define msec_delay(x) do { if(in_interrupt()) { \ #define msec_delay(x) do { if(in_interrupt()) { \
mdelay(x); \ mdelay(x); \
} else { \ } else { \
...@@ -47,9 +47,6 @@ ...@@ -47,9 +47,6 @@
schedule_timeout((x * HZ)/1000); \ schedule_timeout((x * HZ)/1000); \
} } while(0) } } while(0)
#define PCI_COMMAND_REGISTER PCI_COMMAND
#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
typedef enum { typedef enum {
FALSE = 0, FALSE = 0,
TRUE = 1 TRUE = 1
...@@ -84,6 +81,4 @@ typedef enum { ...@@ -84,6 +81,4 @@ typedef enum {
#define IXGB_READ_REG_ARRAY(a, reg, offset) ( \ #define IXGB_READ_REG_ARRAY(a, reg, offset) ( \
readl((a)->hw_addr + IXGB_##reg + ((offset) << 2))) readl((a)->hw_addr + IXGB_##reg + ((offset) << 2)))
#define IXGB_MEMCPY memcpy
#endif /* IXGB_OSDEP_H */ #endif /* IXGB_OSDEP_H */
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