Commit 59156faf authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher

drm/amd/pp: Remove the cgs wrapper for notify smu version on APU

Refine commit f49e9bac ("drm/amd/pp: Get and save Rv smu version")
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6f4969ef
...@@ -654,11 +654,6 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, ...@@ -654,11 +654,6 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
else else
strcpy(fw_name, "amdgpu/vega10_smc.bin"); strcpy(fw_name, "amdgpu/vega10_smc.bin");
break; break;
case CHIP_CARRIZO:
case CHIP_STONEY:
case CHIP_RAVEN:
adev->pm.fw_version = info->version;
return 0;
default: default:
DRM_ERROR("SMC firmware not supported\n"); DRM_ERROR("SMC firmware not supported\n");
return -EINVAL; return -EINVAL;
......
...@@ -247,13 +247,11 @@ static int smu10_smu_fini(struct pp_hwmgr *hwmgr) ...@@ -247,13 +247,11 @@ static int smu10_smu_fini(struct pp_hwmgr *hwmgr)
static int smu10_start_smu(struct pp_hwmgr *hwmgr) static int smu10_start_smu(struct pp_hwmgr *hwmgr)
{ {
struct cgs_firmware_info info = {0}; struct amdgpu_device *adev = hwmgr->adev;
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
hwmgr->smu_version = smu10_read_arg_from_smc(hwmgr); hwmgr->smu_version = smu10_read_arg_from_smc(hwmgr);
info.version = hwmgr->smu_version >> 8; adev->pm.fw_version = hwmgr->smu_version >> 8;
cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
if (smu10_verify_smc_interface(hwmgr)) if (smu10_verify_smc_interface(hwmgr))
return -EINVAL; return -EINVAL;
......
...@@ -698,7 +698,8 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr) ...@@ -698,7 +698,8 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr)
{ {
int ret = 0; int ret = 0;
uint32_t fw_to_check = 0; uint32_t fw_to_check = 0;
struct cgs_firmware_info info = {0}; struct amdgpu_device *adev = hwmgr->adev;
uint32_t index = SMN_MP1_SRAM_START_ADDR + uint32_t index = SMN_MP1_SRAM_START_ADDR +
SMU8_FIRMWARE_HEADER_LOCATION + SMU8_FIRMWARE_HEADER_LOCATION +
offsetof(struct SMU8_Firmware_Header, Version); offsetof(struct SMU8_Firmware_Header, Version);
...@@ -709,8 +710,7 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr) ...@@ -709,8 +710,7 @@ static int smu8_start_smu(struct pp_hwmgr *hwmgr)
cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index); cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
hwmgr->smu_version = cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA); hwmgr->smu_version = cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA);
info.version = hwmgr->smu_version >> 8; adev->pm.fw_version = hwmgr->smu_version >> 8;
cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
fw_to_check = UCODE_ID_RLC_G_MASK | fw_to_check = UCODE_ID_RLC_G_MASK |
UCODE_ID_SDMA0_MASK | UCODE_ID_SDMA0_MASK |
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment