Commit 5a412ad7 authored by David S. Miller's avatar David S. Miller

Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/jkirsher/net-next-2.6

parents 301102cc 6716344c
...@@ -1512,7 +1512,7 @@ static int e100_phy_init(struct nic *nic) ...@@ -1512,7 +1512,7 @@ static int e100_phy_init(struct nic *nic)
static int e100_hw_init(struct nic *nic) static int e100_hw_init(struct nic *nic)
{ {
int err; int err = 0;
e100_hw_reset(nic); e100_hw_reset(nic);
......
...@@ -244,6 +244,14 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw) ...@@ -244,6 +244,14 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
*/ */
size += NVM_WORD_SIZE_BASE_SHIFT; size += NVM_WORD_SIZE_BASE_SHIFT;
/*
* Check for invalid size
*/
if ((hw->mac.type == e1000_82576) && (size > 15)) {
printk("igb: The NVM size is not valid, "
"defaulting to 32K.\n");
size = 15;
}
nvm->word_size = 1 << size; nvm->word_size = 1 << size;
if (nvm->word_size == (1 << 15)) if (nvm->word_size == (1 << 15))
nvm->page_size = 128; nvm->page_size = 128;
......
...@@ -391,11 +391,6 @@ static int igbvf_set_wol(struct net_device *netdev, ...@@ -391,11 +391,6 @@ static int igbvf_set_wol(struct net_device *netdev,
return -EOPNOTSUPP; return -EOPNOTSUPP;
} }
static int igbvf_phys_id(struct net_device *netdev, u32 data)
{
return 0;
}
static int igbvf_get_coalesce(struct net_device *netdev, static int igbvf_get_coalesce(struct net_device *netdev,
struct ethtool_coalesce *ec) struct ethtool_coalesce *ec)
{ {
...@@ -527,7 +522,6 @@ static const struct ethtool_ops igbvf_ethtool_ops = { ...@@ -527,7 +522,6 @@ static const struct ethtool_ops igbvf_ethtool_ops = {
.self_test = igbvf_diag_test, .self_test = igbvf_diag_test,
.get_sset_count = igbvf_get_sset_count, .get_sset_count = igbvf_get_sset_count,
.get_strings = igbvf_get_strings, .get_strings = igbvf_get_strings,
.phys_id = igbvf_phys_id,
.get_ethtool_stats = igbvf_get_ethtool_stats, .get_ethtool_stats = igbvf_get_ethtool_stats,
.get_coalesce = igbvf_get_coalesce, .get_coalesce = igbvf_get_coalesce,
.set_coalesce = igbvf_set_coalesce, .set_coalesce = igbvf_set_coalesce,
......
...@@ -157,9 +157,6 @@ struct ixgb_adapter { ...@@ -157,9 +157,6 @@ struct ixgb_adapter {
u16 link_duplex; u16 link_duplex;
struct work_struct tx_timeout_task; struct work_struct tx_timeout_task;
struct timer_list blink_timer;
unsigned long led_status;
/* TX */ /* TX */
struct ixgb_desc_ring tx_ring ____cacheline_aligned_in_smp; struct ixgb_desc_ring tx_ring ____cacheline_aligned_in_smp;
unsigned int restart_queue; unsigned int restart_queue;
......
...@@ -611,45 +611,23 @@ ixgb_set_ringparam(struct net_device *netdev, ...@@ -611,45 +611,23 @@ ixgb_set_ringparam(struct net_device *netdev,
return err; return err;
} }
/* toggle LED 4 times per second = 2 "blinks" per second */
#define IXGB_ID_INTERVAL (HZ/4)
/* bit defines for adapter->led_status */
#define IXGB_LED_ON 0
static void
ixgb_led_blink_callback(unsigned long data)
{
struct ixgb_adapter *adapter = (struct ixgb_adapter *)data;
if (test_and_change_bit(IXGB_LED_ON, &adapter->led_status))
ixgb_led_off(&adapter->hw);
else
ixgb_led_on(&adapter->hw);
mod_timer(&adapter->blink_timer, jiffies + IXGB_ID_INTERVAL);
}
static int static int
ixgb_phys_id(struct net_device *netdev, u32 data) ixgb_set_phys_id(struct net_device *netdev, enum ethtool_phys_id_state state)
{ {
struct ixgb_adapter *adapter = netdev_priv(netdev); struct ixgb_adapter *adapter = netdev_priv(netdev);
if (!data) switch (state) {
data = INT_MAX; case ETHTOOL_ID_ACTIVE:
return 2;
if (!adapter->blink_timer.function) {
init_timer(&adapter->blink_timer);
adapter->blink_timer.function = ixgb_led_blink_callback;
adapter->blink_timer.data = (unsigned long)adapter;
}
mod_timer(&adapter->blink_timer, jiffies); case ETHTOOL_ID_ON:
ixgb_led_on(&adapter->hw);
break;
msleep_interruptible(data * 1000); case ETHTOOL_ID_OFF:
del_timer_sync(&adapter->blink_timer); case ETHTOOL_ID_INACTIVE:
ixgb_led_off(&adapter->hw); ixgb_led_off(&adapter->hw);
clear_bit(IXGB_LED_ON, &adapter->led_status); }
return 0; return 0;
} }
...@@ -767,7 +745,7 @@ static const struct ethtool_ops ixgb_ethtool_ops = { ...@@ -767,7 +745,7 @@ static const struct ethtool_ops ixgb_ethtool_ops = {
.set_msglevel = ixgb_set_msglevel, .set_msglevel = ixgb_set_msglevel,
.set_tso = ixgb_set_tso, .set_tso = ixgb_set_tso,
.get_strings = ixgb_get_strings, .get_strings = ixgb_get_strings,
.phys_id = ixgb_phys_id, .set_phys_id = ixgb_set_phys_id,
.get_sset_count = ixgb_get_sset_count, .get_sset_count = ixgb_get_sset_count,
.get_ethtool_stats = ixgb_get_ethtool_stats, .get_ethtool_stats = ixgb_get_ethtool_stats,
.get_flags = ethtool_op_get_flags, .get_flags = ethtool_op_get_flags,
......
...@@ -1281,6 +1281,7 @@ static struct ixgbe_mac_operations mac_ops_82598 = { ...@@ -1281,6 +1281,7 @@ static struct ixgbe_mac_operations mac_ops_82598 = {
static struct ixgbe_eeprom_operations eeprom_ops_82598 = { static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
.init_params = &ixgbe_init_eeprom_params_generic, .init_params = &ixgbe_init_eeprom_params_generic,
.read = &ixgbe_read_eerd_generic, .read = &ixgbe_read_eerd_generic,
.read_buffer = &ixgbe_read_eerd_buffer_generic,
.calc_checksum = &ixgbe_calc_eeprom_checksum_generic, .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
.validate_checksum = &ixgbe_validate_eeprom_checksum_generic, .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
.update_checksum = &ixgbe_update_eeprom_checksum_generic, .update_checksum = &ixgbe_update_eeprom_checksum_generic,
......
...@@ -110,7 +110,6 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) ...@@ -110,7 +110,6 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
&data_offset); &data_offset);
if (ret_val != 0) if (ret_val != 0)
goto setup_sfp_out; goto setup_sfp_out;
...@@ -130,7 +129,7 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) ...@@ -130,7 +129,7 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
} }
/* Release the semaphore */ /* Release the semaphore */
ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
/* /*
* Delay obtaining semaphore again to allow FW access, * Delay obtaining semaphore again to allow FW access,
* semaphore_delay is in ms usleep_range needs us. * semaphore_delay is in ms usleep_range needs us.
...@@ -2064,6 +2063,39 @@ static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) ...@@ -2064,6 +2063,39 @@ static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
return lesm_enabled; return lesm_enabled;
} }
/**
* ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
* fastest available method
*
* @hw: pointer to hardware structure
* @offset: offset of word in EEPROM to read
* @words: number of words
* @data: word(s) read from the EEPROM
*
* Retrieves 16 bit word(s) read from EEPROM
**/
static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
u16 words, u16 *data)
{
struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
s32 ret_val = IXGBE_ERR_CONFIG;
/*
* If EEPROM is detected and can be addressed using 14 bits,
* use EERD otherwise use bit bang
*/
if ((eeprom->type == ixgbe_eeprom_spi) &&
(offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
data);
else
ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
words,
data);
return ret_val;
}
/** /**
* ixgbe_read_eeprom_82599 - Read EEPROM word using * ixgbe_read_eeprom_82599 - Read EEPROM word using
* fastest available method * fastest available method
...@@ -2140,7 +2172,9 @@ static struct ixgbe_mac_operations mac_ops_82599 = { ...@@ -2140,7 +2172,9 @@ static struct ixgbe_mac_operations mac_ops_82599 = {
static struct ixgbe_eeprom_operations eeprom_ops_82599 = { static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
.init_params = &ixgbe_init_eeprom_params_generic, .init_params = &ixgbe_init_eeprom_params_generic,
.read = &ixgbe_read_eeprom_82599, .read = &ixgbe_read_eeprom_82599,
.read_buffer = &ixgbe_read_eeprom_buffer_82599,
.write = &ixgbe_write_eeprom_generic, .write = &ixgbe_write_eeprom_generic,
.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
.calc_checksum = &ixgbe_calc_eeprom_checksum_generic, .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
.validate_checksum = &ixgbe_validate_eeprom_checksum_generic, .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
.update_checksum = &ixgbe_update_eeprom_checksum_generic, .update_checksum = &ixgbe_update_eeprom_checksum_generic,
......
This diff is collapsed.
...@@ -49,10 +49,18 @@ s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index); ...@@ -49,10 +49,18 @@ s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw); s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data); s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
u16 words, u16 *data);
s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data); s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
u16 words, u16 *data);
s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data); s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
u16 words, u16 *data);
s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
u16 *data); u16 *data);
s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
u16 words, u16 *data);
u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw); u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);
s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
u16 *checksum_val); u16 *checksum_val);
......
...@@ -847,11 +847,8 @@ static int ixgbe_get_eeprom(struct net_device *netdev, ...@@ -847,11 +847,8 @@ static int ixgbe_get_eeprom(struct net_device *netdev,
if (!eeprom_buff) if (!eeprom_buff)
return -ENOMEM; return -ENOMEM;
for (i = 0; i < eeprom_len; i++) { ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
if ((ret_val = hw->eeprom.ops.read(hw, first_word + i, eeprom_buff);
&eeprom_buff[i])))
break;
}
/* Device's eeprom is always little-endian, word addressable */ /* Device's eeprom is always little-endian, word addressable */
for (i = 0; i < eeprom_len; i++) for (i = 0; i < eeprom_len; i++)
...@@ -1236,45 +1233,61 @@ static const struct ixgbe_reg_test reg_test_82598[] = { ...@@ -1236,45 +1233,61 @@ static const struct ixgbe_reg_test reg_test_82598[] = {
{ 0, 0, 0, 0 } { 0, 0, 0, 0 }
}; };
static const u32 register_test_patterns[] = { static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF u32 mask, u32 write)
}; {
u32 pat, val, before;
static const u32 test_pattern[] = {
0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
before = readl(adapter->hw.hw_addr + reg);
writel((test_pattern[pat] & write),
(adapter->hw.hw_addr + reg));
val = readl(adapter->hw.hw_addr + reg);
if (val != (test_pattern[pat] & write & mask)) {
e_err(drv, "pattern test reg %04X failed: got "
"0x%08X expected 0x%08X\n",
reg, val, (test_pattern[pat] & write & mask));
*data = reg;
writel(before, adapter->hw.hw_addr + reg);
return 1;
}
writel(before, adapter->hw.hw_addr + reg);
}
return 0;
}
#define REG_PATTERN_TEST(R, M, W) \ static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
{ \ u32 mask, u32 write)
u32 pat, val, before; \ {
for (pat = 0; pat < ARRAY_SIZE(register_test_patterns); pat++) { \ u32 val, before;
before = readl(adapter->hw.hw_addr + R); \ before = readl(adapter->hw.hw_addr + reg);
writel((register_test_patterns[pat] & W), \ writel((write & mask), (adapter->hw.hw_addr + reg));
(adapter->hw.hw_addr + R)); \ val = readl(adapter->hw.hw_addr + reg);
val = readl(adapter->hw.hw_addr + R); \ if ((write & mask) != (val & mask)) {
if (val != (register_test_patterns[pat] & W & M)) { \ e_err(drv, "set/check reg %04X test failed: got 0x%08X "
e_err(drv, "pattern test reg %04X failed: got " \ "expected 0x%08X\n", reg, (val & mask), (write & mask));
"0x%08X expected 0x%08X\n", \ *data = reg;
R, val, (register_test_patterns[pat] & W & M)); \ writel(before, (adapter->hw.hw_addr + reg));
*data = R; \ return 1;
writel(before, adapter->hw.hw_addr + R); \ }
return 1; \ writel(before, (adapter->hw.hw_addr + reg));
} \ return 0;
writel(before, adapter->hw.hw_addr + R); \
} \
} }
#define REG_SET_AND_CHECK(R, M, W) \ #define REG_PATTERN_TEST(reg, mask, write) \
{ \ do { \
u32 val, before; \ if (reg_pattern_test(adapter, data, reg, mask, write)) \
before = readl(adapter->hw.hw_addr + R); \
writel((W & M), (adapter->hw.hw_addr + R)); \
val = readl(adapter->hw.hw_addr + R); \
if ((W & M) != (val & M)) { \
e_err(drv, "set/check reg %04X test failed: got 0x%08X " \
"expected 0x%08X\n", R, (val & M), (W & M)); \
*data = R; \
writel(before, (adapter->hw.hw_addr + R)); \
return 1; \ return 1; \
} \ } while (0) \
writel(before, (adapter->hw.hw_addr + R)); \
}
#define REG_SET_AND_CHECK(reg, mask, write) \
do { \
if (reg_set_and_check(adapter, data, reg, mask, write)) \
return 1; \
} while (0) \
static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
{ {
......
...@@ -3862,9 +3862,10 @@ static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) ...@@ -3862,9 +3862,10 @@ static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
gpie |= IXGBE_SDP1_GPIEN; gpie |= IXGBE_SDP1_GPIEN;
if (hw->mac.type == ixgbe_mac_82599EB) if (hw->mac.type == ixgbe_mac_82599EB) {
gpie |= IXGBE_SDP1_GPIEN; gpie |= IXGBE_SDP1_GPIEN;
gpie |= IXGBE_SDP2_GPIEN; gpie |= IXGBE_SDP2_GPIEN;
}
IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
} }
...@@ -7468,8 +7469,8 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev, ...@@ -7468,8 +7469,8 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
/* print bus type/speed/width info */ /* print bus type/speed/width info */
e_dev_info("(PCI Express:%s:%s) %pM\n", e_dev_info("(PCI Express:%s:%s) %pM\n",
(hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" : (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" : hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
"Unknown"), "Unknown"),
(hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" : (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" : hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
......
...@@ -1222,7 +1222,7 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, ...@@ -1222,7 +1222,7 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
swfw_mask = IXGBE_GSSR_PHY0_SM; swfw_mask = IXGBE_GSSR_PHY0_SM;
do { do {
if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != 0) { if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
status = IXGBE_ERR_SWFW_SYNC; status = IXGBE_ERR_SWFW_SYNC;
goto read_byte_out; goto read_byte_out;
} }
...@@ -1269,7 +1269,7 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, ...@@ -1269,7 +1269,7 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
break; break;
fail: fail:
ixgbe_release_swfw_sync(hw, swfw_mask); hw->mac.ops.release_swfw_sync(hw, swfw_mask);
msleep(100); msleep(100);
ixgbe_i2c_bus_clear(hw); ixgbe_i2c_bus_clear(hw);
retry++; retry++;
...@@ -1280,7 +1280,7 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, ...@@ -1280,7 +1280,7 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
} while (retry < max_retry); } while (retry < max_retry);
ixgbe_release_swfw_sync(hw, swfw_mask); hw->mac.ops.release_swfw_sync(hw, swfw_mask);
read_byte_out: read_byte_out:
return status; return status;
...@@ -1308,7 +1308,7 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, ...@@ -1308,7 +1308,7 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
else else
swfw_mask = IXGBE_GSSR_PHY0_SM; swfw_mask = IXGBE_GSSR_PHY0_SM;
if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != 0) { if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
status = IXGBE_ERR_SWFW_SYNC; status = IXGBE_ERR_SWFW_SYNC;
goto write_byte_out; goto write_byte_out;
} }
...@@ -1352,7 +1352,7 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, ...@@ -1352,7 +1352,7 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
hw_dbg(hw, "I2C byte write error.\n"); hw_dbg(hw, "I2C byte write error.\n");
} while (retry < max_retry); } while (retry < max_retry);
ixgbe_release_swfw_sync(hw, swfw_mask); hw->mac.ops.release_swfw_sync(hw, swfw_mask);
write_byte_out: write_byte_out:
return status; return status;
......
...@@ -1668,6 +1668,10 @@ ...@@ -1668,6 +1668,10 @@
#define IXGBE_ETH_LENGTH_OF_ADDRESS 6 #define IXGBE_ETH_LENGTH_OF_ADDRESS 6
#define IXGBE_EEPROM_PAGE_SIZE_MAX 128
#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */
#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */
#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
#endif #endif
...@@ -2563,7 +2567,9 @@ typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr, ...@@ -2563,7 +2567,9 @@ typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
struct ixgbe_eeprom_operations { struct ixgbe_eeprom_operations {
s32 (*init_params)(struct ixgbe_hw *); s32 (*init_params)(struct ixgbe_hw *);
s32 (*read)(struct ixgbe_hw *, u16, u16 *); s32 (*read)(struct ixgbe_hw *, u16, u16 *);
s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
s32 (*write)(struct ixgbe_hw *, u16, u16); s32 (*write)(struct ixgbe_hw *, u16, u16);
s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
s32 (*validate_checksum)(struct ixgbe_hw *, u16 *); s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
s32 (*update_checksum)(struct ixgbe_hw *); s32 (*update_checksum)(struct ixgbe_hw *);
u16 (*calc_checksum)(struct ixgbe_hw *); u16 (*calc_checksum)(struct ixgbe_hw *);
...@@ -2649,6 +2655,7 @@ struct ixgbe_eeprom_info { ...@@ -2649,6 +2655,7 @@ struct ixgbe_eeprom_info {
u32 semaphore_delay; u32 semaphore_delay;
u16 word_size; u16 word_size;
u16 address_bits; u16 address_bits;
u16 word_page_size;
}; };
#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01 #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
......
...@@ -304,21 +304,49 @@ static s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) ...@@ -304,21 +304,49 @@ static s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
} }
/** /**
* ixgbe_read_eerd_X540 - Read EEPROM word using EERD * ixgbe_read_eerd_X540- Read EEPROM word using EERD
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* @offset: offset of word in the EEPROM to read * @offset: offset of word in the EEPROM to read
* @data: word read from the EERPOM * @data: word read from the EEPROM
*
* Reads a 16 bit word from the EEPROM using the EERD register.
**/ **/
static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
{ {
s32 status; s32 status = 0;
if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
0)
status = ixgbe_read_eerd_generic(hw, offset, data); status = ixgbe_read_eerd_generic(hw, offset, data);
else else
status = IXGBE_ERR_SWFW_SYNC; status = IXGBE_ERR_SWFW_SYNC;
ixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM); hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
return status;
}
/**
* ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
* @hw: pointer to hardware structure
* @offset: offset of word in the EEPROM to read
* @words: number of words
* @data: word(s) read from the EEPROM
*
* Reads a 16 bit word(s) from the EEPROM using the EERD register.
**/
static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
u16 offset, u16 words, u16 *data)
{
s32 status = 0;
if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
0)
status = ixgbe_read_eerd_buffer_generic(hw, offset,
words, data);
else
status = IXGBE_ERR_SWFW_SYNC;
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
return status; return status;
} }
...@@ -343,6 +371,31 @@ static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) ...@@ -343,6 +371,31 @@ static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
return status; return status;
} }
/**
* ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
* @hw: pointer to hardware structure
* @offset: offset of word in the EEPROM to write
* @words: number of words
* @data: word(s) write to the EEPROM
*
* Write a 16 bit word(s) to the EEPROM using the EEWR register.
**/
static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
u16 offset, u16 words, u16 *data)
{
s32 status = 0;
if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
0)
status = ixgbe_write_eewr_buffer_generic(hw, offset,
words, data);
else
status = IXGBE_ERR_SWFW_SYNC;
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
return status;
}
/** /**
* ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
* *
...@@ -851,7 +904,9 @@ static struct ixgbe_mac_operations mac_ops_X540 = { ...@@ -851,7 +904,9 @@ static struct ixgbe_mac_operations mac_ops_X540 = {
static struct ixgbe_eeprom_operations eeprom_ops_X540 = { static struct ixgbe_eeprom_operations eeprom_ops_X540 = {
.init_params = &ixgbe_init_eeprom_params_X540, .init_params = &ixgbe_init_eeprom_params_X540,
.read = &ixgbe_read_eerd_X540, .read = &ixgbe_read_eerd_X540,
.read_buffer = &ixgbe_read_eerd_buffer_X540,
.write = &ixgbe_write_eewr_X540, .write = &ixgbe_write_eewr_X540,
.write_buffer = &ixgbe_write_eewr_buffer_X540,
.calc_checksum = &ixgbe_calc_eeprom_checksum_X540, .calc_checksum = &ixgbe_calc_eeprom_checksum_X540,
.validate_checksum = &ixgbe_validate_eeprom_checksum_X540, .validate_checksum = &ixgbe_validate_eeprom_checksum_X540,
.update_checksum = &ixgbe_update_eeprom_checksum_X540, .update_checksum = &ixgbe_update_eeprom_checksum_X540,
......
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