Commit 5a6bfe09 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher

drm/amdgpu/psp: udpate ta_ras interface header

ras ta interface header need to be updated to match with latest ta fw updates
Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarJames Zhu <James.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 561564be
/****************************************************************************\ /*
* * Copyright 2019 Advanced Micro Devices, Inc.
* File Name ta_ras_if.h *
* Project AMD PSP SW IP Module * Permission is hereby granted, free of charge, to any person obtaining a
* * copy of this software and associated documentation files (the "Software"),
* Description Interface to the RAS Trusted Application * to deal in the Software without restriction, including without limitation
* * the rights to use, copy, modify, merge, publish, distribute, sublicense,
* Copyright 2019 Advanced Micro Devices, Inc. * and/or sell copies of the Software, and to permit persons to whom the
* * Software is furnished to do so, subject to the following conditions:
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software *
* and associated documentation files (the "Software"), to deal in the Software without restriction, * The above copyright notice and this permission notice shall be included in
* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, * all copies or substantial portions of the Software.
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, *
* subject to the following conditions: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* The above copyright notice and this permission notice shall be included in all copies or substantial * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* portions of the Software. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * OTHER DEALINGS IN THE SOFTWARE.
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR */
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _TA_RAS_IF_H #ifndef _TA_RAS_IF_H
#define _TA_RAS_IF_H #define _TA_RAS_IF_H
...@@ -31,8 +28,8 @@ ...@@ -31,8 +28,8 @@
#define RSP_ID_MASK (1U << 31) #define RSP_ID_MASK (1U << 31)
#define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK) #define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK)
#define TA_NUM_BLOCK_MAX 14 /* RAS related enumerations */
/**********************************************************/
enum ras_command { enum ras_command {
TA_RAS_COMMAND__ENABLE_FEATURES = 0, TA_RAS_COMMAND__ENABLE_FEATURES = 0,
TA_RAS_COMMAND__DISABLE_FEATURES, TA_RAS_COMMAND__DISABLE_FEATURES,
...@@ -45,7 +42,12 @@ enum ta_ras_status { ...@@ -45,7 +42,12 @@ enum ta_ras_status {
TA_RAS_STATUS__ERROR_INVALID_PARAMETER = 0x02, TA_RAS_STATUS__ERROR_INVALID_PARAMETER = 0x02,
TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE = 0x03, TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE = 0x03,
TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD = 0x04, TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD = 0x04,
TA_RAS_STATUS__ERROR_INJECTION_FAILED = 0x05 TA_RAS_STATUS__ERROR_INJECTION_FAILED = 0x05,
TA_RAS_STATUS__ERROR_ASD_READ_WRITE = 0x06,
TA_RAS_STATUS__ERROR_TOGGLE_DF_CSTATE = 0x07,
TA_RAS_STATUS__ERROR_TIMEOUT = 0x08,
TA_RAS_STATUS__ERROR_BLOCK_DISABLED = 0x09,
TA_RAS_STATUS__ERROR_GENERIC = 0x10,
}; };
enum ta_ras_block { enum ta_ras_block {
...@@ -62,7 +64,8 @@ enum ta_ras_block { ...@@ -62,7 +64,8 @@ enum ta_ras_block {
TA_RAS_BLOCK__SEM, TA_RAS_BLOCK__SEM,
TA_RAS_BLOCK__MP0, TA_RAS_BLOCK__MP0,
TA_RAS_BLOCK__MP1, TA_RAS_BLOCK__MP1,
TA_RAS_BLOCK__FUSE = (TA_NUM_BLOCK_MAX - 1), TA_RAS_BLOCK__FUSE,
TA_NUM_BLOCK_MAX
}; };
enum ta_ras_error_type { enum ta_ras_error_type {
...@@ -70,9 +73,12 @@ enum ta_ras_error_type { ...@@ -70,9 +73,12 @@ enum ta_ras_error_type {
TA_RAS_ERROR__PARITY = 1, TA_RAS_ERROR__PARITY = 1,
TA_RAS_ERROR__SINGLE_CORRECTABLE = 2, TA_RAS_ERROR__SINGLE_CORRECTABLE = 2,
TA_RAS_ERROR__MULTI_UNCORRECTABLE = 4, TA_RAS_ERROR__MULTI_UNCORRECTABLE = 4,
TA_RAS_ERROR__POISON = 8 TA_RAS_ERROR__POISON = 8,
}; };
/* Input/output structures for RAS commands */
/**********************************************************/
struct ta_ras_enable_features_input { struct ta_ras_enable_features_input {
enum ta_ras_block block_id; enum ta_ras_block block_id;
enum ta_ras_error_type error_type; enum ta_ras_error_type error_type;
...@@ -84,19 +90,23 @@ struct ta_ras_disable_features_input { ...@@ -84,19 +90,23 @@ struct ta_ras_disable_features_input {
}; };
struct ta_ras_trigger_error_input { struct ta_ras_trigger_error_input {
enum ta_ras_block block_id; enum ta_ras_block block_id; // ras-block. i.e. umc, gfx
enum ta_ras_error_type inject_error_type; enum ta_ras_error_type inject_error_type; // type of error. i.e. single_correctable
uint32_t sub_block_index; uint32_t sub_block_index; // mem block. i.e. hbm, sram etc.
uint64_t address; uint64_t address; // explicit address of error
uint64_t value; uint64_t value; // method if error injection. i.e persistent, coherent etc.
}; };
/* Common input structure for RAS callbacks */
/**********************************************************/
union ta_ras_cmd_input { union ta_ras_cmd_input {
struct ta_ras_enable_features_input enable_features; struct ta_ras_enable_features_input enable_features;
struct ta_ras_disable_features_input disable_features; struct ta_ras_disable_features_input disable_features;
struct ta_ras_trigger_error_input trigger_error; struct ta_ras_trigger_error_input trigger_error;
}; };
/* Shared Memory structures */
/**********************************************************/
struct ta_ras_shared_memory { struct ta_ras_shared_memory {
uint32_t cmd_id; uint32_t cmd_id;
uint32_t resp_id; uint32_t resp_id;
......
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