Commit 5bc6e3cf authored by Graf Yang's avatar Graf Yang Committed by Mike Frysinger

Blackfin: add CPLB entries for Core B on-chip L1 SRAM regions

The Blackfin SMP port was missing CPLB entries for Core B on-chip L1 SRAM
regions.  Any code that attempted to use these would wrongly crash due to
a CPLB miss.
Signed-off-by: default avatarGraf Yang <graf.yang@analog.com>
Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent f574a76a
...@@ -72,13 +72,24 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) ...@@ -72,13 +72,24 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
} }
/* Cover L1 memory. One 4M area for code and data each is enough. */ /* Cover L1 memory. One 4M area for code and data each is enough. */
if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { if (cpu == 0) {
d_tbl[i_d].addr = L1_DATA_A_START; if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; d_tbl[i_d].addr = L1_DATA_A_START;
d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
}
i_tbl[i_i].addr = L1_CODE_START;
i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
} }
i_tbl[i_i].addr = L1_CODE_START; #ifdef CONFIG_SMP
i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; else {
if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
d_tbl[i_d].addr = COREB_L1_DATA_A_START;
d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
}
i_tbl[i_i].addr = COREB_L1_CODE_START;
i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
}
#endif
first_switched_dcplb = i_d; first_switched_dcplb = i_d;
first_switched_icplb = i_i; first_switched_icplb = i_i;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment