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Commit 5c277007 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'mfd-for-linus-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd 

Pull MFD updates from Lee Jones:
 "Changes to existing drivers:
   - fixr platform device collision; da9052, wm8994-core
   - regmap configuration amendments; tps65218
   - fix runtime PM deadlock; rtsx_usb
   - remove unused/superfluous code; db8500-prcmu, omap-usb-host
   - enable watchdog timer; lpc_sch
   - add start/stop RX URBs helpers; dln2
   - remove platform device (DT only); max77686, max77802
   - support suspend and resume; dln2
   - add Device Tree support; da9063
   - extra error checking; intel_soc_pmic
   - const'ify all the things; 88pm860x, hi6421-pmic, intel_soc_pmic,
                               max77686, lm3533, retu, pcf50633,
                               davinci_voicecodec, smsc-ece1099,
                               tps65218, mc13xxx, tps65217, twl-core,
                               twl6040

  New drivers/supported devices:
   - new driver for Richtek RT5033
   - new driver for DA9150 Charger and FuelGauge
   - new driver for Qualcomm Resource Power Manager (RPM)
   - add support for the ir-clk into sun6i-prcm
   - add support for FuelGauge into axp20x"

* tag 'mfd-for-linus-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (32 commits)
  mfd: intel_soc_pmic: Add missing error check for devm_kzalloc
  mfd: rtsx_usb: Defer autosuspend while card exists
  mfd: devicetree: Add bindings for DA9063
  mfd: da9063: Add device tree support
  regulator: qcom-rpm: Add missing state flag in call to RPM
  mfd: qcom-rpm: Driver for the Qualcomm RPM
  mfd: devicetree: bindings: Add Qualcomm RPM DT binding
  mfd: max77686/802: Remove support for board files
  mfd: omap-usb-host: Remove some unused functions
  mfd: twl6040: Constify struct regmap_config and reg_default array
  mfd: twl-core: Constify struct regmap_config and reg_default array
  mfd: tps65217: Constify struct regmap_config
  mfd: mc13xxx: i2c/spi: Constify struct regmap_config
  mfd: tps65218: Constify struct regmap_config
  mfd: smsc-ece1099: Constify struct regmap_config
  mfd: davinci_voicecodec: Constify struct regmap_config
  mfd: pcf50633: Constify struct regmap_config
  mfd: retu: Constify struct regmap_config
  mfd: lm3533: Constify struct regmap_config
  mfd: max77686: Constify struct regmap_config
  ...
parents 9a8b2aa5 0a65fbf6
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Documentation/devicetree/bindings/mfd/da9063.txt 0 → 100644
View file @ 5c277007
* Dialog DA9063 Power Management Integrated Circuit (PMIC)
DA9093 consists of a large and varied group of sub-devices (I2C Only):
Device Supply Names Description
------ ------------ -----------
da9063-regulator : : LDOs & BUCKs
da9063-rtc : : Real-Time Clock
da9063-watchdog : : Watchdog
======
Required properties:
- compatible : Should be "dlg,da9063"
- reg : Specifies the I2C slave address (this defaults to 0x58 but it can be
modified to match the chip's OTP settings).
- interrupt-parent : Specifies the reference to the interrupt controller for
the DA9063.
- interrupts : IRQ line information.
- interrupt-controller
Sub-nodes:
- regulators : This node defines the settings for the LDOs and BUCKs. The
DA9063 regulators are bound using their names listed below:
bcore1 : BUCK CORE1
bcore2 : BUCK CORE2
bpro : BUCK PRO
bmem : BUCK MEM
bio : BUCK IO
bperi : BUCK PERI
ldo1 : LDO_1
ldo2 : LDO_2
ldo3 : LDO_3
ldo4 : LDO_4
ldo5 : LDO_5
ldo6 : LDO_6
ldo7 : LDO_7
ldo8 : LDO_8
ldo9 : LDO_9
ldo10 : LDO_10
ldo11 : LDO_11
The component follows the standard regulator framework and the bindings
details of individual regulator device can be found in:
Documentation/devicetree/bindings/regulator/regulator.txt
- rtc : This node defines settings for the Real-Time Clock associated with
the DA9063. There are currently no entries in this binding, however
compatible = "dlg,da9063-rtc" should be added if a node is created.
- watchdog : This node defines settings for the Watchdog timer associated
with the DA9063. There are currently no entries in this binding, however
compatible = "dlg,da9063-watchdog" should be added if a node is created.
Example:
pmic0: da9063@58 {
compatible = "dlg,da9063"
reg = <0x58>;
interrupt-parent = <&gpio6>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
rtc {
compatible = "dlg,da9063-rtc";
};
wdt {
compatible = "dlg,da9063-watchdog";
};
regulators {
DA9063_BCORE1: bcore1 {
regulator-name = "BCORE1";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-min-microamp = <500000>;
regulator-max-microamp = <2000000>;
regulator-boot-on;
};
DA9063_LDO11: ldo11 {
regulator-name = "LDO_11";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
};
};
};
Documentation/devicetree/bindings/mfd/qcom-rpm.txt 0 → 100644
View file @ 5c277007
Qualcomm Resource Power Manager (RPM)
This driver is used to interface with the Resource Power Manager (RPM) found in
various Qualcomm platforms. The RPM allows each component in the system to vote
for state of the system resources, such as clocks, regulators and bus
frequencies.
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,rpm-apq8064"
"qcom,rpm-msm8660"
"qcom,rpm-msm8960"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: base address and size of the RPM's message ram
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: three entries specifying the RPM's:
1. acknowledgement interrupt
2. error interrupt
3. wakeup interrupt
- interrupt-names:
Usage: required
Value type: <string-array>
Definition: must be the three strings "ack", "err" and "wakeup", in order
- #address-cells:
Usage: required
Value type: <u32>
Definition: must be 1
- #size-cells:
Usage: required
Value type: <u32>
Definition: must be 0
- qcom,ipc:
Usage: required
Value type: <prop-encoded-array>
Definition: three entries specifying the outgoing ipc bit used for
signaling the RPM:
- phandle to a syscon node representing the apcs registers
- u32 representing offset to the register within the syscon
- u32 representing the ipc bit within the register
= EXAMPLE
#include <dt-bindings/mfd/qcom-rpm.h>
rpm@108000 {
compatible = "qcom,rpm-msm8960";
reg = <0x108000 0x1000>;
qcom,ipc = <&apcs 0x8 2>;
interrupts = <0 19 0>, <0 21 0>, <0 22 0>;
interrupt-names = "ack", "err", "wakeup";
#address-cells = <1>;
#size-cells = <0>;
};
drivers/mfd/88pm860x-core.c
View file @ 5c277007
......@@ -1111,7 +1111,7 @@ static int verify_addr(struct i2c_client *i2c)
return 0;
}
static struct regmap_config pm860x_regmap_config = {
static const struct regmap_config pm860x_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
......
drivers/mfd/Kconfig
View file @ 5c277007
......@@ -195,6 +195,18 @@ config MFD_DA9063
Additional drivers must be enabled in order to use the functionality
of the device.
config MFD_DA9150
tristate "Dialog Semiconductor DA9150 Charger Fuel-Gauge chip"
depends on I2C=y
select MFD_CORE
select REGMAP_I2C
select REGMAP_IRQ
help
This adds support for the DA9150 integrated charger and fuel-gauge
chip. This driver provides common support for accessing the device.
Additional drivers must be enabled in order to use the specific
features of the device.
config MFD_DLN2
tristate "Diolan DLN2 support"
select MFD_CORE
......@@ -417,6 +429,7 @@ config MFD_MAX14577
config MFD_MAX77686
bool "Maxim Semiconductor MAX77686/802 PMIC Support"
depends on I2C=y
depends on OF
select MFD_CORE
select REGMAP_I2C
select REGMAP_IRQ
......@@ -589,6 +602,20 @@ config MFD_PM8921_CORE
Say M here if you want to include support for PM8921 chip as a module.
This will build a module called "pm8921-core".
config MFD_QCOM_RPM
tristate "Qualcomm Resource Power Manager (RPM)"
depends on ARCH_QCOM && OF
help
If you say yes to this option, support will be included for the
Resource Power Manager system found in the Qualcomm 8660, 8960 and
8064 based devices.
This is required to access many regulators, clocks and bus
frequencies controlled by the RPM on these devices.
Say M here if you want to include support for the Qualcomm RPM as a
module. This will build a module called "qcom_rpm".
config MFD_SPMI_PMIC
tristate "Qualcomm SPMI PMICs"
depends on ARCH_QCOM || COMPILE_TEST
......@@ -623,6 +650,18 @@ config MFD_RTSX_PCI
types of memory cards, such as Memory Stick, Memory Stick Pro,
Secure Digital and MultiMediaCard.
config MFD_RT5033
tristate "Richtek RT5033 Power Management IC"
depends on I2C=y
select MFD_CORE
select REGMAP_I2C
help
This driver provides for the Richtek RT5033 Power Management IC,
which includes the I2C driver and the Core APIs. This driver provides
common support for accessing the device. The device supports multiple
sub-devices like charger, fuel gauge, flash LED, current source,
LDO and Buck.
config MFD_RTSX_USB
tristate "Realtek USB card reader"
depends on USB
......
drivers/mfd/Makefile
View file @ 5c277007
......@@ -113,7 +113,7 @@ obj-$(CONFIG_MFD_DA9055) += da9055.o
da9063-objs := da9063-core.o da9063-irq.o da9063-i2c.o
obj-$(CONFIG_MFD_DA9063) += da9063.o
obj-$(CONFIG_MFD_DA9150) += da9150-core.o
obj-$(CONFIG_MFD_MAX14577) += max14577.o
obj-$(CONFIG_MFD_MAX77686) += max77686.o
obj-$(CONFIG_MFD_MAX77693) += max77693.o
......@@ -153,6 +153,7 @@ obj-$(CONFIG_MFD_SI476X_CORE) += si476x-core.o
obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o
obj-$(CONFIG_MFD_OMAP_USB_HOST) += omap-usb-host.o omap-usb-tll.o
obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o ssbi.o
obj-$(CONFIG_MFD_QCOM_RPM) += qcom_rpm.o
obj-$(CONFIG_MFD_SPMI_PMIC) += qcom-spmi-pmic.o
obj-$(CONFIG_TPS65911_COMPARATOR) += tps65911-comparator.o
obj-$(CONFIG_MFD_TPS65090) += tps65090.o
......@@ -176,6 +177,7 @@ obj-$(CONFIG_MFD_IPAQ_MICRO) += ipaq-micro.o
obj-$(CONFIG_MFD_MENF21BMC) += menf21bmc.o
obj-$(CONFIG_MFD_HI6421_PMIC) += hi6421-pmic-core.o
obj-$(CONFIG_MFD_DLN2) += dln2.o
obj-$(CONFIG_MFD_RT5033) += rt5033.o
intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o
obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
drivers/mfd/da9063-core.c
View file @ 5c277007
......@@ -86,6 +86,7 @@ static const struct mfd_cell da9063_devs[] = {
},
{
.name = DA9063_DRVNAME_WATCHDOG,
.of_compatible = "dlg,da9063-watchdog",
},
{
.name = DA9063_DRVNAME_HWMON,
......@@ -101,6 +102,7 @@ static const struct mfd_cell da9063_devs[] = {
.name = DA9063_DRVNAME_RTC,
.num_resources = ARRAY_SIZE(da9063_rtc_resources),
.resources = da9063_rtc_resources,
.of_compatible = "dlg,da9063-rtc",
},
{
.name = DA9063_DRVNAME_VIBRATION,
......
drivers/mfd/da9063-i2c.c
View file @ 5c277007
......@@ -25,6 +25,9 @@
#include <linux/mfd/da9063/pdata.h>
#include <linux/mfd/da9063/registers.h>
#include <linux/of.h>
#include <linux/regulator/of_regulator.h>
static const struct regmap_range da9063_ad_readable_ranges[] = {
{
.range_min = DA9063_REG_PAGE_CON,
......@@ -203,6 +206,11 @@ static struct regmap_config da9063_regmap_config = {
.cache_type = REGCACHE_RBTREE,
};
static const struct of_device_id da9063_dt_ids[] = {
{ .compatible = "dlg,da9063", },
{ }
};
MODULE_DEVICE_TABLE(of, da9063_dt_ids);
static int da9063_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
......@@ -257,6 +265,7 @@ static struct i2c_driver da9063_i2c_driver = {
.driver = {
.name = "da9063",
.owner = THIS_MODULE,
.of_match_table = of_match_ptr(da9063_dt_ids),
},
.probe = da9063_i2c_probe,
.remove = da9063_i2c_remove,
......
drivers/mfd/da9150-core.c 0 → 100644
View file @ 5c277007
/*
* DA9150 Core MFD Driver
*
* Copyright (c) 2014 Dialog Semiconductor
*
* Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/mfd/da9150/core.h>
#include <linux/mfd/da9150/registers.h>
static bool da9150_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case DA9150_PAGE_CON:
case DA9150_STATUS_A:
case DA9150_STATUS_B:
case DA9150_STATUS_C:
case DA9150_STATUS_D:
case DA9150_STATUS_E:
case DA9150_STATUS_F:
case DA9150_STATUS_G:
case DA9150_STATUS_H:
case DA9150_STATUS_I:
case DA9150_STATUS_J:
case DA9150_STATUS_K:
case DA9150_STATUS_L:
case DA9150_STATUS_N:
case DA9150_FAULT_LOG_A:
case DA9150_FAULT_LOG_B:
case DA9150_EVENT_E:
case DA9150_EVENT_F:
case DA9150_EVENT_G:
case DA9150_EVENT_H:
case DA9150_CONTROL_B:
case DA9150_CONTROL_C:
case DA9150_GPADC_MAN:
case DA9150_GPADC_RES_A:
case DA9150_GPADC_RES_B:
case DA9150_ADETVB_CFG_C:
case DA9150_ADETD_STAT:
case DA9150_ADET_CMPSTAT:
case DA9150_ADET_CTRL_A:
case DA9150_PPR_TCTR_B:
case DA9150_COREBTLD_STAT_A:
case DA9150_CORE_DATA_A:
case DA9150_CORE_DATA_B:
case DA9150_CORE_DATA_C:
case DA9150_CORE_DATA_D:
case DA9150_CORE2WIRE_STAT_A:
case DA9150_FW_CTRL_C:
case DA9150_FG_CTRL_B:
case DA9150_FW_CTRL_B:
case DA9150_GPADC_CMAN:
case DA9150_GPADC_CRES_A:
case DA9150_GPADC_CRES_B:
case DA9150_CC_ICHG_RES_A:
case DA9150_CC_ICHG_RES_B:
case DA9150_CC_IAVG_RES_A:
case DA9150_CC_IAVG_RES_B:
case DA9150_TAUX_CTRL_A:
case DA9150_TAUX_VALUE_H:
case DA9150_TAUX_VALUE_L:
case DA9150_TBAT_RES_A:
case DA9150_TBAT_RES_B:
return true;
default:
return false;
}
}
static const struct regmap_range_cfg da9150_range_cfg[] = {
{
.range_min = DA9150_PAGE_CON,
.range_max = DA9150_TBAT_RES_B,
.selector_reg = DA9150_PAGE_CON,
.selector_mask = DA9150_I2C_PAGE_MASK,
.selector_shift = DA9150_I2C_PAGE_SHIFT,
.window_start = 0,
.window_len = 256,
},
};
static struct regmap_config da9150_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.ranges = da9150_range_cfg,
.num_ranges = ARRAY_SIZE(da9150_range_cfg),
.max_register = DA9150_TBAT_RES_B,
.cache_type = REGCACHE_RBTREE,
.volatile_reg = da9150_volatile_reg,
};
u8 da9150_reg_read(struct da9150 *da9150, u16 reg)
{
int val, ret;
ret = regmap_read(da9150->regmap, reg, &val);
if (ret)
dev_err(da9150->dev, "Failed to read from reg 0x%x: %d\n",
reg, ret);
return (u8) val;
}
EXPORT_SYMBOL_GPL(da9150_reg_read);
void da9150_reg_write(struct da9150 *da9150, u16 reg, u8 val)
{
int ret;
ret = regmap_write(da9150->regmap, reg, val);
if (ret)
dev_err(da9150->dev, "Failed to write to reg 0x%x: %d\n",
reg, ret);
}
EXPORT_SYMBOL_GPL(da9150_reg_write);
void da9150_set_bits(struct da9150 *da9150, u16 reg, u8 mask, u8 val)
{
int ret;
ret = regmap_update_bits(da9150->regmap, reg, mask, val);
if (ret)
dev_err(da9150->dev, "Failed to set bits in reg 0x%x: %d\n",
reg, ret);
}
EXPORT_SYMBOL_GPL(da9150_set_bits);
void da9150_bulk_read(struct da9150 *da9150, u16 reg, int count, u8 *buf)
{
int ret;
ret = regmap_bulk_read(da9150->regmap, reg, buf, count);
if (ret)
dev_err(da9150->dev, "Failed to bulk read from reg 0x%x: %d\n",
reg, ret);
}
EXPORT_SYMBOL_GPL(da9150_bulk_read);
void da9150_bulk_write(struct da9150 *da9150, u16 reg, int count, const u8 *buf)
{
int ret;
ret = regmap_raw_write(da9150->regmap, reg, buf, count);
if (ret)
dev_err(da9150->dev, "Failed to bulk write to reg 0x%x %d\n",
reg, ret);
}
EXPORT_SYMBOL_GPL(da9150_bulk_write);
static struct regmap_irq da9150_irqs[] = {
[DA9150_IRQ_VBUS] = {
.reg_offset = 0,
.mask = DA9150_E_VBUS_MASK,
},
[DA9150_IRQ_CHG] = {
.reg_offset = 0,
.mask = DA9150_E_CHG_MASK,
},
[DA9150_IRQ_TCLASS] = {
.reg_offset = 0,
.mask = DA9150_E_TCLASS_MASK,
},
[DA9150_IRQ_TJUNC] = {
.reg_offset = 0,
.mask = DA9150_E_TJUNC_MASK,
},
[DA9150_IRQ_VFAULT] = {
.reg_offset = 0,
.mask = DA9150_E_VFAULT_MASK,
},
[DA9150_IRQ_CONF] = {
.reg_offset = 1,
.mask = DA9150_E_CONF_MASK,
},
[DA9150_IRQ_DAT] = {
.reg_offset = 1,
.mask = DA9150_E_DAT_MASK,
},
[DA9150_IRQ_DTYPE] = {
.reg_offset = 1,
.mask = DA9150_E_DTYPE_MASK,
},
[DA9150_IRQ_ID] = {
.reg_offset = 1,
.mask = DA9150_E_ID_MASK,
},
[DA9150_IRQ_ADP] = {
.reg_offset = 1,
.mask = DA9150_E_ADP_MASK,
},
[DA9150_IRQ_SESS_END] = {
.reg_offset = 1,
.mask = DA9150_E_SESS_END_MASK,
},
[DA9150_IRQ_SESS_VLD] = {
.reg_offset = 1,
.mask = DA9150_E_SESS_VLD_MASK,
},
[DA9150_IRQ_FG] = {
.reg_offset = 2,
.mask = DA9150_E_FG_MASK,
},
[DA9150_IRQ_GP] = {
.reg_offset = 2,
.mask = DA9150_E_GP_MASK,
},
[DA9150_IRQ_TBAT] = {
.reg_offset = 2,
.mask = DA9150_E_TBAT_MASK,
},
[DA9150_IRQ_GPIOA] = {
.reg_offset = 2,
.mask = DA9150_E_GPIOA_MASK,
},
[DA9150_IRQ_GPIOB] = {
.reg_offset = 2,
.mask = DA9150_E_GPIOB_MASK,
},
[DA9150_IRQ_GPIOC] = {
.reg_offset = 2,
.mask = DA9150_E_GPIOC_MASK,
},
[DA9150_IRQ_GPIOD] = {
.reg_offset = 2,
.mask = DA9150_E_GPIOD_MASK,
},
[DA9150_IRQ_GPADC] = {
.reg_offset = 2,
.mask = DA9150_E_GPADC_MASK,
},
[DA9150_IRQ_WKUP] = {
.reg_offset = 3,
.mask = DA9150_E_WKUP_MASK,
},
};
static struct regmap_irq_chip da9150_regmap_irq_chip = {
.name = "da9150_irq",
.status_base = DA9150_EVENT_E,
.mask_base = DA9150_IRQ_MASK_E,
.ack_base = DA9150_EVENT_E,
.num_regs = DA9150_NUM_IRQ_REGS,
.irqs = da9150_irqs,
.num_irqs = ARRAY_SIZE(da9150_irqs),
};
static struct resource da9150_gpadc_resources[] = {
{
.name = "GPADC",
.start = DA9150_IRQ_GPADC,
.end = DA9150_IRQ_GPADC,
.flags = IORESOURCE_IRQ,
},
};
static struct resource da9150_charger_resources[] = {
{
.name = "CHG_STATUS",
.start = DA9150_IRQ_CHG,
.end = DA9150_IRQ_CHG,
.flags = IORESOURCE_IRQ,
},
{
.name = "CHG_TJUNC",
.start = DA9150_IRQ_TJUNC,
.end = DA9150_IRQ_TJUNC,
.flags = IORESOURCE_IRQ,
},
{
.name = "CHG_VFAULT",
.start = DA9150_IRQ_VFAULT,
.end = DA9150_IRQ_VFAULT,
.flags = IORESOURCE_IRQ,
},
{
.name = "CHG_VBUS",
.start = DA9150_IRQ_VBUS,
.end = DA9150_IRQ_VBUS,
.flags = IORESOURCE_IRQ,
},
};
static struct mfd_cell da9150_devs[] = {
{
.name = "da9150-gpadc",
.of_compatible = "dlg,da9150-gpadc",
.resources = da9150_gpadc_resources,
.num_resources = ARRAY_SIZE(da9150_gpadc_resources),
},
{
.name = "da9150-charger",
.of_compatible = "dlg,da9150-charger",
.resources = da9150_charger_resources,
.num_resources = ARRAY_SIZE(da9150_charger_resources),
},
};
static int da9150_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct da9150 *da9150;
struct da9150_pdata *pdata = dev_get_platdata(&client->dev);
int ret;
da9150 = devm_kzalloc(&client->dev, sizeof(*da9150), GFP_KERNEL);
if (!da9150)
return -ENOMEM;
da9150->dev = &client->dev;
da9150->irq = client->irq;
i2c_set_clientdata(client, da9150);
da9150->regmap = devm_regmap_init_i2c(client, &da9150_regmap_config);
if (IS_ERR(da9150->regmap)) {
ret = PTR_ERR(da9150->regmap);
dev_err(da9150->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
da9150->irq_base = pdata ? pdata->irq_base : -1;
ret = regmap_add_irq_chip(da9150->regmap, da9150->irq,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
da9150->irq_base, &da9150_regmap_irq_chip,
&da9150->regmap_irq_data);
if (ret)
return ret;
da9150->irq_base = regmap_irq_chip_get_base(da9150->regmap_irq_data);
enable_irq_wake(da9150->irq);
ret = mfd_add_devices(da9150->dev, -1, da9150_devs,
ARRAY_SIZE(da9150_devs), NULL,
da9150->irq_base, NULL);
if (ret) {
dev_err(da9150->dev, "Failed to add child devices: %d\n", ret);
regmap_del_irq_chip(da9150->irq, da9150->regmap_irq_data);
return ret;
}
return 0;
}
static int da9150_remove(struct i2c_client *client)
{
struct da9150 *da9150 = i2c_get_clientdata(client);
regmap_del_irq_chip(da9150->irq, da9150->regmap_irq_data);
mfd_remove_devices(da9150->dev);
return 0;
}
static void da9150_shutdown(struct i2c_client *client)
{
struct da9150 *da9150 = i2c_get_clientdata(client);
/* Make sure we have a wakup source for the device */
da9150_set_bits(da9150, DA9150_CONFIG_D,
DA9150_WKUP_PM_EN_MASK,
DA9150_WKUP_PM_EN_MASK);
/* Set device to DISABLED mode */
da9150_set_bits(da9150, DA9150_CONTROL_C,
DA9150_DISABLE_MASK, DA9150_DISABLE_MASK);
}
static const struct i2c_device_id da9150_i2c_id[] = {
{ "da9150", },
{ }
};
MODULE_DEVICE_TABLE(i2c, da9150_i2c_id);
static const struct of_device_id da9150_of_match[] = {
{ .compatible = "dlg,da9150", },
{ }
};
MODULE_DEVICE_TABLE(of, da9150_of_match);
static struct i2c_driver da9150_driver = {
.driver = {
.name = "da9150",
.of_match_table = of_match_ptr(da9150_of_match),
},
.probe = da9150_probe,
.remove = da9150_remove,
.shutdown = da9150_shutdown,
.id_table = da9150_i2c_id,
};
module_i2c_driver(da9150_driver);
MODULE_DESCRIPTION("MFD Core Driver for DA9150");
MODULE_AUTHOR("Adam Thomson <Adam.Thomson.Opensource@diasemi.com>");
MODULE_LICENSE("GPL");
drivers/mfd/davinci_voicecodec.c
View file @ 5c277007
......@@ -33,7 +33,7 @@
#include <linux/mfd/davinci_voicecodec.h>
static struct regmap_config davinci_vc_regmap = {
static const struct regmap_config davinci_vc_regmap = {
.reg_bits = 32,
.val_bits = 32,
};
......
drivers/mfd/db8500-prcmu.c
View file @ 5c277007
......@@ -674,15 +674,6 @@ bool prcmu_has_arm_maxopp(void)
PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
}
/**
* prcmu_get_boot_status - PRCMU boot status checking
* Returns: the current PRCMU boot status
*/
int prcmu_get_boot_status(void)
{
return readb(tcdm_base + PRCM_BOOT_STATUS);
}
/**
* prcmu_set_rc_a2p - This function is used to run few power state sequences
* @val: Value to be set, i.e. transition requested
......
drivers/mfd/dln2.c
View file @ 5c277007
......@@ -587,12 +587,19 @@ static void dln2_free_rx_urbs(struct dln2_dev *dln2)
int i;
for (i = 0; i < DLN2_MAX_URBS; i++) {
usb_kill_urb(dln2->rx_urb[i]);
usb_free_urb(dln2->rx_urb[i]);
kfree(dln2->rx_buf[i]);
}
}
static void dln2_stop_rx_urbs(struct dln2_dev *dln2)
{
int i;
for (i = 0; i < DLN2_MAX_URBS; i++)
usb_kill_urb(dln2->rx_urb[i]);
}
static void dln2_free(struct dln2_dev *dln2)
{
dln2_free_rx_urbs(dln2);
......@@ -604,9 +611,7 @@ static int dln2_setup_rx_urbs(struct dln2_dev *dln2,
struct usb_host_interface *hostif)
{
int i;
int ret;
const int rx_max_size = DLN2_RX_BUF_SIZE;
struct device *dev = &dln2->interface->dev;
for (i = 0; i < DLN2_MAX_URBS; i++) {
dln2->rx_buf[i] = kmalloc(rx_max_size, GFP_KERNEL);
......@@ -620,8 +625,19 @@ static int dln2_setup_rx_urbs(struct dln2_dev *dln2,
usb_fill_bulk_urb(dln2->rx_urb[i], dln2->usb_dev,
usb_rcvbulkpipe(dln2->usb_dev, dln2->ep_in),
dln2->rx_buf[i], rx_max_size, dln2_rx, dln2);
}
ret = usb_submit_urb(dln2->rx_urb[i], GFP_KERNEL);
return 0;
}
static int dln2_start_rx_urbs(struct dln2_dev *dln2, gfp_t gfp)
{
struct device *dev = &dln2->interface->dev;
int ret;
int i;
for (i = 0; i < DLN2_MAX_URBS; i++) {
ret = usb_submit_urb(dln2->rx_urb[i], gfp);
if (ret < 0) {
dev_err(dev, "failed to submit RX URB: %d\n", ret);
return ret;
......@@ -665,9 +681,8 @@ static const struct mfd_cell dln2_devs[] = {
},
};
static void dln2_disconnect(struct usb_interface *interface)
static void dln2_stop(struct dln2_dev *dln2)
{
struct dln2_dev *dln2 = usb_get_intfdata(interface);
int i, j;
/* don't allow starting new transfers */
......@@ -696,6 +711,15 @@ static void dln2_disconnect(struct usb_interface *interface)
/* wait for transfers to end */
wait_event(dln2->disconnect_wq, !dln2->active_transfers);
dln2_stop_rx_urbs(dln2);
}
static void dln2_disconnect(struct usb_interface *interface)
{
struct dln2_dev *dln2 = usb_get_intfdata(interface);
dln2_stop(dln2);
mfd_remove_devices(&interface->dev);
dln2_free(dln2);
......@@ -738,28 +762,53 @@ static int dln2_probe(struct usb_interface *interface,
ret = dln2_setup_rx_urbs(dln2, hostif);
if (ret)
goto out_cleanup;
goto out_free;
ret = dln2_start_rx_urbs(dln2, GFP_KERNEL);
if (ret)
goto out_stop_rx;
ret = dln2_hw_init(dln2);
if (ret < 0) {
dev_err(dev, "failed to initialize hardware\n");
goto out_cleanup;
goto out_stop_rx;
}
ret = mfd_add_hotplug_devices(dev, dln2_devs, ARRAY_SIZE(dln2_devs));
if (ret != 0) {
dev_err(dev, "failed to add mfd devices to core\n");
goto out_cleanup;
goto out_stop_rx;
}
return 0;
out_cleanup:
out_stop_rx:
dln2_stop_rx_urbs(dln2);
out_free:
dln2_free(dln2);
return ret;
}
static int dln2_suspend(struct usb_interface *iface, pm_message_t message)
{
struct dln2_dev *dln2 = usb_get_intfdata(iface);
dln2_stop(dln2);
return 0;
}
static int dln2_resume(struct usb_interface *iface)
{
struct dln2_dev *dln2 = usb_get_intfdata(iface);
dln2->disconnect = false;
return dln2_start_rx_urbs(dln2, GFP_NOIO);
}
static const struct usb_device_id dln2_table[] = {
{ USB_DEVICE(0xa257, 0x2013) },
{ }
......@@ -772,6 +821,8 @@ static struct usb_driver dln2_driver = {
.probe = dln2_probe,
.disconnect = dln2_disconnect,
.id_table = dln2_table,
.suspend = dln2_suspend,
.resume = dln2_resume,
};
module_usb_driver(dln2_driver);
......
drivers/mfd/hi6421-pmic-core.c
View file @ 5c277007
......@@ -35,7 +35,7 @@ static const struct mfd_cell hi6421_devs[] = {
{ .name = "hi6421-regulator", },
};
static struct regmap_config hi6421_regmap_config = {
static const struct regmap_config hi6421_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 8,
......
drivers/mfd/intel_soc_pmic_core.c
View file @ 5c277007
......@@ -64,6 +64,9 @@ static int intel_soc_pmic_i2c_probe(struct i2c_client *i2c,
config = (struct intel_soc_pmic_config *)id->driver_data;
pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
if (!pmic)
return -ENOMEM;
dev_set_drvdata(dev, pmic);
pmic->regmap = devm_regmap_init_i2c(i2c, config->regmap_config);
......
drivers/mfd/intel_soc_pmic_core.h
View file @ 5c277007
......@@ -23,7 +23,7 @@ struct intel_soc_pmic_config {
unsigned long irq_flags;
struct mfd_cell *cell_dev;
int n_cell_devs;
struct regmap_config *regmap_config;
const struct regmap_config *regmap_config;
struct regmap_irq_chip *irq_chip;
};
......
drivers/mfd/intel_soc_pmic_crc.c
View file @ 5c277007
......@@ -111,7 +111,7 @@ static struct mfd_cell crystal_cove_dev[] = {
},
};
static struct regmap_config crystal_cove_regmap_config = {
static const struct regmap_config crystal_cove_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
......
drivers/mfd/lm3533-core.c
View file @ 5c277007
......@@ -583,7 +583,7 @@ static bool lm3533_precious_register(struct device *dev, unsigned int reg)
}
}
static struct regmap_config regmap_config = {
static const struct regmap_config regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = LM3533_REG_MAX,
......
drivers/mfd/lpc_sch.c
View file @ 5c277007
......@@ -75,6 +75,7 @@ static struct lpc_sch_info sch_chipset_info[] = {
[LPC_QUARK_X1000] = {
.io_size_gpio = GPIO_IO_SIZE,
.irq_gpio = GPIO_IRQ_QUARK_X1000,
.io_size_wdt = WDT_IO_SIZE,
},
};
......
drivers/mfd/max77686.c
View file @ 5c277007
......@@ -111,17 +111,17 @@ static bool max77802_is_volatile_reg(struct device *dev, unsigned int reg)
max77802_rtc_is_volatile_reg(dev, reg));
}
static struct regmap_config max77686_regmap_config = {
static const struct regmap_config max77686_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
static struct regmap_config max77686_rtc_regmap_config = {
static const struct regmap_config max77686_rtc_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
static struct regmap_config max77802_regmap_config = {
static const struct regmap_config max77802_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.writeable_reg = max77802_is_accessible_reg,
......@@ -205,24 +205,10 @@ static const struct of_device_id max77686_pmic_dt_match[] = {
{ },
};
static struct max77686_platform_data *max77686_i2c_parse_dt_pdata(struct device
*dev)
{
struct max77686_platform_data *pd;
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
if (!pd)
return NULL;
dev->platform_data = pd;
return pd;
}
static int max77686_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct max77686_dev *max77686 = NULL;
struct max77686_platform_data *pdata = dev_get_platdata(&i2c->dev);
const struct of_device_id *match;
unsigned int data;
int ret = 0;
......@@ -233,14 +219,6 @@ static int max77686_i2c_probe(struct i2c_client *i2c,
const struct mfd_cell *cells;
int n_devs;
if (IS_ENABLED(CONFIG_OF) && i2c->dev.of_node && !pdata)
pdata = max77686_i2c_parse_dt_pdata(&i2c->dev);
if (!pdata) {
dev_err(&i2c->dev, "No platform data found.\n");
return -EINVAL;
}
max77686 = devm_kzalloc(&i2c->dev,
sizeof(struct max77686_dev), GFP_KERNEL);
if (!max77686)
......@@ -259,7 +237,6 @@ static int max77686_i2c_probe(struct i2c_client *i2c,
max77686->dev = &i2c->dev;
max77686->i2c = i2c;
max77686->wakeup = pdata->wakeup;
max77686->irq = i2c->irq;
if (max77686->type == TYPE_MAX77686) {
......
drivers/mfd/mc13xxx-i2c.c
View file @ 5c277007
......@@ -46,7 +46,7 @@ static const struct of_device_id mc13xxx_dt_ids[] = {
};
MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
static struct regmap_config mc13xxx_regmap_i2c_config = {
static const struct regmap_config mc13xxx_regmap_i2c_config = {
.reg_bits = 8,
.val_bits = 24,
......
drivers/mfd/mc13xxx-spi.c
View file @ 5c277007
......@@ -48,7 +48,7 @@ static const struct of_device_id mc13xxx_dt_ids[] = {
};
MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
static struct regmap_config mc13xxx_regmap_spi_config = {
static const struct regmap_config mc13xxx_regmap_spi_config = {
.reg_bits = 7,
.pad_bits = 1,
.val_bits = 24,
......
drivers/mfd/omap-usb-host.c
View file @ 5c277007
......@@ -129,16 +129,6 @@ static inline u32 usbhs_read(void __iomem *base, u32 reg)
return readl_relaxed(base + reg);
}
static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
{
writeb_relaxed(val, base + reg);
}
static inline u8 usbhs_readb(void __iomem *base, u8 reg)
{
return readb_relaxed(base + reg);
}
/*-------------------------------------------------------------------------*/
/**
......
drivers/mfd/pcf50633-core.c
View file @ 5c277007
......@@ -183,7 +183,7 @@ static int pcf50633_resume(struct device *dev)
static SIMPLE_DEV_PM_OPS(pcf50633_pm, pcf50633_suspend, pcf50633_resume);
static struct regmap_config pcf50633_regmap_config = {
static const struct regmap_config pcf50633_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
......
drivers/mfd/qcom_rpm.c 0 → 100644
View file @ 5c277007
/*
* Copyright (c) 2014, Sony Mobile Communications AB.
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
* Author: Bjorn Andersson <bjorn.andersson@sonymobile.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/mfd/qcom_rpm.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <dt-bindings/mfd/qcom-rpm.h>
struct qcom_rpm_resource {
unsigned target_id;
unsigned status_id;
unsigned select_id;
unsigned size;
};
struct qcom_rpm_data {
u32 version;
const struct qcom_rpm_resource *resource_table;
unsigned n_resources;
};
struct qcom_rpm {
struct device *dev;
struct regmap *ipc_regmap;
unsigned ipc_offset;
unsigned ipc_bit;
struct completion ack;
struct mutex lock;
void __iomem *status_regs;
void __iomem *ctrl_regs;
void __iomem *req_regs;
u32 ack_status;
const struct qcom_rpm_data *data;
};
#define RPM_STATUS_REG(rpm, i) ((rpm)->status_regs + (i) * 4)
#define RPM_CTRL_REG(rpm, i) ((rpm)->ctrl_regs + (i) * 4)
#define RPM_REQ_REG(rpm, i) ((rpm)->req_regs + (i) * 4)
#define RPM_REQUEST_TIMEOUT (5 * HZ)
#define RPM_REQUEST_CONTEXT 3
#define RPM_REQ_SELECT 11
#define RPM_ACK_CONTEXT 15
#define RPM_ACK_SELECTOR 23
#define RPM_SELECT_SIZE 7
#define RPM_NOTIFICATION BIT(30)
#define RPM_REJECTED BIT(31)
#define RPM_SIGNAL BIT(2)
static const struct qcom_rpm_resource apq8064_rpm_resource_table[] = {
[QCOM_RPM_CXO_CLK] = { 25, 9, 5, 1 },
[QCOM_RPM_PXO_CLK] = { 26, 10, 6, 1 },
[QCOM_RPM_APPS_FABRIC_CLK] = { 27, 11, 8, 1 },
[QCOM_RPM_SYS_FABRIC_CLK] = { 28, 12, 9, 1 },
[QCOM_RPM_MM_FABRIC_CLK] = { 29, 13, 10, 1 },
[QCOM_RPM_DAYTONA_FABRIC_CLK] = { 30, 14, 11, 1 },
[QCOM_RPM_SFPB_CLK] = { 31, 15, 12, 1 },
[QCOM_RPM_CFPB_CLK] = { 32, 16, 13, 1 },
[QCOM_RPM_MMFPB_CLK] = { 33, 17, 14, 1 },
[QCOM_RPM_EBI1_CLK] = { 34, 18, 16, 1 },
[QCOM_RPM_APPS_FABRIC_HALT] = { 35, 19, 18, 1 },
[QCOM_RPM_APPS_FABRIC_MODE] = { 37, 20, 19, 1 },
[QCOM_RPM_APPS_FABRIC_IOCTL] = { 40, 21, 20, 1 },
[QCOM_RPM_APPS_FABRIC_ARB] = { 41, 22, 21, 12 },
[QCOM_RPM_SYS_FABRIC_HALT] = { 53, 23, 22, 1 },
[QCOM_RPM_SYS_FABRIC_MODE] = { 55, 24, 23, 1 },
[QCOM_RPM_SYS_FABRIC_IOCTL] = { 58, 25, 24, 1 },
[QCOM_RPM_SYS_FABRIC_ARB] = { 59, 26, 25, 30 },
[QCOM_RPM_MM_FABRIC_HALT] = { 89, 27, 26, 1 },
[QCOM_RPM_MM_FABRIC_MODE] = { 91, 28, 27, 1 },
[QCOM_RPM_MM_FABRIC_IOCTL] = { 94, 29, 28, 1 },
[QCOM_RPM_MM_FABRIC_ARB] = { 95, 30, 29, 21 },
[QCOM_RPM_PM8921_SMPS1] = { 116, 31, 30, 2 },
[QCOM_RPM_PM8921_SMPS2] = { 118, 33, 31, 2 },
[QCOM_RPM_PM8921_SMPS3] = { 120, 35, 32, 2 },
[QCOM_RPM_PM8921_SMPS4] = { 122, 37, 33, 2 },
[QCOM_RPM_PM8921_SMPS5] = { 124, 39, 34, 2 },
[QCOM_RPM_PM8921_SMPS6] = { 126, 41, 35, 2 },
[QCOM_RPM_PM8921_SMPS7] = { 128, 43, 36, 2 },
[QCOM_RPM_PM8921_SMPS8] = { 130, 45, 37, 2 },
[QCOM_RPM_PM8921_LDO1] = { 132, 47, 38, 2 },
[QCOM_RPM_PM8921_LDO2] = { 134, 49, 39, 2 },
[QCOM_RPM_PM8921_LDO3] = { 136, 51, 40, 2 },
[QCOM_RPM_PM8921_LDO4] = { 138, 53, 41, 2 },
[QCOM_RPM_PM8921_LDO5] = { 140, 55, 42, 2 },
[QCOM_RPM_PM8921_LDO6] = { 142, 57, 43, 2 },
[QCOM_RPM_PM8921_LDO7] = { 144, 59, 44, 2 },
[QCOM_RPM_PM8921_LDO8] = { 146, 61, 45, 2 },
[QCOM_RPM_PM8921_LDO9] = { 148, 63, 46, 2 },
[QCOM_RPM_PM8921_LDO10] = { 150, 65, 47, 2 },
[QCOM_RPM_PM8921_LDO11] = { 152, 67, 48, 2 },
[QCOM_RPM_PM8921_LDO12] = { 154, 69, 49, 2 },
[QCOM_RPM_PM8921_LDO13] = { 156, 71, 50, 2 },
[QCOM_RPM_PM8921_LDO14] = { 158, 73, 51, 2 },
[QCOM_RPM_PM8921_LDO15] = { 160, 75, 52, 2 },
[QCOM_RPM_PM8921_LDO16] = { 162, 77, 53, 2 },
[QCOM_RPM_PM8921_LDO17] = { 164, 79, 54, 2 },
[QCOM_RPM_PM8921_LDO18] = { 166, 81, 55, 2 },
[QCOM_RPM_PM8921_LDO19] = { 168, 83, 56, 2 },
[QCOM_RPM_PM8921_LDO20] = { 170, 85, 57, 2 },
[QCOM_RPM_PM8921_LDO21] = { 172, 87, 58, 2 },
[QCOM_RPM_PM8921_LDO22] = { 174, 89, 59, 2 },
[QCOM_RPM_PM8921_LDO23] = { 176, 91, 60, 2 },
[QCOM_RPM_PM8921_LDO24] = { 178, 93, 61, 2 },
[QCOM_RPM_PM8921_LDO25] = { 180, 95, 62, 2 },
[QCOM_RPM_PM8921_LDO26] = { 182, 97, 63, 2 },
[QCOM_RPM_PM8921_LDO27] = { 184, 99, 64, 2 },
[QCOM_RPM_PM8921_LDO28] = { 186, 101, 65, 2 },
[QCOM_RPM_PM8921_LDO29] = { 188, 103, 66, 2 },
[QCOM_RPM_PM8921_CLK1] = { 190, 105, 67, 2 },
[QCOM_RPM_PM8921_CLK2] = { 192, 107, 68, 2 },
[QCOM_RPM_PM8921_LVS1] = { 194, 109, 69, 1 },
[QCOM_RPM_PM8921_LVS2] = { 195, 110, 70, 1 },
[QCOM_RPM_PM8921_LVS3] = { 196, 111, 71, 1 },
[QCOM_RPM_PM8921_LVS4] = { 197, 112, 72, 1 },
[QCOM_RPM_PM8921_LVS5] = { 198, 113, 73, 1 },
[QCOM_RPM_PM8921_LVS6] = { 199, 114, 74, 1 },
[QCOM_RPM_PM8921_LVS7] = { 200, 115, 75, 1 },
[QCOM_RPM_PM8821_SMPS1] = { 201, 116, 76, 2 },
[QCOM_RPM_PM8821_SMPS2] = { 203, 118, 77, 2 },
[QCOM_RPM_PM8821_LDO1] = { 205, 120, 78, 2 },
[QCOM_RPM_PM8921_NCP] = { 207, 122, 80, 2 },
[QCOM_RPM_CXO_BUFFERS] = { 209, 124, 81, 1 },
[QCOM_RPM_USB_OTG_SWITCH] = { 210, 125, 82, 1 },
[QCOM_RPM_HDMI_SWITCH] = { 211, 126, 83, 1 },
[QCOM_RPM_DDR_DMM] = { 212, 127, 84, 2 },
[QCOM_RPM_VDDMIN_GPIO] = { 215, 131, 89, 1 },
};
static const struct qcom_rpm_data apq8064_template = {
.version = 3,
.resource_table = apq8064_rpm_resource_table,
.n_resources = ARRAY_SIZE(apq8064_rpm_resource_table),
};
static const struct qcom_rpm_resource msm8660_rpm_resource_table[] = {
[QCOM_RPM_CXO_CLK] = { 32, 12, 5, 1 },
[QCOM_RPM_PXO_CLK] = { 33, 13, 6, 1 },
[QCOM_RPM_PLL_4] = { 34, 14, 7, 1 },
[QCOM_RPM_APPS_FABRIC_CLK] = { 35, 15, 8, 1 },
[QCOM_RPM_SYS_FABRIC_CLK] = { 36, 16, 9, 1 },
[QCOM_RPM_MM_FABRIC_CLK] = { 37, 17, 10, 1 },
[QCOM_RPM_DAYTONA_FABRIC_CLK] = { 38, 18, 11, 1 },
[QCOM_RPM_SFPB_CLK] = { 39, 19, 12, 1 },
[QCOM_RPM_CFPB_CLK] = { 40, 20, 13, 1 },
[QCOM_RPM_MMFPB_CLK] = { 41, 21, 14, 1 },
[QCOM_RPM_SMI_CLK] = { 42, 22, 15, 1 },
[QCOM_RPM_EBI1_CLK] = { 43, 23, 16, 1 },
[QCOM_RPM_APPS_L2_CACHE_CTL] = { 44, 24, 17, 1 },
[QCOM_RPM_APPS_FABRIC_HALT] = { 45, 25, 18, 2 },
[QCOM_RPM_APPS_FABRIC_MODE] = { 47, 26, 19, 3 },
[QCOM_RPM_APPS_FABRIC_ARB] = { 51, 28, 21, 6 },
[QCOM_RPM_SYS_FABRIC_HALT] = { 63, 29, 22, 2 },
[QCOM_RPM_SYS_FABRIC_MODE] = { 65, 30, 23, 3 },
[QCOM_RPM_SYS_FABRIC_ARB] = { 69, 32, 25, 22 },
[QCOM_RPM_MM_FABRIC_HALT] = { 105, 33, 26, 2 },
[QCOM_RPM_MM_FABRIC_MODE] = { 107, 34, 27, 3 },
[QCOM_RPM_MM_FABRIC_ARB] = { 111, 36, 29, 23 },
[QCOM_RPM_PM8901_SMPS0] = { 134, 37, 30, 2 },
[QCOM_RPM_PM8901_SMPS1] = { 136, 39, 31, 2 },
[QCOM_RPM_PM8901_SMPS2] = { 138, 41, 32, 2 },
[QCOM_RPM_PM8901_SMPS3] = { 140, 43, 33, 2 },
[QCOM_RPM_PM8901_SMPS4] = { 142, 45, 34, 2 },
[QCOM_RPM_PM8901_LDO0] = { 144, 47, 35, 2 },
[QCOM_RPM_PM8901_LDO1] = { 146, 49, 36, 2 },
[QCOM_RPM_PM8901_LDO2] = { 148, 51, 37, 2 },
[QCOM_RPM_PM8901_LDO3] = { 150, 53, 38, 2 },
[QCOM_RPM_PM8901_LDO4] = { 152, 55, 39, 2 },
[QCOM_RPM_PM8901_LDO5] = { 154, 57, 40, 2 },
[QCOM_RPM_PM8901_LDO6] = { 156, 59, 41, 2 },
[QCOM_RPM_PM8901_LVS0] = { 158, 61, 42, 1 },
[QCOM_RPM_PM8901_LVS1] = { 159, 62, 43, 1 },
[QCOM_RPM_PM8901_LVS2] = { 160, 63, 44, 1 },
[QCOM_RPM_PM8901_LVS3] = { 161, 64, 45, 1 },
[QCOM_RPM_PM8901_MVS] = { 162, 65, 46, 1 },
[QCOM_RPM_PM8058_SMPS0] = { 163, 66, 47, 2 },
[QCOM_RPM_PM8058_SMPS1] = { 165, 68, 48, 2 },
[QCOM_RPM_PM8058_SMPS2] = { 167, 70, 49, 2 },
[QCOM_RPM_PM8058_SMPS3] = { 169, 72, 50, 2 },
[QCOM_RPM_PM8058_SMPS4] = { 171, 74, 51, 2 },
[QCOM_RPM_PM8058_LDO0] = { 173, 76, 52, 2 },
[QCOM_RPM_PM8058_LDO1] = { 175, 78, 53, 2 },
[QCOM_RPM_PM8058_LDO2] = { 177, 80, 54, 2 },
[QCOM_RPM_PM8058_LDO3] = { 179, 82, 55, 2 },
[QCOM_RPM_PM8058_LDO4] = { 181, 84, 56, 2 },
[QCOM_RPM_PM8058_LDO5] = { 183, 86, 57, 2 },
[QCOM_RPM_PM8058_LDO6] = { 185, 88, 58, 2 },
[QCOM_RPM_PM8058_LDO7] = { 187, 90, 59, 2 },
[QCOM_RPM_PM8058_LDO8] = { 189, 92, 60, 2 },
[QCOM_RPM_PM8058_LDO9] = { 191, 94, 61, 2 },
[QCOM_RPM_PM8058_LDO10] = { 193, 96, 62, 2 },
[QCOM_RPM_PM8058_LDO11] = { 195, 98, 63, 2 },
[QCOM_RPM_PM8058_LDO12] = { 197, 100, 64, 2 },
[QCOM_RPM_PM8058_LDO13] = { 199, 102, 65, 2 },
[QCOM_RPM_PM8058_LDO14] = { 201, 104, 66, 2 },
[QCOM_RPM_PM8058_LDO15] = { 203, 106, 67, 2 },
[QCOM_RPM_PM8058_LDO16] = { 205, 108, 68, 2 },
[QCOM_RPM_PM8058_LDO17] = { 207, 110, 69, 2 },
[QCOM_RPM_PM8058_LDO18] = { 209, 112, 70, 2 },
[QCOM_RPM_PM8058_LDO19] = { 211, 114, 71, 2 },
[QCOM_RPM_PM8058_LDO20] = { 213, 116, 72, 2 },
[QCOM_RPM_PM8058_LDO21] = { 215, 118, 73, 2 },
[QCOM_RPM_PM8058_LDO22] = { 217, 120, 74, 2 },
[QCOM_RPM_PM8058_LDO23] = { 219, 122, 75, 2 },
[QCOM_RPM_PM8058_LDO24] = { 221, 124, 76, 2 },
[QCOM_RPM_PM8058_LDO25] = { 223, 126, 77, 2 },
[QCOM_RPM_PM8058_LVS0] = { 225, 128, 78, 1 },
[QCOM_RPM_PM8058_LVS1] = { 226, 129, 79, 1 },
[QCOM_RPM_PM8058_NCP] = { 227, 130, 80, 2 },
[QCOM_RPM_CXO_BUFFERS] = { 229, 132, 81, 1 },
};
static const struct qcom_rpm_data msm8660_template = {
.version = 2,
.resource_table = msm8660_rpm_resource_table,
.n_resources = ARRAY_SIZE(msm8660_rpm_resource_table),
};
static const struct qcom_rpm_resource msm8960_rpm_resource_table[] = {
[QCOM_RPM_CXO_CLK] = { 25, 9, 5, 1 },
[QCOM_RPM_PXO_CLK] = { 26, 10, 6, 1 },
[QCOM_RPM_APPS_FABRIC_CLK] = { 27, 11, 8, 1 },
[QCOM_RPM_SYS_FABRIC_CLK] = { 28, 12, 9, 1 },
[QCOM_RPM_MM_FABRIC_CLK] = { 29, 13, 10, 1 },
[QCOM_RPM_DAYTONA_FABRIC_CLK] = { 30, 14, 11, 1 },
[QCOM_RPM_SFPB_CLK] = { 31, 15, 12, 1 },
[QCOM_RPM_CFPB_CLK] = { 32, 16, 13, 1 },
[QCOM_RPM_MMFPB_CLK] = { 33, 17, 14, 1 },
[QCOM_RPM_EBI1_CLK] = { 34, 18, 16, 1 },
[QCOM_RPM_APPS_FABRIC_HALT] = { 35, 19, 18, 1 },
[QCOM_RPM_APPS_FABRIC_MODE] = { 37, 20, 19, 1 },
[QCOM_RPM_APPS_FABRIC_IOCTL] = { 40, 21, 20, 1 },
[QCOM_RPM_APPS_FABRIC_ARB] = { 41, 22, 21, 12 },
[QCOM_RPM_SYS_FABRIC_HALT] = { 53, 23, 22, 1 },
[QCOM_RPM_SYS_FABRIC_MODE] = { 55, 24, 23, 1 },
[QCOM_RPM_SYS_FABRIC_IOCTL] = { 58, 25, 24, 1 },
[QCOM_RPM_SYS_FABRIC_ARB] = { 59, 26, 25, 29 },
[QCOM_RPM_MM_FABRIC_HALT] = { 88, 27, 26, 1 },
[QCOM_RPM_MM_FABRIC_MODE] = { 90, 28, 27, 1 },
[QCOM_RPM_MM_FABRIC_IOCTL] = { 93, 29, 28, 1 },
[QCOM_RPM_MM_FABRIC_ARB] = { 94, 30, 29, 23 },
[QCOM_RPM_PM8921_SMPS1] = { 117, 31, 30, 2 },
[QCOM_RPM_PM8921_SMPS2] = { 119, 33, 31, 2 },
[QCOM_RPM_PM8921_SMPS3] = { 121, 35, 32, 2 },
[QCOM_RPM_PM8921_SMPS4] = { 123, 37, 33, 2 },
[QCOM_RPM_PM8921_SMPS5] = { 125, 39, 34, 2 },
[QCOM_RPM_PM8921_SMPS6] = { 127, 41, 35, 2 },
[QCOM_RPM_PM8921_SMPS7] = { 129, 43, 36, 2 },
[QCOM_RPM_PM8921_SMPS8] = { 131, 45, 37, 2 },
[QCOM_RPM_PM8921_LDO1] = { 133, 47, 38, 2 },
[QCOM_RPM_PM8921_LDO2] = { 135, 49, 39, 2 },
[QCOM_RPM_PM8921_LDO3] = { 137, 51, 40, 2 },
[QCOM_RPM_PM8921_LDO4] = { 139, 53, 41, 2 },
[QCOM_RPM_PM8921_LDO5] = { 141, 55, 42, 2 },
[QCOM_RPM_PM8921_LDO6] = { 143, 57, 43, 2 },
[QCOM_RPM_PM8921_LDO7] = { 145, 59, 44, 2 },
[QCOM_RPM_PM8921_LDO8] = { 147, 61, 45, 2 },
[QCOM_RPM_PM8921_LDO9] = { 149, 63, 46, 2 },
[QCOM_RPM_PM8921_LDO10] = { 151, 65, 47, 2 },
[QCOM_RPM_PM8921_LDO11] = { 153, 67, 48, 2 },
[QCOM_RPM_PM8921_LDO12] = { 155, 69, 49, 2 },
[QCOM_RPM_PM8921_LDO13] = { 157, 71, 50, 2 },
[QCOM_RPM_PM8921_LDO14] = { 159, 73, 51, 2 },
[QCOM_RPM_PM8921_LDO15] = { 161, 75, 52, 2 },
[QCOM_RPM_PM8921_LDO16] = { 163, 77, 53, 2 },
[QCOM_RPM_PM8921_LDO17] = { 165, 79, 54, 2 },
[QCOM_RPM_PM8921_LDO18] = { 167, 81, 55, 2 },
[QCOM_RPM_PM8921_LDO19] = { 169, 83, 56, 2 },
[QCOM_RPM_PM8921_LDO20] = { 171, 85, 57, 2 },
[QCOM_RPM_PM8921_LDO21] = { 173, 87, 58, 2 },
[QCOM_RPM_PM8921_LDO22] = { 175, 89, 59, 2 },
[QCOM_RPM_PM8921_LDO23] = { 177, 91, 60, 2 },
[QCOM_RPM_PM8921_LDO24] = { 179, 93, 61, 2 },
[QCOM_RPM_PM8921_LDO25] = { 181, 95, 62, 2 },
[QCOM_RPM_PM8921_LDO26] = { 183, 97, 63, 2 },
[QCOM_RPM_PM8921_LDO27] = { 185, 99, 64, 2 },
[QCOM_RPM_PM8921_LDO28] = { 187, 101, 65, 2 },
[QCOM_RPM_PM8921_LDO29] = { 189, 103, 66, 2 },
[QCOM_RPM_PM8921_CLK1] = { 191, 105, 67, 2 },
[QCOM_RPM_PM8921_CLK2] = { 193, 107, 68, 2 },
[QCOM_RPM_PM8921_LVS1] = { 195, 109, 69, 1 },
[QCOM_RPM_PM8921_LVS2] = { 196, 110, 70, 1 },
[QCOM_RPM_PM8921_LVS3] = { 197, 111, 71, 1 },
[QCOM_RPM_PM8921_LVS4] = { 198, 112, 72, 1 },
[QCOM_RPM_PM8921_LVS5] = { 199, 113, 73, 1 },
[QCOM_RPM_PM8921_LVS6] = { 200, 114, 74, 1 },
[QCOM_RPM_PM8921_LVS7] = { 201, 115, 75, 1 },
[QCOM_RPM_PM8921_NCP] = { 202, 116, 80, 2 },
[QCOM_RPM_CXO_BUFFERS] = { 204, 118, 81, 1 },
[QCOM_RPM_USB_OTG_SWITCH] = { 205, 119, 82, 1 },
[QCOM_RPM_HDMI_SWITCH] = { 206, 120, 83, 1 },
[QCOM_RPM_DDR_DMM] = { 207, 121, 84, 2 },
};
static const struct qcom_rpm_data msm8960_template = {
.version = 3,
.resource_table = msm8960_rpm_resource_table,
.n_resources = ARRAY_SIZE(msm8960_rpm_resource_table),
};
static const struct of_device_id qcom_rpm_of_match[] = {
{ .compatible = "qcom,rpm-apq8064", .data = &apq8064_template },
{ .compatible = "qcom,rpm-msm8660", .data = &msm8660_template },
{ .compatible = "qcom,rpm-msm8960", .data = &msm8960_template },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_rpm_of_match);
int qcom_rpm_write(struct qcom_rpm *rpm,
int state,
int resource,
u32 *buf, size_t count)
{
const struct qcom_rpm_resource *res;
const struct qcom_rpm_data *data = rpm->data;
u32 sel_mask[RPM_SELECT_SIZE] = { 0 };
int left;
int ret = 0;
int i;
if (WARN_ON(resource < 0 || resource >= data->n_resources))
return -EINVAL;
res = &data->resource_table[resource];
if (WARN_ON(res->size != count))
return -EINVAL;
mutex_lock(&rpm->lock);
for (i = 0; i < res->size; i++)
writel_relaxed(buf[i], RPM_REQ_REG(rpm, res->target_id + i));
bitmap_set((unsigned long *)sel_mask, res->select_id, 1);
for (i = 0; i < ARRAY_SIZE(sel_mask); i++) {
writel_relaxed(sel_mask[i],
RPM_CTRL_REG(rpm, RPM_REQ_SELECT + i));
}
writel_relaxed(BIT(state), RPM_CTRL_REG(rpm, RPM_REQUEST_CONTEXT));
reinit_completion(&rpm->ack);
regmap_write(rpm->ipc_regmap, rpm->ipc_offset, BIT(rpm->ipc_bit));
left = wait_for_completion_timeout(&rpm->ack, RPM_REQUEST_TIMEOUT);
if (!left)
ret = -ETIMEDOUT;
else if (rpm->ack_status & RPM_REJECTED)
ret = -EIO;
mutex_unlock(&rpm->lock);
return ret;
}
EXPORT_SYMBOL(qcom_rpm_write);
static irqreturn_t qcom_rpm_ack_interrupt(int irq, void *dev)
{
struct qcom_rpm *rpm = dev;
u32 ack;
int i;
ack = readl_relaxed(RPM_CTRL_REG(rpm, RPM_ACK_CONTEXT));
for (i = 0; i < RPM_SELECT_SIZE; i++)
writel_relaxed(0, RPM_CTRL_REG(rpm, RPM_ACK_SELECTOR + i));
writel(0, RPM_CTRL_REG(rpm, RPM_ACK_CONTEXT));
if (ack & RPM_NOTIFICATION) {
dev_warn(rpm->dev, "ignoring notification!\n");
} else {
rpm->ack_status = ack;
complete(&rpm->ack);
}
return IRQ_HANDLED;
}
static irqreturn_t qcom_rpm_err_interrupt(int irq, void *dev)
{
struct qcom_rpm *rpm = dev;
regmap_write(rpm->ipc_regmap, rpm->ipc_offset, BIT(rpm->ipc_bit));
dev_err(rpm->dev, "RPM triggered fatal error\n");
return IRQ_HANDLED;
}
static irqreturn_t qcom_rpm_wakeup_interrupt(int irq, void *dev)
{
return IRQ_HANDLED;
}
static int qcom_rpm_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
struct device_node *syscon_np;
struct resource *res;
struct qcom_rpm *rpm;
u32 fw_version[3];
int irq_wakeup;
int irq_ack;
int irq_err;
int ret;
rpm = devm_kzalloc(&pdev->dev, sizeof(*rpm), GFP_KERNEL);
if (!rpm)
return -ENOMEM;
rpm->dev = &pdev->dev;
mutex_init(&rpm->lock);
init_completion(&rpm->ack);
irq_ack = platform_get_irq_byname(pdev, "ack");
if (irq_ack < 0) {
dev_err(&pdev->dev, "required ack interrupt missing\n");
return irq_ack;
}
irq_err = platform_get_irq_byname(pdev, "err");
if (irq_err < 0) {
dev_err(&pdev->dev, "required err interrupt missing\n");
return irq_err;
}
irq_wakeup = platform_get_irq_byname(pdev, "wakeup");
if (irq_wakeup < 0) {
dev_err(&pdev->dev, "required wakeup interrupt missing\n");
return irq_wakeup;
}
match = of_match_device(qcom_rpm_of_match, &pdev->dev);
rpm->data = match->data;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
rpm->status_regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(rpm->status_regs))
return PTR_ERR(rpm->status_regs);
rpm->ctrl_regs = rpm->status_regs + 0x400;
rpm->req_regs = rpm->status_regs + 0x600;
syscon_np = of_parse_phandle(pdev->dev.of_node, "qcom,ipc", 0);
if (!syscon_np) {
dev_err(&pdev->dev, "no qcom,ipc node\n");
return -ENODEV;
}
rpm->ipc_regmap = syscon_node_to_regmap(syscon_np);
if (IS_ERR(rpm->ipc_regmap))
return PTR_ERR(rpm->ipc_regmap);
ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,ipc", 1,
&rpm->ipc_offset);
if (ret < 0) {
dev_err(&pdev->dev, "no offset in qcom,ipc\n");
return -EINVAL;
}
ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,ipc", 2,
&rpm->ipc_bit);
if (ret < 0) {
dev_err(&pdev->dev, "no bit in qcom,ipc\n");
return -EINVAL;
}
dev_set_drvdata(&pdev->dev, rpm);
fw_version[0] = readl(RPM_STATUS_REG(rpm, 0));
fw_version[1] = readl(RPM_STATUS_REG(rpm, 1));
fw_version[2] = readl(RPM_STATUS_REG(rpm, 2));
if (fw_version[0] != rpm->data->version) {
dev_err(&pdev->dev,
"RPM version %u.%u.%u incompatible with driver version %u",
fw_version[0],
fw_version[1],
fw_version[2],
rpm->data->version);
return -EFAULT;
}
dev_info(&pdev->dev, "RPM firmware %u.%u.%u\n", fw_version[0],
fw_version[1],
fw_version[2]);
ret = devm_request_irq(&pdev->dev,
irq_ack,
qcom_rpm_ack_interrupt,
IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND,
"qcom_rpm_ack",
rpm);
if (ret) {
dev_err(&pdev->dev, "failed to request ack interrupt\n");
return ret;
}
ret = irq_set_irq_wake(irq_ack, 1);
if (ret)
dev_warn(&pdev->dev, "failed to mark ack irq as wakeup\n");
ret = devm_request_irq(&pdev->dev,
irq_err,
qcom_rpm_err_interrupt,
IRQF_TRIGGER_RISING,
"qcom_rpm_err",
rpm);
if (ret) {
dev_err(&pdev->dev, "failed to request err interrupt\n");
return ret;
}
ret = devm_request_irq(&pdev->dev,
irq_wakeup,
qcom_rpm_wakeup_interrupt,
IRQF_TRIGGER_RISING,
"qcom_rpm_wakeup",
rpm);
if (ret) {
dev_err(&pdev->dev, "failed to request wakeup interrupt\n");
return ret;
}
ret = irq_set_irq_wake(irq_wakeup, 1);
if (ret)
dev_warn(&pdev->dev, "failed to mark wakeup irq as wakeup\n");
return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
}
static int qcom_rpm_remove(struct platform_device *pdev)
{
of_platform_depopulate(&pdev->dev);
return 0;
}
static struct platform_driver qcom_rpm_driver = {
.probe = qcom_rpm_probe,
.remove = qcom_rpm_remove,
.driver = {
.name = "qcom_rpm",
.of_match_table = qcom_rpm_of_match,
},
};
static int __init qcom_rpm_init(void)
{
return platform_driver_register(&qcom_rpm_driver);
}
arch_initcall(qcom_rpm_init);
static void __exit qcom_rpm_exit(void)
{
platform_driver_unregister(&qcom_rpm_driver);
}
module_exit(qcom_rpm_exit)
MODULE_DESCRIPTION("Qualcomm Resource Power Manager driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
drivers/mfd/retu-mfd.c
View file @ 5c277007
......@@ -222,7 +222,7 @@ static struct regmap_bus retu_bus = {
.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
};
static struct regmap_config retu_config = {
static const struct regmap_config retu_config = {
.reg_bits = 8,
.val_bits = 16,
};
......
drivers/mfd/rt5033.c 0 → 100644
View file @ 5c277007
/*
* MFD core driver for the Richtek RT5033.
*
* RT5033 comprises multiple sub-devices switcing charger, fuel gauge,
* flash LED, current source, LDO and BUCK regulators.
*
* Copyright (C) 2014 Samsung Electronics, Co., Ltd.
* Author: Beomho Seo <beomho.seo@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published bythe Free Software Foundation.
*/
#include <linux/err.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/of_device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/rt5033.h>
#include <linux/mfd/rt5033-private.h>
static const struct regmap_irq rt5033_irqs[] = {
{ .mask = RT5033_PMIC_IRQ_BUCKOCP, },
{ .mask = RT5033_PMIC_IRQ_BUCKLV, },
{ .mask = RT5033_PMIC_IRQ_SAFELDOLV, },
{ .mask = RT5033_PMIC_IRQ_LDOLV, },
{ .mask = RT5033_PMIC_IRQ_OT, },
{ .mask = RT5033_PMIC_IRQ_VDDA_UV, },
};
static const struct regmap_irq_chip rt5033_irq_chip = {
.name = "rt5033",
.status_base = RT5033_REG_PMIC_IRQ_STAT,
.mask_base = RT5033_REG_PMIC_IRQ_CTRL,
.mask_invert = true,
.num_regs = 1,
.irqs = rt5033_irqs,
.num_irqs = ARRAY_SIZE(rt5033_irqs),
};
static const struct mfd_cell rt5033_devs[] = {
{ .name = "rt5033-regulator", },
{
.name = "rt5033-charger",
.of_compatible = "richtek,rt5033-charger",
}, {
.name = "rt5033-battery",
.of_compatible = "richtek,rt5033-battery",
},
};
static const struct regmap_config rt5033_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = RT5033_REG_END,
};
static int rt5033_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct rt5033_dev *rt5033;
unsigned int dev_id;
int ret;
rt5033 = devm_kzalloc(&i2c->dev, sizeof(*rt5033), GFP_KERNEL);
if (!rt5033)
return -ENOMEM;
i2c_set_clientdata(i2c, rt5033);
rt5033->dev = &i2c->dev;
rt5033->irq = i2c->irq;
rt5033->wakeup = true;
rt5033->regmap = devm_regmap_init_i2c(i2c, &rt5033_regmap_config);
if (IS_ERR(rt5033->regmap)) {
dev_err(&i2c->dev, "Failed to allocate register map.\n");
return PTR_ERR(rt5033->regmap);
}
ret = regmap_read(rt5033->regmap, RT5033_REG_DEVICE_ID, &dev_id);
if (ret) {
dev_err(&i2c->dev, "Device not found\n");
return -ENODEV;
}
dev_info(&i2c->dev, "Device found Device ID: %04x\n", dev_id);
ret = regmap_add_irq_chip(rt5033->regmap, rt5033->irq,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
0, &rt5033_irq_chip, &rt5033->irq_data);
if (ret) {
dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
rt5033->irq, ret);
return ret;
}
ret = mfd_add_devices(rt5033->dev, -1, rt5033_devs,
ARRAY_SIZE(rt5033_devs), NULL, 0,
regmap_irq_get_domain(rt5033->irq_data));
if (ret < 0) {
dev_err(&i2c->dev, "Failed to add RT5033 child devices.\n");
return ret;
}
device_init_wakeup(rt5033->dev, rt5033->wakeup);
return 0;
}
static int rt5033_i2c_remove(struct i2c_client *i2c)
{
mfd_remove_devices(&i2c->dev);
return 0;
}
static const struct i2c_device_id rt5033_i2c_id[] = {
{ "rt5033", },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt5033_i2c_id);
static const struct of_device_id rt5033_dt_match[] = {
{ .compatible = "richtek,rt5033", },
{ }
};
static struct i2c_driver rt5033_driver = {
.driver = {
.name = "rt5033",
.of_match_table = of_match_ptr(rt5033_dt_match),
},
.probe = rt5033_i2c_probe,
.remove = rt5033_i2c_remove,
.id_table = rt5033_i2c_id,
};
module_i2c_driver(rt5033_driver);
MODULE_ALIAS("i2c:rt5033");
MODULE_DESCRIPTION("Richtek RT5033 multi-function core driver");
MODULE_AUTHOR("Beomho Seo <beomho.seo@samsung.com>");
MODULE_LICENSE("GPL");
drivers/mfd/rtsx_usb.c
View file @ 5c277007
......@@ -681,9 +681,27 @@ static void rtsx_usb_disconnect(struct usb_interface *intf)
#ifdef CONFIG_PM
static int rtsx_usb_suspend(struct usb_interface *intf, pm_message_t message)
{
struct rtsx_ucr *ucr =
(struct rtsx_ucr *)usb_get_intfdata(intf);
u16 val = 0;
dev_dbg(&intf->dev, "%s called with pm message 0x%04x\n",
__func__, message.event);
if (PMSG_IS_AUTO(message)) {
if (mutex_trylock(&ucr->dev_mutex)) {
rtsx_usb_get_card_status(ucr, &val);
mutex_unlock(&ucr->dev_mutex);
/* Defer the autosuspend if card exists */
if (val & (SD_CD | MS_CD))
return -EAGAIN;
} else {
/* There is an ongoing operation*/
return -EAGAIN;
}
}
return 0;
}
......
drivers/mfd/smsc-ece1099.c
View file @ 5c277007
......@@ -24,7 +24,7 @@
#include <linux/mfd/smsc.h>
#include <linux/of_platform.h>
static struct regmap_config smsc_regmap_config = {
static const struct regmap_config smsc_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = SMSC_VEN_ID_H,
......
drivers/mfd/sun6i-prcm.c
View file @ 5c277007
......@@ -41,6 +41,14 @@ static const struct resource sun6i_a31_apb0_gates_clk_res[] = {
},
};
static const struct resource sun6i_a31_ir_clk_res[] = {
{
.start = 0x54,
.end = 0x57,
.flags = IORESOURCE_MEM,
},
};
static const struct resource sun6i_a31_apb0_rstc_res[] = {
{
.start = 0xb0,
......@@ -68,6 +76,12 @@ static const struct mfd_cell sun6i_a31_prcm_subdevs[] = {
.num_resources = ARRAY_SIZE(sun6i_a31_apb0_gates_clk_res),
.resources = sun6i_a31_apb0_gates_clk_res,
},
{
.name = "sun6i-a31-ir-clk",
.of_compatible = "allwinner,sun4i-a10-mod0-clk",
.num_resources = ARRAY_SIZE(sun6i_a31_ir_clk_res),
.resources = sun6i_a31_ir_clk_res,
},
{
.name = "sun6i-a31-apb0-clock-reset",
.of_compatible = "allwinner,sun6i-a31-clock-reset",
......
drivers/mfd/tps65217.c
View file @ 5c277007
......@@ -145,7 +145,7 @@ int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
}
EXPORT_SYMBOL_GPL(tps65217_clear_bits);
static struct regmap_config tps65217_regmap_config = {
static const struct regmap_config tps65217_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
......
drivers/mfd/tps65218.c
View file @ 5c277007
......@@ -135,7 +135,7 @@ static const struct regmap_access_table tps65218_volatile_table = {
.n_yes_ranges = ARRAY_SIZE(tps65218_yes_ranges),
};
static struct regmap_config tps65218_regmap_config = {
static const struct regmap_config tps65218_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
......
drivers/mfd/twl-core.c
View file @ 5c277007
......@@ -207,7 +207,7 @@ static struct twl_mapping twl4030_map[] = {
{ 2, TWL5031_BASEADD_INTERRUPTS },
};
static struct reg_default twl4030_49_defaults[] = {
static const struct reg_default twl4030_49_defaults[] = {
/* Audio Registers */
{ 0x01, 0x00}, /* CODEC_MODE */
{ 0x02, 0x00}, /* OPTION */
......@@ -306,7 +306,7 @@ static const struct regmap_access_table twl4030_49_volatile_table = {
.n_yes_ranges = ARRAY_SIZE(twl4030_49_volatile_ranges),
};
static struct regmap_config twl4030_regmap_config[4] = {
static const struct regmap_config twl4030_regmap_config[4] = {
{
/* Address 0x48 */
.reg_bits = 8,
......@@ -369,7 +369,7 @@ static struct twl_mapping twl6030_map[] = {
{ 1, TWL6030_BASEADD_GASGAUGE },
};
static struct regmap_config twl6030_regmap_config[3] = {
static const struct regmap_config twl6030_regmap_config[3] = {
{
/* Address 0x48 */
.reg_bits = 8,
......@@ -1087,7 +1087,7 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
struct twl4030_platform_data *pdata = dev_get_platdata(&client->dev);
struct device_node *node = client->dev.of_node;
struct platform_device *pdev;
struct regmap_config *twl_regmap_config;
const struct regmap_config *twl_regmap_config;
int irq_base = 0;
int status;
unsigned i, num_slaves;
......
drivers/mfd/twl6040.c
View file @ 5c277007
......@@ -44,7 +44,7 @@
#define VIBRACTRL_MEMBER(reg) ((reg == TWL6040_REG_VIBCTLL) ? 0 : 1)
#define TWL6040_NUM_SUPPLIES (2)
static struct reg_default twl6040_defaults[] = {
static const struct reg_default twl6040_defaults[] = {
{ 0x01, 0x4B }, /* REG_ASICID (ro) */
{ 0x02, 0x00 }, /* REG_ASICREV (ro) */
{ 0x03, 0x00 }, /* REG_INTID */
......@@ -580,7 +580,7 @@ static bool twl6040_writeable_reg(struct device *dev, unsigned int reg)
}
}
static struct regmap_config twl6040_regmap_config = {
static const struct regmap_config twl6040_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
......
drivers/mfd/wm8994-core.c
View file @ 5c277007
......@@ -36,12 +36,12 @@
static const struct mfd_cell wm8994_regulator_devs[] = {
{
.name = "wm8994-ldo",
.id = 1,
.id = 0,
.pm_runtime_no_callbacks = true,
},
{
.name = "wm8994-ldo",
.id = 2,
.id = 1,
.pm_runtime_no_callbacks = true,
},
};
......@@ -344,7 +344,7 @@ static int wm8994_device_init(struct wm8994 *wm8994, int irq)
dev_set_drvdata(wm8994->dev, wm8994);
/* Add the on-chip regulators first for bootstrapping */
ret = mfd_add_devices(wm8994->dev, -1,
ret = mfd_add_devices(wm8994->dev, 0,
wm8994_regulator_devs,
ARRAY_SIZE(wm8994_regulator_devs),
NULL, 0, NULL);
......
drivers/regulator/qcom_rpm-regulator.c
View file @ 5c277007
......@@ -205,6 +205,7 @@ static int rpm_reg_write(struct qcom_rpm_reg *vreg,
vreg->val[req->word] |= value << req->shift;
return qcom_rpm_write(vreg->rpm,
QCOM_RPM_ACTIVE_STATE,
vreg->resource,
vreg->val,
vreg->parts->request_len);
......
include/dt-bindings/mfd/qcom-rpm.h 0 → 100644
View file @ 5c277007
/*
* This header provides constants for the Qualcomm RPM bindings.
*/
#ifndef _DT_BINDINGS_MFD_QCOM_RPM_H
#define _DT_BINDINGS_MFD_QCOM_RPM_H
/*
* Constants use to identify individual resources in the RPM.
*/
#define QCOM_RPM_APPS_FABRIC_ARB 1
#define QCOM_RPM_APPS_FABRIC_CLK 2
#define QCOM_RPM_APPS_FABRIC_HALT 3
#define QCOM_RPM_APPS_FABRIC_IOCTL 4
#define QCOM_RPM_APPS_FABRIC_MODE 5
#define QCOM_RPM_APPS_L2_CACHE_CTL 6
#define QCOM_RPM_CFPB_CLK 7
#define QCOM_RPM_CXO_BUFFERS 8
#define QCOM_RPM_CXO_CLK 9
#define QCOM_RPM_DAYTONA_FABRIC_CLK 10
#define QCOM_RPM_DDR_DMM 11
#define QCOM_RPM_EBI1_CLK 12
#define QCOM_RPM_HDMI_SWITCH 13
#define QCOM_RPM_MMFPB_CLK 14
#define QCOM_RPM_MM_FABRIC_ARB 15
#define QCOM_RPM_MM_FABRIC_CLK 16
#define QCOM_RPM_MM_FABRIC_HALT 17
#define QCOM_RPM_MM_FABRIC_IOCTL 18
#define QCOM_RPM_MM_FABRIC_MODE 19
#define QCOM_RPM_PLL_4 20
#define QCOM_RPM_PM8058_LDO0 21
#define QCOM_RPM_PM8058_LDO1 22
#define QCOM_RPM_PM8058_LDO2 23
#define QCOM_RPM_PM8058_LDO3 24
#define QCOM_RPM_PM8058_LDO4 25
#define QCOM_RPM_PM8058_LDO5 26
#define QCOM_RPM_PM8058_LDO6 27
#define QCOM_RPM_PM8058_LDO7 28
#define QCOM_RPM_PM8058_LDO8 29
#define QCOM_RPM_PM8058_LDO9 30
#define QCOM_RPM_PM8058_LDO10 31
#define QCOM_RPM_PM8058_LDO11 32
#define QCOM_RPM_PM8058_LDO12 33
#define QCOM_RPM_PM8058_LDO13 34
#define QCOM_RPM_PM8058_LDO14 35
#define QCOM_RPM_PM8058_LDO15 36
#define QCOM_RPM_PM8058_LDO16 37
#define QCOM_RPM_PM8058_LDO17 38
#define QCOM_RPM_PM8058_LDO18 39
#define QCOM_RPM_PM8058_LDO19 40
#define QCOM_RPM_PM8058_LDO20 41
#define QCOM_RPM_PM8058_LDO21 42
#define QCOM_RPM_PM8058_LDO22 43
#define QCOM_RPM_PM8058_LDO23 44
#define QCOM_RPM_PM8058_LDO24 45
#define QCOM_RPM_PM8058_LDO25 46
#define QCOM_RPM_PM8058_LVS0 47
#define QCOM_RPM_PM8058_LVS1 48
#define QCOM_RPM_PM8058_NCP 49
#define QCOM_RPM_PM8058_SMPS0 50
#define QCOM_RPM_PM8058_SMPS1 51
#define QCOM_RPM_PM8058_SMPS2 52
#define QCOM_RPM_PM8058_SMPS3 53
#define QCOM_RPM_PM8058_SMPS4 54
#define QCOM_RPM_PM8821_LDO1 55
#define QCOM_RPM_PM8821_SMPS1 56
#define QCOM_RPM_PM8821_SMPS2 57
#define QCOM_RPM_PM8901_LDO0 58
#define QCOM_RPM_PM8901_LDO1 59
#define QCOM_RPM_PM8901_LDO2 60
#define QCOM_RPM_PM8901_LDO3 61
#define QCOM_RPM_PM8901_LDO4 62
#define QCOM_RPM_PM8901_LDO5 63
#define QCOM_RPM_PM8901_LDO6 64
#define QCOM_RPM_PM8901_LVS0 65
#define QCOM_RPM_PM8901_LVS1 66
#define QCOM_RPM_PM8901_LVS2 67
#define QCOM_RPM_PM8901_LVS3 68
#define QCOM_RPM_PM8901_MVS 69
#define QCOM_RPM_PM8901_SMPS0 70
#define QCOM_RPM_PM8901_SMPS1 71
#define QCOM_RPM_PM8901_SMPS2 72
#define QCOM_RPM_PM8901_SMPS3 73
#define QCOM_RPM_PM8901_SMPS4 74
#define QCOM_RPM_PM8921_CLK1 75
#define QCOM_RPM_PM8921_CLK2 76
#define QCOM_RPM_PM8921_LDO1 77
#define QCOM_RPM_PM8921_LDO2 78
#define QCOM_RPM_PM8921_LDO3 79
#define QCOM_RPM_PM8921_LDO4 80
#define QCOM_RPM_PM8921_LDO5 81
#define QCOM_RPM_PM8921_LDO6 82
#define QCOM_RPM_PM8921_LDO7 83
#define QCOM_RPM_PM8921_LDO8 84
#define QCOM_RPM_PM8921_LDO9 85
#define QCOM_RPM_PM8921_LDO10 86
#define QCOM_RPM_PM8921_LDO11 87
#define QCOM_RPM_PM8921_LDO12 88
#define QCOM_RPM_PM8921_LDO13 89
#define QCOM_RPM_PM8921_LDO14 90
#define QCOM_RPM_PM8921_LDO15 91
#define QCOM_RPM_PM8921_LDO16 92
#define QCOM_RPM_PM8921_LDO17 93
#define QCOM_RPM_PM8921_LDO18 94
#define QCOM_RPM_PM8921_LDO19 95
#define QCOM_RPM_PM8921_LDO20 96
#define QCOM_RPM_PM8921_LDO21 97
#define QCOM_RPM_PM8921_LDO22 98
#define QCOM_RPM_PM8921_LDO23 99
#define QCOM_RPM_PM8921_LDO24 100
#define QCOM_RPM_PM8921_LDO25 101
#define QCOM_RPM_PM8921_LDO26 102
#define QCOM_RPM_PM8921_LDO27 103
#define QCOM_RPM_PM8921_LDO28 104
#define QCOM_RPM_PM8921_LDO29 105
#define QCOM_RPM_PM8921_LVS1 106
#define QCOM_RPM_PM8921_LVS2 107
#define QCOM_RPM_PM8921_LVS3 108
#define QCOM_RPM_PM8921_LVS4 109
#define QCOM_RPM_PM8921_LVS5 110
#define QCOM_RPM_PM8921_LVS6 111
#define QCOM_RPM_PM8921_LVS7 112
#define QCOM_RPM_PM8921_MVS 113
#define QCOM_RPM_PM8921_NCP 114
#define QCOM_RPM_PM8921_SMPS1 115
#define QCOM_RPM_PM8921_SMPS2 116
#define QCOM_RPM_PM8921_SMPS3 117
#define QCOM_RPM_PM8921_SMPS4 118
#define QCOM_RPM_PM8921_SMPS5 119
#define QCOM_RPM_PM8921_SMPS6 120
#define QCOM_RPM_PM8921_SMPS7 121
#define QCOM_RPM_PM8921_SMPS8 122
#define QCOM_RPM_PXO_CLK 123
#define QCOM_RPM_QDSS_CLK 124
#define QCOM_RPM_SFPB_CLK 125
#define QCOM_RPM_SMI_CLK 126
#define QCOM_RPM_SYS_FABRIC_ARB 127
#define QCOM_RPM_SYS_FABRIC_CLK 128
#define QCOM_RPM_SYS_FABRIC_HALT 129
#define QCOM_RPM_SYS_FABRIC_IOCTL 130
#define QCOM_RPM_SYS_FABRIC_MODE 131
#define QCOM_RPM_USB_OTG_SWITCH 132
#define QCOM_RPM_VDDMIN_GPIO 133
/*
* Constants used to select force mode for regulators.
*/
#define QCOM_RPM_FORCE_MODE_NONE 0
#define QCOM_RPM_FORCE_MODE_LPM 1
#define QCOM_RPM_FORCE_MODE_HPM 2
#define QCOM_RPM_FORCE_MODE_AUTO 3
#define QCOM_RPM_FORCE_MODE_BYPASS 4
#endif
include/linux/mfd/axp20x.h
View file @ 5c277007
......@@ -124,10 +124,27 @@ enum {
#define AXP288_PMIC_ADC_H 0x56
#define AXP288_PMIC_ADC_L 0x57
#define AXP288_ADC_TS_PIN_CTRL 0x84
#define AXP288_PMIC_ADC_EN 0x84
#define AXP288_FG_TUNE5 0xed
/* Fuel Gauge */
#define AXP288_FG_RDC1_REG 0xba
#define AXP288_FG_RDC0_REG 0xbb
#define AXP288_FG_OCVH_REG 0xbc
#define AXP288_FG_OCVL_REG 0xbd
#define AXP288_FG_OCV_CURVE_REG 0xc0
#define AXP288_FG_DES_CAP1_REG 0xe0
#define AXP288_FG_DES_CAP0_REG 0xe1
#define AXP288_FG_CC_MTR1_REG 0xe2
#define AXP288_FG_CC_MTR0_REG 0xe3
#define AXP288_FG_OCV_CAP_REG 0xe4
#define AXP288_FG_CC_CAP_REG 0xe5
#define AXP288_FG_LOW_CAP_REG 0xe6
#define AXP288_FG_TUNE0 0xe8
#define AXP288_FG_TUNE1 0xe9
#define AXP288_FG_TUNE2 0xea
#define AXP288_FG_TUNE3 0xeb
#define AXP288_FG_TUNE4 0xec
#define AXP288_FG_TUNE5 0xed
/* Regulators IDs */
enum {
......@@ -236,4 +253,26 @@ struct axp20x_dev {
const struct regmap_irq_chip *regmap_irq_chip;
};
#define BATTID_LEN 64
#define OCV_CURVE_SIZE 32
#define MAX_THERM_CURVE_SIZE 25
#define PD_DEF_MIN_TEMP 0
#define PD_DEF_MAX_TEMP 55
struct axp20x_fg_pdata {
char battid[BATTID_LEN + 1];
int design_cap;
int min_volt;
int max_volt;
int max_temp;
int min_temp;
int cap1;
int cap0;
int rdc1;
int rdc0;
int ocv_curve[OCV_CURVE_SIZE];
int tcsz;
int thermistor_curve[MAX_THERM_CURVE_SIZE][2];
};
#endif /* __LINUX_MFD_AXP20X_H */
include/linux/mfd/da9063/core.h
View file @ 5c277007
......@@ -36,6 +36,7 @@ enum da9063_models {
enum da9063_variant_codes {
PMIC_DA9063_AD = 0x3,
PMIC_DA9063_BB = 0x5,
PMIC_DA9063_CA = 0x6,
};
/* Interrupts */
......
include/linux/mfd/da9150/core.h 0 → 100644
View file @ 5c277007
/*
* DA9150 MFD Driver - Core Data
*
* Copyright (c) 2014 Dialog Semiconductor
*
* Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __DA9150_CORE_H
#define __DA9150_CORE_H
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/regmap.h>
/* I2C address paging */
#define DA9150_REG_PAGE_SHIFT 8
#define DA9150_REG_PAGE_MASK 0xFF
/* IRQs */
#define DA9150_NUM_IRQ_REGS 4
#define DA9150_IRQ_VBUS 0
#define DA9150_IRQ_CHG 1
#define DA9150_IRQ_TCLASS 2
#define DA9150_IRQ_TJUNC 3
#define DA9150_IRQ_VFAULT 4
#define DA9150_IRQ_CONF 5
#define DA9150_IRQ_DAT 6
#define DA9150_IRQ_DTYPE 7
#define DA9150_IRQ_ID 8
#define DA9150_IRQ_ADP 9
#define DA9150_IRQ_SESS_END 10
#define DA9150_IRQ_SESS_VLD 11
#define DA9150_IRQ_FG 12
#define DA9150_IRQ_GP 13
#define DA9150_IRQ_TBAT 14
#define DA9150_IRQ_GPIOA 15
#define DA9150_IRQ_GPIOB 16
#define DA9150_IRQ_GPIOC 17
#define DA9150_IRQ_GPIOD 18
#define DA9150_IRQ_GPADC 19
#define DA9150_IRQ_WKUP 20
struct da9150_pdata {
int irq_base;
};
struct da9150 {
struct device *dev;
struct regmap *regmap;
struct regmap_irq_chip_data *regmap_irq_data;
int irq;
int irq_base;
};
/* Device I/O */
u8 da9150_reg_read(struct da9150 *da9150, u16 reg);
void da9150_reg_write(struct da9150 *da9150, u16 reg, u8 val);
void da9150_set_bits(struct da9150 *da9150, u16 reg, u8 mask, u8 val);
void da9150_bulk_read(struct da9150 *da9150, u16 reg, int count, u8 *buf);
void da9150_bulk_write(struct da9150 *da9150, u16 reg, int count, const u8 *buf);
#endif /* __DA9150_CORE_H */
include/linux/mfd/da9150/registers.h 0 → 100644
View file @ 5c277007
/*
* DA9150 MFD Driver - Registers
*
* Copyright (c) 2014 Dialog Semiconductor
*
* Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __DA9150_REGISTERS_H
#define __DA9150_REGISTERS_H
#include <linux/bitops.h>
/* Registers */
#define DA9150_PAGE_CON 0x000
#define DA9150_STATUS_A 0x068
#define DA9150_STATUS_B 0x069
#define DA9150_STATUS_C 0x06A
#define DA9150_STATUS_D 0x06B
#define DA9150_STATUS_E 0x06C
#define DA9150_STATUS_F 0x06D
#define DA9150_STATUS_G 0x06E
#define DA9150_STATUS_H 0x06F
#define DA9150_STATUS_I 0x070
#define DA9150_STATUS_J 0x071
#define DA9150_STATUS_K 0x072
#define DA9150_STATUS_L 0x073
#define DA9150_STATUS_N 0x074
#define DA9150_FAULT_LOG_A 0x076
#define DA9150_FAULT_LOG_B 0x077
#define DA9150_EVENT_E 0x078
#define DA9150_EVENT_F 0x079
#define DA9150_EVENT_G 0x07A
#define DA9150_EVENT_H 0x07B
#define DA9150_IRQ_MASK_E 0x07C
#define DA9150_IRQ_MASK_F 0x07D
#define DA9150_IRQ_MASK_G 0x07E
#define DA9150_IRQ_MASK_H 0x07F
#define DA9150_PAGE_CON_1 0x080
#define DA9150_CONFIG_A 0x0E0
#define DA9150_CONFIG_B 0x0E1
#define DA9150_CONFIG_C 0x0E2
#define DA9150_CONFIG_D 0x0E3
#define DA9150_CONFIG_E 0x0E4
#define DA9150_CONTROL_A 0x0E5
#define DA9150_CONTROL_B 0x0E6
#define DA9150_CONTROL_C 0x0E7
#define DA9150_GPIO_A_B 0x0E8
#define DA9150_GPIO_C_D 0x0E9
#define DA9150_GPIO_MODE_CONT 0x0EA
#define DA9150_GPIO_CTRL_B 0x0EB
#define DA9150_GPIO_CTRL_A 0x0EC
#define DA9150_GPIO_CTRL_C 0x0ED
#define DA9150_GPIO_CFG_A 0x0EE
#define DA9150_GPIO_CFG_B 0x0EF
#define DA9150_GPIO_CFG_C 0x0F0
#define DA9150_GPADC_MAN 0x0F2
#define DA9150_GPADC_RES_A 0x0F4
#define DA9150_GPADC_RES_B 0x0F5
#define DA9150_PAGE_CON_2 0x100
#define DA9150_OTP_CONT_SHARED 0x101
#define DA9150_INTERFACE_SHARED 0x105
#define DA9150_CONFIG_A_SHARED 0x106
#define DA9150_CONFIG_D_SHARED 0x109
#define DA9150_ADETVB_CFG_C 0x150
#define DA9150_ADETD_STAT 0x151
#define DA9150_ADET_CMPSTAT 0x152
#define DA9150_ADET_CTRL_A 0x153
#define DA9150_ADETVB_CFG_B 0x154
#define DA9150_ADETVB_CFG_A 0x155
#define DA9150_ADETAC_CFG_A 0x156
#define DA9150_ADDETAC_CFG_B 0x157
#define DA9150_ADETAC_CFG_C 0x158
#define DA9150_ADETAC_CFG_D 0x159
#define DA9150_ADETVB_CFG_D 0x15A
#define DA9150_ADETID_CFG_A 0x15B
#define DA9150_ADET_RID_PT_CHG_H 0x15C
#define DA9150_ADET_RID_PT_CHG_L 0x15D
#define DA9150_PPR_TCTR_B 0x160
#define DA9150_PPR_BKCTRL_A 0x163
#define DA9150_PPR_BKCFG_A 0x164
#define DA9150_PPR_BKCFG_B 0x165
#define DA9150_PPR_CHGCTRL_A 0x166
#define DA9150_PPR_CHGCTRL_B 0x167
#define DA9150_PPR_CHGCTRL_C 0x168
#define DA9150_PPR_TCTR_A 0x169
#define DA9150_PPR_CHGCTRL_D 0x16A
#define DA9150_PPR_CHGCTRL_E 0x16B
#define DA9150_PPR_CHGCTRL_F 0x16C
#define DA9150_PPR_CHGCTRL_G 0x16D
#define DA9150_PPR_CHGCTRL_H 0x16E
#define DA9150_PPR_CHGCTRL_I 0x16F
#define DA9150_PPR_CHGCTRL_J 0x170
#define DA9150_PPR_CHGCTRL_K 0x171
#define DA9150_PPR_CHGCTRL_L 0x172
#define DA9150_PPR_CHGCTRL_M 0x173
#define DA9150_PPR_THYST_A 0x174
#define DA9150_PPR_THYST_B 0x175
#define DA9150_PPR_THYST_C 0x176
#define DA9150_PPR_THYST_D 0x177
#define DA9150_PPR_THYST_E 0x178
#define DA9150_PPR_THYST_F 0x179
#define DA9150_PPR_THYST_G 0x17A
#define DA9150_PAGE_CON_3 0x180
#define DA9150_PAGE_CON_4 0x200
#define DA9150_PAGE_CON_5 0x280
#define DA9150_PAGE_CON_6 0x300
#define DA9150_COREBTLD_STAT_A 0x302
#define DA9150_COREBTLD_CTRL_A 0x303
#define DA9150_CORE_CONFIG_A 0x304
#define DA9150_CORE_CONFIG_C 0x305
#define DA9150_CORE_CONFIG_B 0x306
#define DA9150_CORE_CFG_DATA_A 0x307
#define DA9150_CORE_CFG_DATA_B 0x308
#define DA9150_CORE_CMD_A 0x309
#define DA9150_CORE_DATA_A 0x30A
#define DA9150_CORE_DATA_B 0x30B
#define DA9150_CORE_DATA_C 0x30C
#define DA9150_CORE_DATA_D 0x30D
#define DA9150_CORE2WIRE_STAT_A 0x310
#define DA9150_CORE2WIRE_CTRL_A 0x311
#define DA9150_FW_CTRL_A 0x312
#define DA9150_FW_CTRL_C 0x313
#define DA9150_FW_CTRL_D 0x314
#define DA9150_FG_CTRL_A 0x315
#define DA9150_FG_CTRL_B 0x316
#define DA9150_FW_CTRL_E 0x317
#define DA9150_FW_CTRL_B 0x318
#define DA9150_GPADC_CMAN 0x320
#define DA9150_GPADC_CRES_A 0x322
#define DA9150_GPADC_CRES_B 0x323
#define DA9150_CC_CFG_A 0x328
#define DA9150_CC_CFG_B 0x329
#define DA9150_CC_ICHG_RES_A 0x32A
#define DA9150_CC_ICHG_RES_B 0x32B
#define DA9150_CC_IAVG_RES_A 0x32C
#define DA9150_CC_IAVG_RES_B 0x32D
#define DA9150_TAUX_CTRL_A 0x330
#define DA9150_TAUX_RELOAD_H 0x332
#define DA9150_TAUX_RELOAD_L 0x333
#define DA9150_TAUX_VALUE_H 0x334
#define DA9150_TAUX_VALUE_L 0x335
#define DA9150_AUX_DATA_0 0x338
#define DA9150_AUX_DATA_1 0x339
#define DA9150_AUX_DATA_2 0x33A
#define DA9150_AUX_DATA_3 0x33B
#define DA9150_BIF_CTRL 0x340
#define DA9150_TBAT_CTRL_A 0x342
#define DA9150_TBAT_CTRL_B 0x343
#define DA9150_TBAT_RES_A 0x344
#define DA9150_TBAT_RES_B 0x345
/* DA9150_PAGE_CON = 0x000 */
#define DA9150_PAGE_SHIFT 0
#define DA9150_PAGE_MASK (0x3f << 0)
#define DA9150_I2C_PAGE_SHIFT 1
#define DA9150_I2C_PAGE_MASK (0x1f << 1)
#define DA9150_WRITE_MODE_SHIFT 6
#define DA9150_WRITE_MODE_MASK BIT(6)
#define DA9150_REVERT_SHIFT 7
#define DA9150_REVERT_MASK BIT(7)
/* DA9150_STATUS_A = 0x068 */
#define DA9150_WKUP_STAT_SHIFT 2
#define DA9150_WKUP_STAT_MASK (0x0f << 2)
#define DA9150_SLEEP_STAT_SHIFT 6
#define DA9150_SLEEP_STAT_MASK (0x03 << 6)
/* DA9150_STATUS_B = 0x069 */
#define DA9150_VFAULT_STAT_SHIFT 0
#define DA9150_VFAULT_STAT_MASK BIT(0)
#define DA9150_TFAULT_STAT_SHIFT 1
#define DA9150_TFAULT_STAT_MASK BIT(1)
/* DA9150_STATUS_C = 0x06A */
#define DA9150_VDD33_STAT_SHIFT 0
#define DA9150_VDD33_STAT_MASK BIT(0)
#define DA9150_VDD33_SLEEP_SHIFT 1
#define DA9150_VDD33_SLEEP_MASK BIT(1)
#define DA9150_LFOSC_STAT_SHIFT 7
#define DA9150_LFOSC_STAT_MASK BIT(7)
/* DA9150_STATUS_D = 0x06B */
#define DA9150_GPIOA_STAT_SHIFT 0
#define DA9150_GPIOA_STAT_MASK BIT(0)
#define DA9150_GPIOB_STAT_SHIFT 1
#define DA9150_GPIOB_STAT_MASK BIT(1)
#define DA9150_GPIOC_STAT_SHIFT 2
#define DA9150_GPIOC_STAT_MASK BIT(2)
#define DA9150_GPIOD_STAT_SHIFT 3
#define DA9150_GPIOD_STAT_MASK BIT(3)
/* DA9150_STATUS_E = 0x06C */
#define DA9150_DTYPE_SHIFT 0
#define DA9150_DTYPE_MASK (0x1f << 0)
#define DA9150_DTYPE_DT_NIL (0x00 << 0)
#define DA9150_DTYPE_DT_USB_OTG BIT(0)
#define DA9150_DTYPE_DT_USB_STD (0x02 << 0)
#define DA9150_DTYPE_DT_USB_CHG (0x03 << 0)
#define DA9150_DTYPE_DT_ACA_CHG (0x04 << 0)
#define DA9150_DTYPE_DT_ACA_OTG (0x05 << 0)
#define DA9150_DTYPE_DT_ACA_DOC (0x06 << 0)
#define DA9150_DTYPE_DT_DED_CHG (0x07 << 0)
#define DA9150_DTYPE_DT_CR5_CHG (0x08 << 0)
#define DA9150_DTYPE_DT_CR4_CHG (0x0c << 0)
#define DA9150_DTYPE_DT_PT_CHG (0x11 << 0)
#define DA9150_DTYPE_DT_NN_ACC (0x16 << 0)
#define DA9150_DTYPE_DT_NN_CHG (0x17 << 0)
/* DA9150_STATUS_F = 0x06D */
#define DA9150_SESS_VLD_SHIFT 0
#define DA9150_SESS_VLD_MASK BIT(0)
#define DA9150_ID_ERR_SHIFT 1
#define DA9150_ID_ERR_MASK BIT(1)
#define DA9150_PT_CHG_SHIFT 2
#define DA9150_PT_CHG_MASK BIT(2)
/* DA9150_STATUS_G = 0x06E */
#define DA9150_RID_SHIFT 0
#define DA9150_RID_MASK (0xff << 0)
/* DA9150_STATUS_H = 0x06F */
#define DA9150_VBUS_STAT_SHIFT 0
#define DA9150_VBUS_STAT_MASK (0x07 << 0)
#define DA9150_VBUS_STAT_OFF (0x00 << 0)
#define DA9150_VBUS_STAT_WAIT BIT(0)
#define DA9150_VBUS_STAT_CHG (0x02 << 0)
#define DA9150_VBUS_TRED_SHIFT 3
#define DA9150_VBUS_TRED_MASK BIT(3)
#define DA9150_VBUS_DROP_STAT_SHIFT 4
#define DA9150_VBUS_DROP_STAT_MASK (0x0f << 4)
/* DA9150_STATUS_I = 0x070 */
#define DA9150_VBUS_ISET_STAT_SHIFT 0
#define DA9150_VBUS_ISET_STAT_MASK (0x1f << 0)
#define DA9150_VBUS_OT_SHIFT 7
#define DA9150_VBUS_OT_MASK BIT(7)
/* DA9150_STATUS_J = 0x071 */
#define DA9150_CHG_STAT_SHIFT 0
#define DA9150_CHG_STAT_MASK (0x0f << 0)
#define DA9150_CHG_STAT_OFF (0x00 << 0)
#define DA9150_CHG_STAT_SUSP BIT(0)
#define DA9150_CHG_STAT_ACT (0x02 << 0)
#define DA9150_CHG_STAT_PRE (0x03 << 0)
#define DA9150_CHG_STAT_CC (0x04 << 0)
#define DA9150_CHG_STAT_CV (0x05 << 0)
#define DA9150_CHG_STAT_FULL (0x06 << 0)
#define DA9150_CHG_STAT_TEMP (0x07 << 0)
#define DA9150_CHG_STAT_TIME (0x08 << 0)
#define DA9150_CHG_STAT_BAT (0x09 << 0)
#define DA9150_CHG_TEMP_SHIFT 4
#define DA9150_CHG_TEMP_MASK (0x07 << 4)
#define DA9150_CHG_TEMP_UNDER (0x06 << 4)
#define DA9150_CHG_TEMP_OVER (0x07 << 4)
#define DA9150_CHG_IEND_STAT_SHIFT 7
#define DA9150_CHG_IEND_STAT_MASK BIT(7)
/* DA9150_STATUS_K = 0x072 */
#define DA9150_CHG_IAV_H_SHIFT 0
#define DA9150_CHG_IAV_H_MASK (0xff << 0)
/* DA9150_STATUS_L = 0x073 */
#define DA9150_CHG_IAV_L_SHIFT 5
#define DA9150_CHG_IAV_L_MASK (0x07 << 5)
/* DA9150_STATUS_N = 0x074 */
#define DA9150_CHG_TIME_SHIFT 1
#define DA9150_CHG_TIME_MASK BIT(1)
#define DA9150_CHG_TRED_SHIFT 2
#define DA9150_CHG_TRED_MASK BIT(2)
#define DA9150_CHG_TJUNC_CLASS_SHIFT 3
#define DA9150_CHG_TJUNC_CLASS_MASK (0x07 << 3)
#define DA9150_CHG_TJUNC_CLASS_6 (0x06 << 3)
#define DA9150_EBS_STAT_SHIFT 6
#define DA9150_EBS_STAT_MASK BIT(6)
#define DA9150_CHG_BAT_REMOVED_SHIFT 7
#define DA9150_CHG_BAT_REMOVED_MASK BIT(7)
/* DA9150_FAULT_LOG_A = 0x076 */
#define DA9150_TEMP_FAULT_SHIFT 0
#define DA9150_TEMP_FAULT_MASK BIT(0)
#define DA9150_VSYS_FAULT_SHIFT 1
#define DA9150_VSYS_FAULT_MASK BIT(1)
#define DA9150_START_FAULT_SHIFT 2
#define DA9150_START_FAULT_MASK BIT(2)
#define DA9150_EXT_FAULT_SHIFT 3
#define DA9150_EXT_FAULT_MASK BIT(3)
#define DA9150_POR_FAULT_SHIFT 4
#define DA9150_POR_FAULT_MASK BIT(4)
/* DA9150_FAULT_LOG_B = 0x077 */
#define DA9150_VBUS_FAULT_SHIFT 0
#define DA9150_VBUS_FAULT_MASK BIT(0)
#define DA9150_OTG_FAULT_SHIFT 1
#define DA9150_OTG_FAULT_MASK BIT(1)
/* DA9150_EVENT_E = 0x078 */
#define DA9150_E_VBUS_SHIFT 0
#define DA9150_E_VBUS_MASK BIT(0)
#define DA9150_E_CHG_SHIFT 1
#define DA9150_E_CHG_MASK BIT(1)
#define DA9150_E_TCLASS_SHIFT 2
#define DA9150_E_TCLASS_MASK BIT(2)
#define DA9150_E_TJUNC_SHIFT 3
#define DA9150_E_TJUNC_MASK BIT(3)
#define DA9150_E_VFAULT_SHIFT 4
#define DA9150_E_VFAULT_MASK BIT(4)
#define DA9150_EVENTS_H_SHIFT 5
#define DA9150_EVENTS_H_MASK BIT(5)
#define DA9150_EVENTS_G_SHIFT 6
#define DA9150_EVENTS_G_MASK BIT(6)
#define DA9150_EVENTS_F_SHIFT 7
#define DA9150_EVENTS_F_MASK BIT(7)
/* DA9150_EVENT_F = 0x079 */
#define DA9150_E_CONF_SHIFT 0
#define DA9150_E_CONF_MASK BIT(0)
#define DA9150_E_DAT_SHIFT 1
#define DA9150_E_DAT_MASK BIT(1)
#define DA9150_E_DTYPE_SHIFT 3
#define DA9150_E_DTYPE_MASK BIT(3)
#define DA9150_E_ID_SHIFT 4
#define DA9150_E_ID_MASK BIT(4)
#define DA9150_E_ADP_SHIFT 5
#define DA9150_E_ADP_MASK BIT(5)
#define DA9150_E_SESS_END_SHIFT 6
#define DA9150_E_SESS_END_MASK BIT(6)
#define DA9150_E_SESS_VLD_SHIFT 7
#define DA9150_E_SESS_VLD_MASK BIT(7)
/* DA9150_EVENT_G = 0x07A */
#define DA9150_E_FG_SHIFT 0
#define DA9150_E_FG_MASK BIT(0)
#define DA9150_E_GP_SHIFT 1
#define DA9150_E_GP_MASK BIT(1)
#define DA9150_E_TBAT_SHIFT 2
#define DA9150_E_TBAT_MASK BIT(2)
#define DA9150_E_GPIOA_SHIFT 3
#define DA9150_E_GPIOA_MASK BIT(3)
#define DA9150_E_GPIOB_SHIFT 4
#define DA9150_E_GPIOB_MASK BIT(4)
#define DA9150_E_GPIOC_SHIFT 5
#define DA9150_E_GPIOC_MASK BIT(5)
#define DA9150_E_GPIOD_SHIFT 6
#define DA9150_E_GPIOD_MASK BIT(6)
#define DA9150_E_GPADC_SHIFT 7
#define DA9150_E_GPADC_MASK BIT(7)
/* DA9150_EVENT_H = 0x07B */
#define DA9150_E_WKUP_SHIFT 0
#define DA9150_E_WKUP_MASK BIT(0)
/* DA9150_IRQ_MASK_E = 0x07C */
#define DA9150_M_VBUS_SHIFT 0
#define DA9150_M_VBUS_MASK BIT(0)
#define DA9150_M_CHG_SHIFT 1
#define DA9150_M_CHG_MASK BIT(1)
#define DA9150_M_TJUNC_SHIFT 3
#define DA9150_M_TJUNC_MASK BIT(3)
#define DA9150_M_VFAULT_SHIFT 4
#define DA9150_M_VFAULT_MASK BIT(4)
/* DA9150_IRQ_MASK_F = 0x07D */
#define DA9150_M_CONF_SHIFT 0
#define DA9150_M_CONF_MASK BIT(0)
#define DA9150_M_DAT_SHIFT 1
#define DA9150_M_DAT_MASK BIT(1)
#define DA9150_M_DTYPE_SHIFT 3
#define DA9150_M_DTYPE_MASK BIT(3)
#define DA9150_M_ID_SHIFT 4
#define DA9150_M_ID_MASK BIT(4)
#define DA9150_M_ADP_SHIFT 5
#define DA9150_M_ADP_MASK BIT(5)
#define DA9150_M_SESS_END_SHIFT 6
#define DA9150_M_SESS_END_MASK BIT(6)
#define DA9150_M_SESS_VLD_SHIFT 7
#define DA9150_M_SESS_VLD_MASK BIT(7)
/* DA9150_IRQ_MASK_G = 0x07E */
#define DA9150_M_FG_SHIFT 0
#define DA9150_M_FG_MASK BIT(0)
#define DA9150_M_GP_SHIFT 1
#define DA9150_M_GP_MASK BIT(1)
#define DA9150_M_TBAT_SHIFT 2
#define DA9150_M_TBAT_MASK BIT(2)
#define DA9150_M_GPIOA_SHIFT 3
#define DA9150_M_GPIOA_MASK BIT(3)
#define DA9150_M_GPIOB_SHIFT 4
#define DA9150_M_GPIOB_MASK BIT(4)
#define DA9150_M_GPIOC_SHIFT 5
#define DA9150_M_GPIOC_MASK BIT(5)
#define DA9150_M_GPIOD_SHIFT 6
#define DA9150_M_GPIOD_MASK BIT(6)
#define DA9150_M_GPADC_SHIFT 7
#define DA9150_M_GPADC_MASK BIT(7)
/* DA9150_IRQ_MASK_H = 0x07F */
#define DA9150_M_WKUP_SHIFT 0
#define DA9150_M_WKUP_MASK BIT(0)
/* DA9150_PAGE_CON_1 = 0x080 */
#define DA9150_PAGE_SHIFT 0
#define DA9150_PAGE_MASK (0x3f << 0)
#define DA9150_WRITE_MODE_SHIFT 6
#define DA9150_WRITE_MODE_MASK BIT(6)
#define DA9150_REVERT_SHIFT 7
#define DA9150_REVERT_MASK BIT(7)
/* DA9150_CONFIG_A = 0x0E0 */
#define DA9150_RESET_DUR_SHIFT 0
#define DA9150_RESET_DUR_MASK (0x03 << 0)
#define DA9150_RESET_EXT_SHIFT 2
#define DA9150_RESET_EXT_MASK (0x03 << 2)
#define DA9150_START_MAX_SHIFT 4
#define DA9150_START_MAX_MASK (0x03 << 4)
#define DA9150_PS_WAIT_EN_SHIFT 6
#define DA9150_PS_WAIT_EN_MASK BIT(6)
#define DA9150_PS_DISABLE_DIRECT_SHIFT 7
#define DA9150_PS_DISABLE_DIRECT_MASK BIT(7)
/* DA9150_CONFIG_B = 0x0E1 */
#define DA9150_VFAULT_ADJ_SHIFT 0
#define DA9150_VFAULT_ADJ_MASK (0x0f << 0)
#define DA9150_VFAULT_HYST_SHIFT 4
#define DA9150_VFAULT_HYST_MASK (0x07 << 4)
#define DA9150_VFAULT_EN_SHIFT 7
#define DA9150_VFAULT_EN_MASK BIT(7)
/* DA9150_CONFIG_C = 0x0E2 */
#define DA9150_VSYS_MIN_SHIFT 3
#define DA9150_VSYS_MIN_MASK (0x1f << 3)
/* DA9150_CONFIG_D = 0x0E3 */
#define DA9150_LFOSC_EXT_SHIFT 0
#define DA9150_LFOSC_EXT_MASK BIT(0)
#define DA9150_VDD33_DWN_SHIFT 1
#define DA9150_VDD33_DWN_MASK BIT(1)
#define DA9150_WKUP_PM_EN_SHIFT 2
#define DA9150_WKUP_PM_EN_MASK BIT(2)
#define DA9150_WKUP_CE_SEL_SHIFT 3
#define DA9150_WKUP_CE_SEL_MASK (0x03 << 3)
#define DA9150_WKUP_CLK32K_EN_SHIFT 5
#define DA9150_WKUP_CLK32K_EN_MASK BIT(5)
#define DA9150_DISABLE_DEL_SHIFT 7
#define DA9150_DISABLE_DEL_MASK BIT(7)
/* DA9150_CONFIG_E = 0x0E4 */
#define DA9150_PM_SPKSUP_DIS_SHIFT 0
#define DA9150_PM_SPKSUP_DIS_MASK BIT(0)
#define DA9150_PM_MERGE_SHIFT 1
#define DA9150_PM_MERGE_MASK BIT(1)
#define DA9150_PM_SR_OFF_SHIFT 2
#define DA9150_PM_SR_OFF_MASK BIT(2)
#define DA9150_PM_TIMEOUT_EN_SHIFT 3
#define DA9150_PM_TIMEOUT_EN_MASK BIT(3)
#define DA9150_PM_DLY_SEL_SHIFT 4
#define DA9150_PM_DLY_SEL_MASK (0x07 << 4)
#define DA9150_PM_OUT_DLY_SEL_SHIFT 7
#define DA9150_PM_OUT_DLY_SEL_MASK BIT(7)
/* DA9150_CONTROL_A = 0x0E5 */
#define DA9150_VDD33_SL_SHIFT 0
#define DA9150_VDD33_SL_MASK BIT(0)
#define DA9150_VDD33_LPM_SHIFT 1
#define DA9150_VDD33_LPM_MASK (0x03 << 1)
#define DA9150_VDD33_EN_SHIFT 3
#define DA9150_VDD33_EN_MASK BIT(3)
#define DA9150_GPI_LPM_SHIFT 6
#define DA9150_GPI_LPM_MASK BIT(6)
#define DA9150_PM_IF_LPM_SHIFT 7
#define DA9150_PM_IF_LPM_MASK BIT(7)
/* DA9150_CONTROL_B = 0x0E6 */
#define DA9150_LPM_SHIFT 0
#define DA9150_LPM_MASK BIT(0)
#define DA9150_RESET_SHIFT 1
#define DA9150_RESET_MASK BIT(1)
#define DA9150_RESET_USRCONF_EN_SHIFT 2
#define DA9150_RESET_USRCONF_EN_MASK BIT(2)
/* DA9150_CONTROL_C = 0x0E7 */
#define DA9150_DISABLE_SHIFT 0
#define DA9150_DISABLE_MASK BIT(0)
/* DA9150_GPIO_A_B = 0x0E8 */
#define DA9150_GPIOA_PIN_SHIFT 0
#define DA9150_GPIOA_PIN_MASK (0x07 << 0)
#define DA9150_GPIOA_PIN_GPI (0x00 << 0)
#define DA9150_GPIOA_PIN_GPO_OD BIT(0)
#define DA9150_GPIOA_TYPE_SHIFT 3
#define DA9150_GPIOA_TYPE_MASK BIT(3)
#define DA9150_GPIOB_PIN_SHIFT 4
#define DA9150_GPIOB_PIN_MASK (0x07 << 4)
#define DA9150_GPIOB_PIN_GPI (0x00 << 4)
#define DA9150_GPIOB_PIN_GPO_OD BIT(4)
#define DA9150_GPIOB_TYPE_SHIFT 7
#define DA9150_GPIOB_TYPE_MASK BIT(7)
/* DA9150_GPIO_C_D = 0x0E9 */
#define DA9150_GPIOC_PIN_SHIFT 0
#define DA9150_GPIOC_PIN_MASK (0x07 << 0)
#define DA9150_GPIOC_PIN_GPI (0x00 << 0)
#define DA9150_GPIOC_PIN_GPO_OD BIT(0)
#define DA9150_GPIOC_TYPE_SHIFT 3
#define DA9150_GPIOC_TYPE_MASK BIT(3)
#define DA9150_GPIOD_PIN_SHIFT 4
#define DA9150_GPIOD_PIN_MASK (0x07 << 4)
#define DA9150_GPIOD_PIN_GPI (0x00 << 4)
#define DA9150_GPIOD_PIN_GPO_OD BIT(4)
#define DA9150_GPIOD_TYPE_SHIFT 7
#define DA9150_GPIOD_TYPE_MASK BIT(7)
/* DA9150_GPIO_MODE_CONT = 0x0EA */
#define DA9150_GPIOA_MODE_SHIFT 0
#define DA9150_GPIOA_MODE_MASK BIT(0)
#define DA9150_GPIOB_MODE_SHIFT 1
#define DA9150_GPIOB_MODE_MASK BIT(1)
#define DA9150_GPIOC_MODE_SHIFT 2
#define DA9150_GPIOC_MODE_MASK BIT(2)
#define DA9150_GPIOD_MODE_SHIFT 3
#define DA9150_GPIOD_MODE_MASK BIT(3)
#define DA9150_GPIOA_CONT_SHIFT 4
#define DA9150_GPIOA_CONT_MASK BIT(4)
#define DA9150_GPIOB_CONT_SHIFT 5
#define DA9150_GPIOB_CONT_MASK BIT(5)
#define DA9150_GPIOC_CONT_SHIFT 6
#define DA9150_GPIOC_CONT_MASK BIT(6)
#define DA9150_GPIOD_CONT_SHIFT 7
#define DA9150_GPIOD_CONT_MASK BIT(7)
/* DA9150_GPIO_CTRL_B = 0x0EB */
#define DA9150_WAKE_PIN_SHIFT 0
#define DA9150_WAKE_PIN_MASK (0x03 << 0)
#define DA9150_WAKE_MODE_SHIFT 2
#define DA9150_WAKE_MODE_MASK BIT(2)
#define DA9150_WAKE_CONT_SHIFT 3
#define DA9150_WAKE_CONT_MASK BIT(3)
#define DA9150_WAKE_DLY_SHIFT 4
#define DA9150_WAKE_DLY_MASK BIT(4)
/* DA9150_GPIO_CTRL_A = 0x0EC */
#define DA9150_GPIOA_ANAEN_SHIFT 0
#define DA9150_GPIOA_ANAEN_MASK BIT(0)
#define DA9150_GPIOB_ANAEN_SHIFT 1
#define DA9150_GPIOB_ANAEN_MASK BIT(1)
#define DA9150_GPIOC_ANAEN_SHIFT 2
#define DA9150_GPIOC_ANAEN_MASK BIT(2)
#define DA9150_GPIOD_ANAEN_SHIFT 3
#define DA9150_GPIOD_ANAEN_MASK BIT(3)
#define DA9150_GPIO_ANAEN 0x01
#define DA9150_GPIO_ANAEN_MASK 0x0F
#define DA9150_CHGLED_PIN_SHIFT 5
#define DA9150_CHGLED_PIN_MASK (0x07 << 5)
/* DA9150_GPIO_CTRL_C = 0x0ED */
#define DA9150_CHGBL_DUR_SHIFT 0
#define DA9150_CHGBL_DUR_MASK (0x03 << 0)
#define DA9150_CHGBL_DBL_SHIFT 2
#define DA9150_CHGBL_DBL_MASK BIT(2)
#define DA9150_CHGBL_FRQ_SHIFT 3
#define DA9150_CHGBL_FRQ_MASK (0x03 << 3)
#define DA9150_CHGBL_FLKR_SHIFT 5
#define DA9150_CHGBL_FLKR_MASK BIT(5)
/* DA9150_GPIO_CFG_A = 0x0EE */
#define DA9150_CE_LPM_DEB_SHIFT 0
#define DA9150_CE_LPM_DEB_MASK (0x07 << 0)
/* DA9150_GPIO_CFG_B = 0x0EF */
#define DA9150_GPIOA_PUPD_SHIFT 0
#define DA9150_GPIOA_PUPD_MASK BIT(0)
#define DA9150_GPIOB_PUPD_SHIFT 1
#define DA9150_GPIOB_PUPD_MASK BIT(1)
#define DA9150_GPIOC_PUPD_SHIFT 2
#define DA9150_GPIOC_PUPD_MASK BIT(2)
#define DA9150_GPIOD_PUPD_SHIFT 3
#define DA9150_GPIOD_PUPD_MASK BIT(3)
#define DA9150_GPIO_PUPD_MASK (0xF << 0)
#define DA9150_GPI_DEB_SHIFT 4
#define DA9150_GPI_DEB_MASK (0x07 << 4)
#define DA9150_LPM_EN_SHIFT 7
#define DA9150_LPM_EN_MASK BIT(7)
/* DA9150_GPIO_CFG_C = 0x0F0 */
#define DA9150_GPI_V_SHIFT 0
#define DA9150_GPI_V_MASK BIT(0)
#define DA9150_VDDIO_INT_SHIFT 1
#define DA9150_VDDIO_INT_MASK BIT(1)
#define DA9150_FAULT_PIN_SHIFT 3
#define DA9150_FAULT_PIN_MASK (0x07 << 3)
#define DA9150_FAULT_TYPE_SHIFT 6
#define DA9150_FAULT_TYPE_MASK BIT(6)
#define DA9150_NIRQ_PUPD_SHIFT 7
#define DA9150_NIRQ_PUPD_MASK BIT(7)
/* DA9150_GPADC_MAN = 0x0F2 */
#define DA9150_GPADC_EN_SHIFT 0
#define DA9150_GPADC_EN_MASK BIT(0)
#define DA9150_GPADC_MUX_SHIFT 1
#define DA9150_GPADC_MUX_MASK (0x1f << 1)
/* DA9150_GPADC_RES_A = 0x0F4 */
#define DA9150_GPADC_RES_H_SHIFT 0
#define DA9150_GPADC_RES_H_MASK (0xff << 0)
/* DA9150_GPADC_RES_B = 0x0F5 */
#define DA9150_GPADC_RUN_SHIFT 0
#define DA9150_GPADC_RUN_MASK BIT(0)
#define DA9150_GPADC_RES_L_SHIFT 6
#define DA9150_GPADC_RES_L_MASK (0x03 << 6)
#define DA9150_GPADC_RES_L_BITS 2
/* DA9150_PAGE_CON_2 = 0x100 */
#define DA9150_PAGE_SHIFT 0
#define DA9150_PAGE_MASK (0x3f << 0)
#define DA9150_WRITE_MODE_SHIFT 6
#define DA9150_WRITE_MODE_MASK BIT(6)
#define DA9150_REVERT_SHIFT 7
#define DA9150_REVERT_MASK BIT(7)
/* DA9150_OTP_CONT_SHARED = 0x101 */
#define DA9150_PC_DONE_SHIFT 3
#define DA9150_PC_DONE_MASK BIT(3)
/* DA9150_INTERFACE_SHARED = 0x105 */
#define DA9150_IF_BASE_ADDR_SHIFT 4
#define DA9150_IF_BASE_ADDR_MASK (0x0f << 4)
/* DA9150_CONFIG_A_SHARED = 0x106 */
#define DA9150_NIRQ_VDD_SHIFT 1
#define DA9150_NIRQ_VDD_MASK BIT(1)
#define DA9150_NIRQ_PIN_SHIFT 2
#define DA9150_NIRQ_PIN_MASK BIT(2)
#define DA9150_NIRQ_TYPE_SHIFT 3
#define DA9150_NIRQ_TYPE_MASK BIT(3)
#define DA9150_PM_IF_V_SHIFT 4
#define DA9150_PM_IF_V_MASK BIT(4)
#define DA9150_PM_IF_FMP_SHIFT 5
#define DA9150_PM_IF_FMP_MASK BIT(5)
#define DA9150_PM_IF_HSM_SHIFT 6
#define DA9150_PM_IF_HSM_MASK BIT(6)
/* DA9150_CONFIG_D_SHARED = 0x109 */
#define DA9150_NIRQ_MODE_SHIFT 1
#define DA9150_NIRQ_MODE_MASK BIT(1)
/* DA9150_ADETVB_CFG_C = 0x150 */
#define DA9150_TADP_RISE_SHIFT 0
#define DA9150_TADP_RISE_MASK (0xff << 0)
/* DA9150_ADETD_STAT = 0x151 */
#define DA9150_DCD_STAT_SHIFT 0
#define DA9150_DCD_STAT_MASK BIT(0)
#define DA9150_PCD_STAT_SHIFT 1
#define DA9150_PCD_STAT_MASK (0x03 << 1)
#define DA9150_SCD_STAT_SHIFT 3
#define DA9150_SCD_STAT_MASK (0x03 << 3)
#define DA9150_DP_STAT_SHIFT 5
#define DA9150_DP_STAT_MASK BIT(5)
#define DA9150_DM_STAT_SHIFT 6
#define DA9150_DM_STAT_MASK BIT(6)
/* DA9150_ADET_CMPSTAT = 0x152 */
#define DA9150_DP_COMP_SHIFT 1
#define DA9150_DP_COMP_MASK BIT(1)
#define DA9150_DM_COMP_SHIFT 2
#define DA9150_DM_COMP_MASK BIT(2)
#define DA9150_ADP_SNS_COMP_SHIFT 3
#define DA9150_ADP_SNS_COMP_MASK BIT(3)
#define DA9150_ADP_PRB_COMP_SHIFT 4
#define DA9150_ADP_PRB_COMP_MASK BIT(4)
#define DA9150_ID_COMP_SHIFT 5
#define DA9150_ID_COMP_MASK BIT(5)
/* DA9150_ADET_CTRL_A = 0x153 */
#define DA9150_AID_DAT_SHIFT 0
#define DA9150_AID_DAT_MASK BIT(0)
#define DA9150_AID_ID_SHIFT 1
#define DA9150_AID_ID_MASK BIT(1)
#define DA9150_AID_TRIG_SHIFT 2
#define DA9150_AID_TRIG_MASK BIT(2)
/* DA9150_ADETVB_CFG_B = 0x154 */
#define DA9150_VB_MODE_SHIFT 0
#define DA9150_VB_MODE_MASK (0x03 << 0)
#define DA9150_VB_MODE_VB_SESS BIT(0)
#define DA9150_TADP_PRB_SHIFT 2
#define DA9150_TADP_PRB_MASK BIT(2)
#define DA9150_DAT_RPD_EXT_SHIFT 5
#define DA9150_DAT_RPD_EXT_MASK BIT(5)
#define DA9150_CONF_RPD_SHIFT 6
#define DA9150_CONF_RPD_MASK BIT(6)
#define DA9150_CONF_SRP_SHIFT 7
#define DA9150_CONF_SRP_MASK BIT(7)
/* DA9150_ADETVB_CFG_A = 0x155 */
#define DA9150_AID_MODE_SHIFT 0
#define DA9150_AID_MODE_MASK (0x03 << 0)
#define DA9150_AID_EXT_POL_SHIFT 2
#define DA9150_AID_EXT_POL_MASK BIT(2)
/* DA9150_ADETAC_CFG_A = 0x156 */
#define DA9150_ISET_CDP_SHIFT 0
#define DA9150_ISET_CDP_MASK (0x1f << 0)
#define DA9150_CONF_DBP_SHIFT 5
#define DA9150_CONF_DBP_MASK BIT(5)
/* DA9150_ADDETAC_CFG_B = 0x157 */
#define DA9150_ISET_DCHG_SHIFT 0
#define DA9150_ISET_DCHG_MASK (0x1f << 0)
#define DA9150_CONF_GPIOA_SHIFT 5
#define DA9150_CONF_GPIOA_MASK BIT(5)
#define DA9150_CONF_GPIOB_SHIFT 6
#define DA9150_CONF_GPIOB_MASK BIT(6)
#define DA9150_AID_VB_SHIFT 7
#define DA9150_AID_VB_MASK BIT(7)
/* DA9150_ADETAC_CFG_C = 0x158 */
#define DA9150_ISET_DEF_SHIFT 0
#define DA9150_ISET_DEF_MASK (0x1f << 0)
#define DA9150_CONF_MODE_SHIFT 5
#define DA9150_CONF_MODE_MASK (0x03 << 5)
#define DA9150_AID_CR_DIS_SHIFT 7
#define DA9150_AID_CR_DIS_MASK BIT(7)
/* DA9150_ADETAC_CFG_D = 0x159 */
#define DA9150_ISET_UNIT_SHIFT 0
#define DA9150_ISET_UNIT_MASK (0x1f << 0)
#define DA9150_AID_UNCLAMP_SHIFT 5
#define DA9150_AID_UNCLAMP_MASK BIT(5)
/* DA9150_ADETVB_CFG_D = 0x15A */
#define DA9150_ID_MODE_SHIFT 0
#define DA9150_ID_MODE_MASK (0x03 << 0)
#define DA9150_DAT_MODE_SHIFT 2
#define DA9150_DAT_MODE_MASK (0x0f << 2)
#define DA9150_DAT_SWP_SHIFT 6
#define DA9150_DAT_SWP_MASK BIT(6)
#define DA9150_DAT_CLAMP_EXT_SHIFT 7
#define DA9150_DAT_CLAMP_EXT_MASK BIT(7)
/* DA9150_ADETID_CFG_A = 0x15B */
#define DA9150_TID_POLL_SHIFT 0
#define DA9150_TID_POLL_MASK (0x07 << 0)
#define DA9150_RID_CONV_SHIFT 3
#define DA9150_RID_CONV_MASK BIT(3)
/* DA9150_ADET_RID_PT_CHG_H = 0x15C */
#define DA9150_RID_PT_CHG_H_SHIFT 0
#define DA9150_RID_PT_CHG_H_MASK (0xff << 0)
/* DA9150_ADET_RID_PT_CHG_L = 0x15D */
#define DA9150_RID_PT_CHG_L_SHIFT 6
#define DA9150_RID_PT_CHG_L_MASK (0x03 << 6)
/* DA9150_PPR_TCTR_B = 0x160 */
#define DA9150_CHG_TCTR_VAL_SHIFT 0
#define DA9150_CHG_TCTR_VAL_MASK (0xff << 0)
/* DA9150_PPR_BKCTRL_A = 0x163 */
#define DA9150_VBUS_MODE_SHIFT 0
#define DA9150_VBUS_MODE_MASK (0x03 << 0)
#define DA9150_VBUS_MODE_CHG BIT(0)
#define DA9150_VBUS_MODE_OTG (0x02 << 0)
#define DA9150_VBUS_LPM_SHIFT 2
#define DA9150_VBUS_LPM_MASK (0x03 << 2)
#define DA9150_VBUS_SUSP_SHIFT 4
#define DA9150_VBUS_SUSP_MASK BIT(4)
#define DA9150_VBUS_PWM_SHIFT 5
#define DA9150_VBUS_PWM_MASK BIT(5)
#define DA9150_VBUS_ISO_SHIFT 6
#define DA9150_VBUS_ISO_MASK BIT(6)
#define DA9150_VBUS_LDO_SHIFT 7
#define DA9150_VBUS_LDO_MASK BIT(7)
/* DA9150_PPR_BKCFG_A = 0x164 */
#define DA9150_VBUS_ISET_SHIFT 0
#define DA9150_VBUS_ISET_MASK (0x1f << 0)
#define DA9150_VBUS_IMAX_SHIFT 5
#define DA9150_VBUS_IMAX_MASK BIT(5)
#define DA9150_VBUS_IOTG_SHIFT 6
#define DA9150_VBUS_IOTG_MASK (0x03 << 6)
/* DA9150_PPR_BKCFG_B = 0x165 */
#define DA9150_VBUS_DROP_SHIFT 0
#define DA9150_VBUS_DROP_MASK (0x0f << 0)
#define DA9150_VBUS_FAULT_DIS_SHIFT 6
#define DA9150_VBUS_FAULT_DIS_MASK BIT(6)
#define DA9150_OTG_FAULT_DIS_SHIFT 7
#define DA9150_OTG_FAULT_DIS_MASK BIT(7)
/* DA9150_PPR_CHGCTRL_A = 0x166 */
#define DA9150_CHG_EN_SHIFT 0
#define DA9150_CHG_EN_MASK BIT(0)
/* DA9150_PPR_CHGCTRL_B = 0x167 */
#define DA9150_CHG_VBAT_SHIFT 0
#define DA9150_CHG_VBAT_MASK (0x1f << 0)
#define DA9150_CHG_VDROP_SHIFT 6
#define DA9150_CHG_VDROP_MASK (0x03 << 6)
/* DA9150_PPR_CHGCTRL_C = 0x168 */
#define DA9150_CHG_VFAULT_SHIFT 0
#define DA9150_CHG_VFAULT_MASK (0x0f << 0)
#define DA9150_CHG_IPRE_SHIFT 4
#define DA9150_CHG_IPRE_MASK (0x03 << 4)
/* DA9150_PPR_TCTR_A = 0x169 */
#define DA9150_CHG_TCTR_SHIFT 0
#define DA9150_CHG_TCTR_MASK (0x07 << 0)
#define DA9150_CHG_TCTR_MODE_SHIFT 4
#define DA9150_CHG_TCTR_MODE_MASK BIT(4)
/* DA9150_PPR_CHGCTRL_D = 0x16A */
#define DA9150_CHG_IBAT_SHIFT 0
#define DA9150_CHG_IBAT_MASK (0xff << 0)
/* DA9150_PPR_CHGCTRL_E = 0x16B */
#define DA9150_CHG_IEND_SHIFT 0
#define DA9150_CHG_IEND_MASK (0xff << 0)
/* DA9150_PPR_CHGCTRL_F = 0x16C */
#define DA9150_CHG_VCOLD_SHIFT 0
#define DA9150_CHG_VCOLD_MASK (0x1f << 0)
#define DA9150_TBAT_TQA_EN_SHIFT 6
#define DA9150_TBAT_TQA_EN_MASK BIT(6)
#define DA9150_TBAT_TDP_EN_SHIFT 7
#define DA9150_TBAT_TDP_EN_MASK BIT(7)
/* DA9150_PPR_CHGCTRL_G = 0x16D */
#define DA9150_CHG_VWARM_SHIFT 0
#define DA9150_CHG_VWARM_MASK (0x1f << 0)
/* DA9150_PPR_CHGCTRL_H = 0x16E */
#define DA9150_CHG_VHOT_SHIFT 0
#define DA9150_CHG_VHOT_MASK (0x1f << 0)
/* DA9150_PPR_CHGCTRL_I = 0x16F */
#define DA9150_CHG_ICOLD_SHIFT 0
#define DA9150_CHG_ICOLD_MASK (0xff << 0)
/* DA9150_PPR_CHGCTRL_J = 0x170 */
#define DA9150_CHG_IWARM_SHIFT 0
#define DA9150_CHG_IWARM_MASK (0xff << 0)
/* DA9150_PPR_CHGCTRL_K = 0x171 */
#define DA9150_CHG_IHOT_SHIFT 0
#define DA9150_CHG_IHOT_MASK (0xff << 0)
/* DA9150_PPR_CHGCTRL_L = 0x172 */
#define DA9150_CHG_IBAT_TRED_SHIFT 0
#define DA9150_CHG_IBAT_TRED_MASK (0xff << 0)
/* DA9150_PPR_CHGCTRL_M = 0x173 */
#define DA9150_CHG_VFLOAT_SHIFT 0
#define DA9150_CHG_VFLOAT_MASK (0x0f << 0)
#define DA9150_CHG_LPM_SHIFT 5
#define DA9150_CHG_LPM_MASK BIT(5)
#define DA9150_CHG_NBLO_SHIFT 6
#define DA9150_CHG_NBLO_MASK BIT(6)
#define DA9150_EBS_EN_SHIFT 7
#define DA9150_EBS_EN_MASK BIT(7)
/* DA9150_PPR_THYST_A = 0x174 */
#define DA9150_TBAT_T1_SHIFT 0
#define DA9150_TBAT_T1_MASK (0xff << 0)
/* DA9150_PPR_THYST_B = 0x175 */
#define DA9150_TBAT_T2_SHIFT 0
#define DA9150_TBAT_T2_MASK (0xff << 0)
/* DA9150_PPR_THYST_C = 0x176 */
#define DA9150_TBAT_T3_SHIFT 0
#define DA9150_TBAT_T3_MASK (0xff << 0)
/* DA9150_PPR_THYST_D = 0x177 */
#define DA9150_TBAT_T4_SHIFT 0
#define DA9150_TBAT_T4_MASK (0xff << 0)
/* DA9150_PPR_THYST_E = 0x178 */
#define DA9150_TBAT_T5_SHIFT 0
#define DA9150_TBAT_T5_MASK (0xff << 0)
/* DA9150_PPR_THYST_F = 0x179 */
#define DA9150_TBAT_H1_SHIFT 0
#define DA9150_TBAT_H1_MASK (0xff << 0)
/* DA9150_PPR_THYST_G = 0x17A */
#define DA9150_TBAT_H5_SHIFT 0
#define DA9150_TBAT_H5_MASK (0xff << 0)
/* DA9150_PAGE_CON_3 = 0x180 */
#define DA9150_PAGE_SHIFT 0
#define DA9150_PAGE_MASK (0x3f << 0)
#define DA9150_WRITE_MODE_SHIFT 6
#define DA9150_WRITE_MODE_MASK BIT(6)
#define DA9150_REVERT_SHIFT 7
#define DA9150_REVERT_MASK BIT(7)
/* DA9150_PAGE_CON_4 = 0x200 */
#define DA9150_PAGE_SHIFT 0
#define DA9150_PAGE_MASK (0x3f << 0)
#define DA9150_WRITE_MODE_SHIFT 6
#define DA9150_WRITE_MODE_MASK BIT(6)
#define DA9150_REVERT_SHIFT 7
#define DA9150_REVERT_MASK BIT(7)
/* DA9150_PAGE_CON_5 = 0x280 */
#define DA9150_PAGE_SHIFT 0
#define DA9150_PAGE_MASK (0x3f << 0)
#define DA9150_WRITE_MODE_SHIFT 6
#define DA9150_WRITE_MODE_MASK BIT(6)
#define DA9150_REVERT_SHIFT 7
#define DA9150_REVERT_MASK BIT(7)
/* DA9150_PAGE_CON_6 = 0x300 */
#define DA9150_PAGE_SHIFT 0
#define DA9150_PAGE_MASK (0x3f << 0)
#define DA9150_WRITE_MODE_SHIFT 6
#define DA9150_WRITE_MODE_MASK BIT(6)
#define DA9150_REVERT_SHIFT 7
#define DA9150_REVERT_MASK BIT(7)
/* DA9150_COREBTLD_STAT_A = 0x302 */
#define DA9150_BOOTLD_STAT_SHIFT 0
#define DA9150_BOOTLD_STAT_MASK (0x03 << 0)
#define DA9150_CORE_LOCKUP_SHIFT 2
#define DA9150_CORE_LOCKUP_MASK BIT(2)
/* DA9150_COREBTLD_CTRL_A = 0x303 */
#define DA9150_CORE_RESET_SHIFT 0
#define DA9150_CORE_RESET_MASK BIT(0)
#define DA9150_CORE_STOP_SHIFT 1
#define DA9150_CORE_STOP_MASK BIT(1)
/* DA9150_CORE_CONFIG_A = 0x304 */
#define DA9150_CORE_MEMMUX_SHIFT 0
#define DA9150_CORE_MEMMUX_MASK (0x03 << 0)
#define DA9150_WDT_AUTO_START_SHIFT 2
#define DA9150_WDT_AUTO_START_MASK BIT(2)
#define DA9150_WDT_AUTO_LOCK_SHIFT 3
#define DA9150_WDT_AUTO_LOCK_MASK BIT(3)
#define DA9150_WDT_HLT_NO_CLK_SHIFT 4
#define DA9150_WDT_HLT_NO_CLK_MASK BIT(4)
/* DA9150_CORE_CONFIG_C = 0x305 */
#define DA9150_CORE_SW_SIZE_SHIFT 0
#define DA9150_CORE_SW_SIZE_MASK (0xff << 0)
/* DA9150_CORE_CONFIG_B = 0x306 */
#define DA9150_BOOTLD_EN_SHIFT 0
#define DA9150_BOOTLD_EN_MASK BIT(0)
#define DA9150_CORE_EN_SHIFT 2
#define DA9150_CORE_EN_MASK BIT(2)
#define DA9150_CORE_SW_SRC_SHIFT 3
#define DA9150_CORE_SW_SRC_MASK (0x07 << 3)
#define DA9150_DEEP_SLEEP_EN_SHIFT 7
#define DA9150_DEEP_SLEEP_EN_MASK BIT(7)
/* DA9150_CORE_CFG_DATA_A = 0x307 */
#define DA9150_CORE_CFG_DT_A_SHIFT 0
#define DA9150_CORE_CFG_DT_A_MASK (0xff << 0)
/* DA9150_CORE_CFG_DATA_B = 0x308 */
#define DA9150_CORE_CFG_DT_B_SHIFT 0
#define DA9150_CORE_CFG_DT_B_MASK (0xff << 0)
/* DA9150_CORE_CMD_A = 0x309 */
#define DA9150_CORE_CMD_SHIFT 0
#define DA9150_CORE_CMD_MASK (0xff << 0)
/* DA9150_CORE_DATA_A = 0x30A */
#define DA9150_CORE_DATA_0_SHIFT 0
#define DA9150_CORE_DATA_0_MASK (0xff << 0)
/* DA9150_CORE_DATA_B = 0x30B */
#define DA9150_CORE_DATA_1_SHIFT 0
#define DA9150_CORE_DATA_1_MASK (0xff << 0)
/* DA9150_CORE_DATA_C = 0x30C */
#define DA9150_CORE_DATA_2_SHIFT 0
#define DA9150_CORE_DATA_2_MASK (0xff << 0)
/* DA9150_CORE_DATA_D = 0x30D */
#define DA9150_CORE_DATA_3_SHIFT 0
#define DA9150_CORE_DATA_3_MASK (0xff << 0)
/* DA9150_CORE2WIRE_STAT_A = 0x310 */
#define DA9150_FW_FWDL_ERR_SHIFT 7
#define DA9150_FW_FWDL_ERR_MASK BIT(7)
/* DA9150_CORE2WIRE_CTRL_A = 0x311 */
#define DA9150_FW_FWDL_EN_SHIFT 0
#define DA9150_FW_FWDL_EN_MASK BIT(0)
#define DA9150_FG_QIF_EN_SHIFT 1
#define DA9150_FG_QIF_EN_MASK BIT(1)
#define DA9150_CORE_BASE_ADDR_SHIFT 4
#define DA9150_CORE_BASE_ADDR_MASK (0x0f << 4)
/* DA9150_FW_CTRL_A = 0x312 */
#define DA9150_FW_SEAL_SHIFT 0
#define DA9150_FW_SEAL_MASK (0xff << 0)
/* DA9150_FW_CTRL_C = 0x313 */
#define DA9150_FW_FWDL_CRC_SHIFT 0
#define DA9150_FW_FWDL_CRC_MASK (0xff << 0)
/* DA9150_FW_CTRL_D = 0x314 */
#define DA9150_FW_FWDL_BASE_SHIFT 0
#define DA9150_FW_FWDL_BASE_MASK (0x0f << 0)
/* DA9150_FG_CTRL_A = 0x315 */
#define DA9150_FG_QIF_CODE_SHIFT 0
#define DA9150_FG_QIF_CODE_MASK (0xff << 0)
/* DA9150_FG_CTRL_B = 0x316 */
#define DA9150_FG_QIF_VALUE_SHIFT 0
#define DA9150_FG_QIF_VALUE_MASK (0xff << 0)
/* DA9150_FW_CTRL_E = 0x317 */
#define DA9150_FW_FWDL_SEG_SHIFT 0
#define DA9150_FW_FWDL_SEG_MASK (0xff << 0)
/* DA9150_FW_CTRL_B = 0x318 */
#define DA9150_FW_FWDL_VALUE_SHIFT 0
#define DA9150_FW_FWDL_VALUE_MASK (0xff << 0)
/* DA9150_GPADC_CMAN = 0x320 */
#define DA9150_GPADC_CEN_SHIFT 0
#define DA9150_GPADC_CEN_MASK BIT(0)
#define DA9150_GPADC_CMUX_SHIFT 1
#define DA9150_GPADC_CMUX_MASK (0x1f << 1)
/* DA9150_GPADC_CRES_A = 0x322 */
#define DA9150_GPADC_CRES_H_SHIFT 0
#define DA9150_GPADC_CRES_H_MASK (0xff << 0)
/* DA9150_GPADC_CRES_B = 0x323 */
#define DA9150_GPADC_CRUN_SHIFT 0
#define DA9150_GPADC_CRUN_MASK BIT(0)
#define DA9150_GPADC_CRES_L_SHIFT 6
#define DA9150_GPADC_CRES_L_MASK (0x03 << 6)
/* DA9150_CC_CFG_A = 0x328 */
#define DA9150_CC_EN_SHIFT 0
#define DA9150_CC_EN_MASK BIT(0)
#define DA9150_CC_TIMEBASE_SHIFT 1
#define DA9150_CC_TIMEBASE_MASK (0x03 << 1)
#define DA9150_CC_CFG_SHIFT 5
#define DA9150_CC_CFG_MASK (0x03 << 5)
#define DA9150_CC_ENDLESS_MODE_SHIFT 7
#define DA9150_CC_ENDLESS_MODE_MASK BIT(7)
/* DA9150_CC_CFG_B = 0x329 */
#define DA9150_CC_OPT_SHIFT 0
#define DA9150_CC_OPT_MASK (0x03 << 0)
#define DA9150_CC_PREAMP_SHIFT 2
#define DA9150_CC_PREAMP_MASK (0x03 << 2)
/* DA9150_CC_ICHG_RES_A = 0x32A */
#define DA9150_CC_ICHG_RES_H_SHIFT 0
#define DA9150_CC_ICHG_RES_H_MASK (0xff << 0)
/* DA9150_CC_ICHG_RES_B = 0x32B */
#define DA9150_CC_ICHG_RES_L_SHIFT 3
#define DA9150_CC_ICHG_RES_L_MASK (0x1f << 3)
/* DA9150_CC_IAVG_RES_A = 0x32C */
#define DA9150_CC_IAVG_RES_H_SHIFT 0
#define DA9150_CC_IAVG_RES_H_MASK (0xff << 0)
/* DA9150_CC_IAVG_RES_B = 0x32D */
#define DA9150_CC_IAVG_RES_L_SHIFT 0
#define DA9150_CC_IAVG_RES_L_MASK (0xff << 0)
/* DA9150_TAUX_CTRL_A = 0x330 */
#define DA9150_TAUX_EN_SHIFT 0
#define DA9150_TAUX_EN_MASK BIT(0)
#define DA9150_TAUX_MOD_SHIFT 1
#define DA9150_TAUX_MOD_MASK BIT(1)
#define DA9150_TAUX_UPDATE_SHIFT 2
#define DA9150_TAUX_UPDATE_MASK BIT(2)
/* DA9150_TAUX_RELOAD_H = 0x332 */
#define DA9150_TAUX_RLD_H_SHIFT 0
#define DA9150_TAUX_RLD_H_MASK (0xff << 0)
/* DA9150_TAUX_RELOAD_L = 0x333 */
#define DA9150_TAUX_RLD_L_SHIFT 3
#define DA9150_TAUX_RLD_L_MASK (0x1f << 3)
/* DA9150_TAUX_VALUE_H = 0x334 */
#define DA9150_TAUX_VAL_H_SHIFT 0
#define DA9150_TAUX_VAL_H_MASK (0xff << 0)
/* DA9150_TAUX_VALUE_L = 0x335 */
#define DA9150_TAUX_VAL_L_SHIFT 3
#define DA9150_TAUX_VAL_L_MASK (0x1f << 3)
/* DA9150_AUX_DATA_0 = 0x338 */
#define DA9150_AUX_DAT_0_SHIFT 0
#define DA9150_AUX_DAT_0_MASK (0xff << 0)
/* DA9150_AUX_DATA_1 = 0x339 */
#define DA9150_AUX_DAT_1_SHIFT 0
#define DA9150_AUX_DAT_1_MASK (0xff << 0)
/* DA9150_AUX_DATA_2 = 0x33A */
#define DA9150_AUX_DAT_2_SHIFT 0
#define DA9150_AUX_DAT_2_MASK (0xff << 0)
/* DA9150_AUX_DATA_3 = 0x33B */
#define DA9150_AUX_DAT_3_SHIFT 0
#define DA9150_AUX_DAT_3_MASK (0xff << 0)
/* DA9150_BIF_CTRL = 0x340 */
#define DA9150_BIF_ISRC_EN_SHIFT 0
#define DA9150_BIF_ISRC_EN_MASK BIT(0)
/* DA9150_TBAT_CTRL_A = 0x342 */
#define DA9150_TBAT_EN_SHIFT 0
#define DA9150_TBAT_EN_MASK BIT(0)
#define DA9150_TBAT_SW1_SHIFT 1
#define DA9150_TBAT_SW1_MASK BIT(1)
#define DA9150_TBAT_SW2_SHIFT 2
#define DA9150_TBAT_SW2_MASK BIT(2)
/* DA9150_TBAT_CTRL_B = 0x343 */
#define DA9150_TBAT_SW_FRC_SHIFT 0
#define DA9150_TBAT_SW_FRC_MASK BIT(0)
#define DA9150_TBAT_STAT_SW1_SHIFT 1
#define DA9150_TBAT_STAT_SW1_MASK BIT(1)
#define DA9150_TBAT_STAT_SW2_SHIFT 2
#define DA9150_TBAT_STAT_SW2_MASK BIT(2)
#define DA9150_TBAT_HIGH_CURR_SHIFT 3
#define DA9150_TBAT_HIGH_CURR_MASK BIT(3)
/* DA9150_TBAT_RES_A = 0x344 */
#define DA9150_TBAT_RES_H_SHIFT 0
#define DA9150_TBAT_RES_H_MASK (0xff << 0)
/* DA9150_TBAT_RES_B = 0x345 */
#define DA9150_TBAT_RES_DIS_SHIFT 0
#define DA9150_TBAT_RES_DIS_MASK BIT(0)
#define DA9150_TBAT_RES_L_SHIFT 6
#define DA9150_TBAT_RES_L_MASK (0x03 << 6)
#endif /* __DA9150_REGISTERS_H */
include/linux/mfd/max77686-private.h
View file @ 5c277007
......@@ -447,7 +447,6 @@ struct max77686_dev {
struct regmap_irq_chip_data *rtc_irq_data;
int irq;
bool wakeup;
struct mutex irqlock;
int irq_masks_cur[MAX77686_IRQ_GROUP_NR];
int irq_masks_cache[MAX77686_IRQ_GROUP_NR];
......
include/linux/mfd/max77686.h
View file @ 5c277007
......@@ -119,12 +119,6 @@ enum max77802_regulators {
MAX77802_REG_MAX,
};
struct max77686_regulator_data {
int id;
struct regulator_init_data *initdata;
struct device_node *of_node;
};
enum max77686_opmode {
MAX77686_OPMODE_NORMAL,
MAX77686_OPMODE_LP,
......@@ -136,26 +130,4 @@ struct max77686_opmode_data {
int mode;
};
struct max77686_platform_data {
int ono;
int wakeup;
/* ---- PMIC ---- */
struct max77686_regulator_data *regulators;
int num_regulators;
struct max77686_opmode_data *opmode_data;
/*
* GPIO-DVS feature is not enabled with the current version of
* MAX77686 driver. Buck2/3/4_voltages[0] is used as the default
* voltage at probe. DVS/SELB gpios are set as OUTPUT-LOW.
*/
int buck234_gpio_dvs[3]; /* GPIO of [0]DVS1, [1]DVS2, [2]DVS3 */
int buck234_gpio_selb[3]; /* [0]SELB2, [1]SELB3, [2]SELB4 */
unsigned int buck2_voltage[8]; /* buckx_voltage in uV */
unsigned int buck3_voltage[8];
unsigned int buck4_voltage[8];
};
#endif /* __LINUX_MFD_MAX77686_H */
include/linux/mfd/qcom_rpm.h 0 → 100644
View file @ 5c277007
#ifndef __QCOM_RPM_H__
#define __QCOM_RPM_H__
#include <linux/types.h>
struct qcom_rpm;
#define QCOM_RPM_ACTIVE_STATE 0
#define QCOM_RPM_SLEEP_STATE 1
int qcom_rpm_write(struct qcom_rpm *rpm, int state, int resource, u32 *buf, size_t count);
#endif
include/linux/mfd/rt5033-private.h 0 → 100644
View file @ 5c277007
/*
* MFD core driver for Richtek RT5033
*
* Copyright (C) 2014 Samsung Electronics, Co., Ltd.
* Author: Beomho Seo <beomho.seo@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published bythe Free Software Foundation.
*/
#ifndef __RT5033_PRIVATE_H__
#define __RT5033_PRIVATE_H__
enum rt5033_reg {
RT5033_REG_CHG_STAT = 0x00,
RT5033_REG_CHG_CTRL1 = 0x01,
RT5033_REG_CHG_CTRL2 = 0x02,
RT5033_REG_DEVICE_ID = 0x03,
RT5033_REG_CHG_CTRL3 = 0x04,
RT5033_REG_CHG_CTRL4 = 0x05,
RT5033_REG_CHG_CTRL5 = 0x06,
RT5033_REG_RT_CTRL0 = 0x07,
RT5033_REG_CHG_RESET = 0x08,
/* Reserved 0x09~0x18 */
RT5033_REG_RT_CTRL1 = 0x19,
/* Reserved 0x1A~0x20 */
RT5033_REG_FLED_FUNCTION1 = 0x21,
RT5033_REG_FLED_FUNCTION2 = 0x22,
RT5033_REG_FLED_STROBE_CTRL1 = 0x23,
RT5033_REG_FLED_STROBE_CTRL2 = 0x24,
RT5033_REG_FLED_CTRL1 = 0x25,
RT5033_REG_FLED_CTRL2 = 0x26,
RT5033_REG_FLED_CTRL3 = 0x27,
RT5033_REG_FLED_CTRL4 = 0x28,
RT5033_REG_FLED_CTRL5 = 0x29,
/* Reserved 0x2A~0x40 */
RT5033_REG_CTRL = 0x41,
RT5033_REG_BUCK_CTRL = 0x42,
RT5033_REG_LDO_CTRL = 0x43,
/* Reserved 0x44~0x46 */
RT5033_REG_MANUAL_RESET_CTRL = 0x47,
/* Reserved 0x48~0x5F */
RT5033_REG_CHG_IRQ1 = 0x60,
RT5033_REG_CHG_IRQ2 = 0x61,
RT5033_REG_CHG_IRQ3 = 0x62,
RT5033_REG_CHG_IRQ1_CTRL = 0x63,
RT5033_REG_CHG_IRQ2_CTRL = 0x64,
RT5033_REG_CHG_IRQ3_CTRL = 0x65,
RT5033_REG_LED_IRQ_STAT = 0x66,
RT5033_REG_LED_IRQ_CTRL = 0x67,
RT5033_REG_PMIC_IRQ_STAT = 0x68,
RT5033_REG_PMIC_IRQ_CTRL = 0x69,
RT5033_REG_SHDN_CTRL = 0x6A,
RT5033_REG_OFF_EVENT = 0x6B,
RT5033_REG_END,
};
/* RT5033 Charger state register */
#define RT5033_CHG_STAT_MASK 0x20
#define RT5033_CHG_STAT_DISCHARGING 0x00
#define RT5033_CHG_STAT_FULL 0x10
#define RT5033_CHG_STAT_CHARGING 0x20
#define RT5033_CHG_STAT_NOT_CHARGING 0x30
#define RT5033_CHG_STAT_TYPE_MASK 0x60
#define RT5033_CHG_STAT_TYPE_PRE 0x20
#define RT5033_CHG_STAT_TYPE_FAST 0x60
/* RT5033 CHGCTRL1 register */
#define RT5033_CHGCTRL1_IAICR_MASK 0xe0
#define RT5033_CHGCTRL1_MODE_MASK 0x01
/* RT5033 CHGCTRL2 register */
#define RT5033_CHGCTRL2_CV_MASK 0xfc
/* RT5033 CHGCTRL3 register */
#define RT5033_CHGCTRL3_CFO_EN_MASK 0x40
#define RT5033_CHGCTRL3_TIMER_MASK 0x38
#define RT5033_CHGCTRL3_TIMER_EN_MASK 0x01
/* RT5033 CHGCTRL4 register */
#define RT5033_CHGCTRL4_EOC_MASK 0x07
#define RT5033_CHGCTRL4_IPREC_MASK 0x18
/* RT5033 CHGCTRL5 register */
#define RT5033_CHGCTRL5_VPREC_MASK 0x0f
#define RT5033_CHGCTRL5_ICHG_MASK 0xf0
#define RT5033_CHGCTRL5_ICHG_SHIFT 0x04
#define RT5033_CHG_MAX_CURRENT 0x0d
/* RT5033 RT CTRL1 register */
#define RT5033_RT_CTRL1_UUG_MASK 0x02
#define RT5033_RT_HZ_MASK 0x01
/* RT5033 control register */
#define RT5033_CTRL_FCCM_BUCK_MASK 0x00
#define RT5033_CTRL_BUCKOMS_MASK 0x01
#define RT5033_CTRL_LDOOMS_MASK 0x02
#define RT5033_CTRL_SLDOOMS_MASK 0x03
#define RT5033_CTRL_EN_BUCK_MASK 0x04
#define RT5033_CTRL_EN_LDO_MASK 0x05
#define RT5033_CTRL_EN_SAFE_LDO_MASK 0x06
#define RT5033_CTRL_LDO_SLEEP_MASK 0x07
/* RT5033 BUCK control register */
#define RT5033_BUCK_CTRL_MASK 0x1f
/* RT5033 LDO control register */
#define RT5033_LDO_CTRL_MASK 0x1f
/* RT5033 charger property - model, manufacturer */
#define RT5033_CHARGER_MODEL "RT5033WSC Charger"
#define RT5033_MANUFACTURER "Richtek Technology Corporation"
/*
* RT5033 charger fast-charge current lmits (as in CHGCTRL1 register),
* AICR mode limits the input current for example,
* the AIRC 100 mode limits the input current to 100 mA.
*/
#define RT5033_AICR_100_MODE 0x20
#define RT5033_AICR_500_MODE 0x40
#define RT5033_AICR_700_MODE 0x60
#define RT5033_AICR_900_MODE 0x80
#define RT5033_AICR_1500_MODE 0xc0
#define RT5033_AICR_2000_MODE 0xe0
#define RT5033_AICR_MODE_MASK 0xe0
/* RT5033 use internal timer need to set time */
#define RT5033_FAST_CHARGE_TIMER4 0x00
#define RT5033_FAST_CHARGE_TIMER6 0x01
#define RT5033_FAST_CHARGE_TIMER8 0x02
#define RT5033_FAST_CHARGE_TIMER9 0x03
#define RT5033_FAST_CHARGE_TIMER12 0x04
#define RT5033_FAST_CHARGE_TIMER14 0x05
#define RT5033_FAST_CHARGE_TIMER16 0x06
#define RT5033_INT_TIMER_ENABLE 0x01
/* RT5033 charger termination enable mask */
#define RT5033_TE_ENABLE_MASK 0x08
/*
* RT5033 charger opa mode. RT50300 have two opa mode charger mode
* and boost mode for OTG
*/
#define RT5033_CHARGER_MODE 0x00
#define RT5033_BOOST_MODE 0x01
/* RT5033 charger termination enable */
#define RT5033_TE_ENABLE 0x08
/* RT5033 charger CFO enable */
#define RT5033_CFO_ENABLE 0x40
/* RT5033 charger constant charge voltage (as in CHGCTRL2 register), uV */
#define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MIN 3650000U
#define RT5033_CHARGER_CONST_VOLTAGE_STEP_NUM 25000U
#define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MAX 4400000U
/* RT5033 charger pre-charge current limits (as in CHGCTRL4 register), uA */
#define RT5033_CHARGER_PRE_CURRENT_LIMIT_MIN 350000U
#define RT5033_CHARGER_PRE_CURRENT_STEP_NUM 100000U
#define RT5033_CHARGER_PRE_CURRENT_LIMIT_MAX 650000U
/* RT5033 charger fast-charge current (as in CHGCTRL5 register), uA */
#define RT5033_CHARGER_FAST_CURRENT_MIN 700000U
#define RT5033_CHARGER_FAST_CURRENT_STEP_NUM 100000U
#define RT5033_CHARGER_FAST_CURRENT_MAX 2000000U
/*
* RT5033 charger const-charge end of charger current (
* as in CHGCTRL4 register), uA
*/
#define RT5033_CHARGER_EOC_MIN 150000U
#define RT5033_CHARGER_EOC_REF 300000U
#define RT5033_CHARGER_EOC_STEP_NUM1 50000U
#define RT5033_CHARGER_EOC_STEP_NUM2 100000U
#define RT5033_CHARGER_EOC_MAX 600000U
/*
* RT5033 charger pre-charge threshold volt limits
* (as in CHGCTRL5 register), uV
*/
#define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MIN 2300000U
#define RT5033_CHARGER_PRE_THRESHOLD_STEP_NUM 100000U
#define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MAX 3800000U
/*
* RT5033 charger enable UUG, If UUG enable MOS auto control by H/W charger
* circuit.
*/
#define RT5033_CHARGER_UUG_ENABLE 0x02
/* RT5033 charger High impedance mode */
#define RT5033_CHARGER_HZ_DISABLE 0x00
#define RT5033_CHARGER_HZ_ENABLE 0x01
/* RT5033 regulator BUCK output voltage uV */
#define RT5033_REGULATOR_BUCK_VOLTAGE_MIN 1000000U
#define RT5033_REGULATOR_BUCK_VOLTAGE_MAX 3000000U
#define RT5033_REGULATOR_BUCK_VOLTAGE_STEP 100000U
#define RT5033_REGULATOR_BUCK_VOLTAGE_STEP_NUM 32
/* RT5033 regulator LDO output voltage uV */
#define RT5033_REGULATOR_LDO_VOLTAGE_MIN 1200000U
#define RT5033_REGULATOR_LDO_VOLTAGE_MAX 3000000U
#define RT5033_REGULATOR_LDO_VOLTAGE_STEP 100000U
#define RT5033_REGULATOR_LDO_VOLTAGE_STEP_NUM 32
/* RT5033 regulator SAFE LDO output voltage uV */
#define RT5033_REGULATOR_SAFE_LDO_VOLTAGE 4900000U
enum rt5033_fuel_reg {
RT5033_FUEL_REG_OCV_H = 0x00,
RT5033_FUEL_REG_OCV_L = 0x01,
RT5033_FUEL_REG_VBAT_H = 0x02,
RT5033_FUEL_REG_VBAT_L = 0x03,
RT5033_FUEL_REG_SOC_H = 0x04,
RT5033_FUEL_REG_SOC_L = 0x05,
RT5033_FUEL_REG_CTRL_H = 0x06,
RT5033_FUEL_REG_CTRL_L = 0x07,
RT5033_FUEL_REG_CRATE = 0x08,
RT5033_FUEL_REG_DEVICE_ID = 0x09,
RT5033_FUEL_REG_AVG_VOLT_H = 0x0A,
RT5033_FUEL_REG_AVG_VOLT_L = 0x0B,
RT5033_FUEL_REG_CONFIG_H = 0x0C,
RT5033_FUEL_REG_CONFIG_L = 0x0D,
/* Reserved 0x0E~0x0F */
RT5033_FUEL_REG_IRQ_CTRL = 0x10,
RT5033_FUEL_REG_IRQ_FLAG = 0x11,
RT5033_FUEL_VMIN = 0x12,
RT5033_FUEL_SMIN = 0x13,
/* Reserved 0x14~0x1F */
RT5033_FUEL_VGCOMP1 = 0x20,
RT5033_FUEL_VGCOMP2 = 0x21,
RT5033_FUEL_VGCOMP3 = 0x22,
RT5033_FUEL_VGCOMP4 = 0x23,
/* Reserved 0x24~0xFD */
RT5033_FUEL_MFA_H = 0xFE,
RT5033_FUEL_MFA_L = 0xFF,
RT5033_FUEL_REG_END,
};
/* RT5033 fuel gauge battery present property */
#define RT5033_FUEL_BAT_PRESENT 0x02
/* RT5033 PMIC interrupts */
#define RT5033_PMIC_IRQ_BUCKOCP 2
#define RT5033_PMIC_IRQ_BUCKLV 3
#define RT5033_PMIC_IRQ_SAFELDOLV 4
#define RT5033_PMIC_IRQ_LDOLV 5
#define RT5033_PMIC_IRQ_OT 6
#define RT5033_PMIC_IRQ_VDDA_UV 7
#endif /* __RT5033_PRIVATE_H__ */
include/linux/mfd/rt5033.h 0 → 100644
View file @ 5c277007
/*
* MFD core driver for the RT5033
*
* Copyright (C) 2014 Samsung Electronics
* Author: Beomho Seo <beomho.seo@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published bythe Free Software Foundation.
*/
#ifndef __RT5033_H__
#define __RT5033_H__
#include <linux/regulator/consumer.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/power_supply.h>
/* RT5033 regulator IDs */
enum rt5033_regulators {
RT5033_BUCK = 0,
RT5033_LDO,
RT5033_SAFE_LDO,
RT5033_REGULATOR_NUM,
};
struct rt5033_dev {
struct device *dev;
struct regmap *regmap;
struct regmap_irq_chip_data *irq_data;
int irq;
bool wakeup;
};
struct rt5033_battery {
struct i2c_client *client;
struct rt5033_dev *rt5033;
struct regmap *regmap;
struct power_supply psy;
};
/* RT5033 charger platform data */
struct rt5033_charger_data {
unsigned int pre_uamp;
unsigned int pre_uvolt;
unsigned int const_uvolt;
unsigned int eoc_uamp;
unsigned int fast_uamp;
};
struct rt5033_charger {
struct device *dev;
struct rt5033_dev *rt5033;
struct power_supply psy;
struct rt5033_charger_data *chg;
};
#endif /* __RT5033_H__ */
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