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Commit 5c6d0b55 authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Nishanth Menon
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arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES 

Rename the external refclk inputs to the SERDES from
dummy_cmn_refclk/dummy_cmn_refclk1 to cmn_refclk/cmn_refclk1
respectively. Also move the external refclk DT nodes outside the
cbass_main DT node. Since in j721e common processor board, only the
cmn_refclk1 is connected to 100MHz clock, fix the clock frequency.

Fixes: afd094eb ("arm64: dts: ti: k3-j721e-main: Add WIZ and SERDES PHY nodes")
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: default avatarAswath Govindraju <a-govindraju@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210603143427.28735-2-kishon@ti.com
parent 7ce11d47
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Showing with 34 additions and 28 deletions
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
View file @ 5c6d0b55
......@@ -635,6 +635,10 @@ &mcasp11 {
status = "disabled";
};
&cmn_refclk1 {
clock-frequency = <100000000>;
};
&serdes0 {
serdes0_pcie_link: link@0 {
reg = <0>;
......
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
View file @ 5c6d0b55
......@@ -8,6 +8,20 @@
#include <dt-bindings/mux/mux.h>
#include <dt-bindings/mux/ti-serdes.h>
/ {
cmn_refclk: clock-cmnrefclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
cmn_refclk1: clock-cmnrefclk1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
};
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
......@@ -338,24 +352,12 @@ main_pmx0: pinctrl@11c000 {
pinctrl-single,function-mask = <0xffffffff>;
};
dummy_cmn_refclk: dummy-cmn-refclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
dummy_cmn_refclk1: dummy-cmn-refclk1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
serdes_wiz0: wiz@5000000 {
compatible = "ti,j721e-wiz-16g";
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
......@@ -364,21 +366,21 @@ serdes_wiz0: wiz@5000000 {
ranges = <0x5000000 0x0 0x5000000 0x10000>;
wiz0_pll0_refclk: pll0-refclk {
clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;
clocks = <&k3_clks 292 11>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_pll0_refclk>;
assigned-clock-parents = <&k3_clks 292 11>;
};
wiz0_pll1_refclk: pll1-refclk {
clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_pll1_refclk>;
assigned-clock-parents = <&k3_clks 292 0>;
};
wiz0_refclk_dig: refclk-dig {
clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_refclk_dig>;
assigned-clock-parents = <&k3_clks 292 11>;
......@@ -412,7 +414,7 @@ serdes_wiz1: wiz@5010000 {
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>;
clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
......@@ -421,21 +423,21 @@ serdes_wiz1: wiz@5010000 {
ranges = <0x5010000 0x0 0x5010000 0x10000>;
wiz1_pll0_refclk: pll0-refclk {
clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
clocks = <&k3_clks 293 13>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz1_pll0_refclk>;
assigned-clock-parents = <&k3_clks 293 13>;
};
wiz1_pll1_refclk: pll1-refclk {
clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz1_pll1_refclk>;
assigned-clock-parents = <&k3_clks 293 0>;
};
wiz1_refclk_dig: refclk-dig {
clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz1_refclk_dig>;
assigned-clock-parents = <&k3_clks 293 13>;
......@@ -469,7 +471,7 @@ serdes_wiz2: wiz@5020000 {
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>;
clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
......@@ -478,21 +480,21 @@ serdes_wiz2: wiz@5020000 {
ranges = <0x5020000 0x0 0x5020000 0x10000>;
wiz2_pll0_refclk: pll0-refclk {
clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>;
clocks = <&k3_clks 294 11>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz2_pll0_refclk>;
assigned-clock-parents = <&k3_clks 294 11>;
};
wiz2_pll1_refclk: pll1-refclk {
clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;
clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz2_pll1_refclk>;
assigned-clock-parents = <&k3_clks 294 0>;
};
wiz2_refclk_dig: refclk-dig {
clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz2_refclk_dig>;
assigned-clock-parents = <&k3_clks 294 11>;
......@@ -526,7 +528,7 @@ serdes_wiz3: wiz@5030000 {
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
......@@ -535,21 +537,21 @@ serdes_wiz3: wiz@5030000 {
ranges = <0x5030000 0x0 0x5030000 0x10000>;
wiz3_pll0_refclk: pll0-refclk {
clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
clocks = <&k3_clks 295 9>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz3_pll0_refclk>;
assigned-clock-parents = <&k3_clks 295 9>;
};
wiz3_pll1_refclk: pll1-refclk {
clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz3_pll1_refclk>;
assigned-clock-parents = <&k3_clks 295 0>;
};
wiz3_refclk_dig: refclk-dig {
clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz3_refclk_dig>;
assigned-clock-parents = <&k3_clks 295 9>;
......
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