Commit 5d8a00ee authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "The usual collection of new drivers, non-critical fixes, and updates
  to existing clk drivers. The bulk of the work is on Allwinner and
  Rockchip SoCs, but there's also an Intel Atom driver in here too.

  New Drivers:
   - Tegra BPMP firmware
   - Hisilicon hi3660 SoCs
   - Rockchip rk3328 SoCs
   - Intel Atom PMC
   - STM32F746
   - IDT VersaClock 5P49V5923 and 5P49V5933
   - Marvell mv98dx3236 SoCs
   - Allwinner V3s SoCs

  Removed Drivers:
   - Samsung Exynos4415 SoCs

  Updates:
   - Migrate ABx500 to OF
   - Qualcomm IPQ4019 CPU clks and general PLL support
   - Qualcomm MSM8974 RPM
   - Rockchip non-critical fixes and clk id additions
   - Samsung Exynos4412 CPUs
   - Socionext UniPhier NAND and eMMC support
   - ZTE zx296718 i2s and other audio clks
   - Renesas CAN and MSIOF clks for R-Car M3-W
   - Renesas resets for R-Car Gen2 and Gen3 and RZ/G1
   - TI CDCE913, CDCE937, and CDCE949 clk generators
   - Marvell Armada ap806 CPU frequencies
   - STM32F4* I2S/SAI support
   - Broadcom BCM2835 DSI support
   - Allwinner sun5i and A80 conversion to new style clk bindings"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (130 commits)
  clk: renesas: mstp: ensure register writes complete
  clk: qcom: Do not drop device node twice
  clk: mvebu: adjust clock handling for the CP110 system controller
  clk: mvebu: Expand mv98dx3236-core-clock support
  clk: zte: add i2s clocks for zx296718
  clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR()
  clk: sunxi-ng: select SUNXI_CCU_MULT for sun5i
  clk: sunxi-ng: Check kzalloc() for errors and cleanup error path
  clk: tegra: Add BPMP clock driver
  clk: uniphier: add eMMC clock for LD11 and LD20 SoCs
  clk: uniphier: add NAND clock for all UniPhier SoCs
  ARM: dts: sun9i: Switch to new clock bindings
  clk: sunxi-ng: Add A80 Display Engine CCU
  clk: sunxi-ng: Add A80 USB CCU
  clk: sunxi-ng: Add A80 CCU
  clk: sunxi-ng: Support separately grouped PLL lock status register
  clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT
  clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag
  clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers
  clk: qcom: SDHCI enablement on Nexus 5X / 6P
  ...
parents 7067739d f59de563
...@@ -16,7 +16,20 @@ Required properties: ...@@ -16,7 +16,20 @@ Required properties:
- #clock-cells: Should be <1>. The permitted clock-specifier values can be - #clock-cells: Should be <1>. The permitted clock-specifier values can be
found in include/dt-bindings/clock/bcm2835.h found in include/dt-bindings/clock/bcm2835.h
- reg: Specifies base physical address and size of the registers - reg: Specifies base physical address and size of the registers
- clocks: The external oscillator clock phandle - clocks: phandles to the parent clocks used as input to the module, in
the following order:
- External oscillator
- DSI0 byte clock
- DSI0 DDR2 clock
- DSI0 DDR clock
- DSI1 byte clock
- DSI1 DDR2 clock
- DSI1 DDR clock
Only external oscillator is required. The DSI clocks may
not be present, in which case their children will be
unusable.
Example: Example:
......
* Samsung Exynos4415 Clock Controller
The Exynos4415 clock controller generates and supplies clock to various
consumer devices within the Exynos4415 SoC.
Required properties:
- compatible: should be one of the following:
- "samsung,exynos4415-cmu" - for the main system clocks controller
(CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).
- "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
Controller (DMC) domain clock controller.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos4415.h header and can be used in device
tree sources.
Example 1: An example of a clock controller node is listed below.
cmu: clock-controller@10030000 {
compatible = "samsung,exynos4415-cmu";
reg = <0x10030000 0x18000>;
#clock-cells = <1>;
};
cmu-dmc: clock-controller@105C0000 {
compatible = "samsung,exynos4415-cmu-dmc";
reg = <0x105C0000 0x3000>;
#clock-cells = <1>;
};
* Hisilicon Hi3660 Clock Controller
The Hi3660 clock controller generates and supplies clock to various
controllers within the Hi3660 SoC.
Required Properties:
- compatible: the compatible should be one of the following strings to
indicate the clock controller functionality.
- "hisilicon,hi3660-crgctrl"
- "hisilicon,hi3660-pctrl"
- "hisilicon,hi3660-pmuctrl"
- "hisilicon,hi3660-sctrl"
- "hisilicon,hi3660-iomcu"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
All these identifier could be found in <dt-bindings/clock/hi3660-clock.h>.
Examples:
crg_ctrl: clock-controller@fff35000 {
compatible = "hisilicon,hi3660-crgctrl", "syscon";
reg = <0x0 0xfff35000 0x0 0x1000>;
#clock-cells = <1>;
};
uart0: serial@fdf02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf02000 0x0 0x1000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
<&crg_ctrl HI3660_PCLK>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
Binding for IDT VersaClock5 programmable i2c clock generator.
The IDT VersaClock5 are programmable i2c clock generators providing
from 3 to 12 output clocks.
==I2C device node==
Required properties:
- compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933".
- reg: i2c device address, shall be 0x68 or 0x6a.
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: from common clock binding; list of parent clock handles,
- 5p49v5923: (required) either or both of XTAL or CLKIN
reference clock.
- 5p49v5933: (optional) property not present (internal
Xtal used) or CLKIN reference
clock.
- clock-names: from common clock binding; clock input names, can be
- 5p49v5923: (required) either or both of "xin", "clkin".
- 5p49v5933: (optional) property not present or "clkin".
==Mapping between clock specifier and physical pins==
When referencing the provided clock in the DT using phandle and
clock specifier, the following mapping applies:
5P49V5923:
0 -- OUT0_SEL_I2CB
1 -- OUT1
2 -- OUT2
5P49V5933:
0 -- OUT0_SEL_I2CB
1 -- OUT1
2 -- OUT4
==Example==
/* 25MHz reference crystal */
ref25: ref25m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
i2c-master-node {
/* IDT 5P49V5923 i2c clock generator */
vc5: clock-generator@6a {
compatible = "idt,5p49v5923";
reg = <0x6a>;
#clock-cells = <1>;
/* Connect XIN input to 25MHz reference */
clocks = <&ref25m>;
clock-names = "xin";
};
};
/* Consumer referencing the 5P49V5923 pin OUT1 */
consumer {
...
clocks = <&vc5 1>;
...
}
...@@ -7,6 +7,7 @@ Required properties: ...@@ -7,6 +7,7 @@ Required properties:
- compatible : must be "marvell,armada-370-corediv-clock", - compatible : must be "marvell,armada-370-corediv-clock",
"marvell,armada-375-corediv-clock", "marvell,armada-375-corediv-clock",
"marvell,armada-380-corediv-clock", "marvell,armada-380-corediv-clock",
"marvell,mv98dx3236-corediv-clock",
- reg : must be the register address of Core Divider control register - reg : must be the register address of Core Divider control register
- #clock-cells : from common clock binding; shall be set to 1 - #clock-cells : from common clock binding; shall be set to 1
......
...@@ -3,6 +3,7 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms ...@@ -3,6 +3,7 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms
Required properties: Required properties:
- compatible : shall be one of the following: - compatible : shall be one of the following:
"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP "marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
"marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
- reg : Address and length of the clock complex register set, followed - reg : Address and length of the clock complex register set, followed
by address and length of the PMU DFS registers by address and length of the PMU DFS registers
- #clock-cells : should be set to 1. - #clock-cells : should be set to 1.
......
...@@ -11,6 +11,7 @@ Required properties : ...@@ -11,6 +11,7 @@ Required properties :
compatible "qcom,rpmcc" should be also included. compatible "qcom,rpmcc" should be also included.
"qcom,rpmcc-msm8916", "qcom,rpmcc" "qcom,rpmcc-msm8916", "qcom,rpmcc"
"qcom,rpmcc-msm8974", "qcom,rpmcc"
"qcom,rpmcc-apq8064", "qcom,rpmcc" "qcom,rpmcc-apq8064", "qcom,rpmcc"
- #clock-cells : shall contain 1 - #clock-cells : shall contain 1
......
...@@ -42,6 +42,10 @@ Required Properties: ...@@ -42,6 +42,10 @@ Required Properties:
Domain bindings in Domain bindings in
Documentation/devicetree/bindings/power/power_domain.txt. Documentation/devicetree/bindings/power/power_domain.txt.
- #reset-cells: Must be 1
- The single reset specifier cell must be the module number, as defined
in the datasheet.
Examples Examples
-------- --------
...@@ -55,6 +59,7 @@ Examples ...@@ -55,6 +59,7 @@ Examples
clock-names = "extal", "extalr"; clock-names = "extal", "extalr";
#clock-cells = <2>; #clock-cells = <2>;
#power-domain-cells = <0>; #power-domain-cells = <0>;
#reset-cells = <1>;
}; };
...@@ -69,5 +74,6 @@ Examples ...@@ -69,5 +74,6 @@ Examples
dmas = <&dmac1 0x13>, <&dmac1 0x12>; dmas = <&dmac1 0x13>, <&dmac1 0x12>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
power-domains = <&cpg>; power-domains = <&cpg>;
resets = <&cpg 310>;
status = "disabled"; status = "disabled";
}; };
* Rockchip RK3328 Clock and Reset Unit
The RK3328 clock controller generates and supplies clock to various
controllers within the SoC and also implements a reset controller for SoC
peripherals.
Required Properties:
- compatible: should be "rockchip,rk3328-cru"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
- #reset-cells: should be 1.
Optional Properties:
- rockchip,grf: phandle to the syscon managing the "general register files"
If missing pll rates are not changeable, due to the missing pll lock status.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
used in device tree sources. Similar macros exist for the reset sources in
these files.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xin24m" - crystal input - required,
- "clkin_i2s" - external I2S clock - optional,
- "gmac_clkin" - external GMAC clock - optional
- "phy_50m_out" - output clock of the pll in the mac phy
Example: Clock controller node:
cru: clock-controller@ff440000 {
compatible = "rockchip,rk3328-cru";
reg = <0x0 0xff440000 0x0 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller:
uart0: serial@ff120000 {
compatible = "snps,dw-apb-uart";
reg = <0xff120000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&cru SCLK_UART0>;
};
...@@ -13,6 +13,12 @@ Required Properties: ...@@ -13,6 +13,12 @@ Required Properties:
- #clock-cells: should be 1. - #clock-cells: should be 1.
- #reset-cells: should be 1. - #reset-cells: should be 1.
Optional Properties:
- rockchip,grf: phandle to the syscon managing the "general register files".
It is used for GRF muxes, if missing any muxes present in the GRF will not
be available.
Each clock is assigned an identifier and client nodes can use this identifier Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
......
...@@ -10,6 +10,7 @@ Required properties: ...@@ -10,6 +10,7 @@ Required properties:
- compatible: Should be: - compatible: Should be:
"st,stm32f42xx-rcc" "st,stm32f42xx-rcc"
"st,stm32f469-rcc" "st,stm32f469-rcc"
"st,stm32f746-rcc"
- reg: should be register base and length as documented in the - reg: should be register base and length as documented in the
datasheet datasheet
- #reset-cells: 1, see below - #reset-cells: 1, see below
...@@ -84,6 +85,25 @@ The secondary index is bound with the following magic numbers: ...@@ -84,6 +85,25 @@ The secondary index is bound with the following magic numbers:
12 CLK_I2SQ_PDIV (post divisor of pll i2s q divisor) 12 CLK_I2SQ_PDIV (post divisor of pll i2s q divisor)
13 CLK_SAIQ_PDIV (post divisor of pll sai q divisor) 13 CLK_SAIQ_PDIV (post divisor of pll sai q divisor)
14 CLK_HSI (Internal ocscillator clock)
15 CLK_SYSCLK (System Clock)
16 CLK_HDMI_CEC (HDMI-CEC clock)
17 CLK_SPDIF (SPDIF-Rx clock)
18 CLK_USART1 (U(s)arts clocks)
19 CLK_USART2
20 CLK_USART3
21 CLK_UART4
22 CLK_UART5
23 CLK_USART6
24 CLK_UART7
25 CLK_UART8
26 CLK_I2C1 (I2S clocks)
27 CLK_I2C2
28 CLK_I2C3
29 CLK_I2C4
30 CLK_LPTIMER (LPTimer1 clock)
)
Example: Example:
/* Misc clock, FCLK */ /* Misc clock, FCLK */
......
Clock bindings for ST-Ericsson ABx500 clocks
Required properties :
- compatible : shall contain the following:
"stericsson,ab8500-clk"
- #clock-cells should be <1>
The ABx500 clocks need to be placed as a subnode of an AB8500
device node, see mfd/ab8500.txt
All available clocks are defined as preprocessor macros in
dt-bindings/clock/ste-ab8500.h header and can be used in device
tree sources.
Example:
clock-controller {
compatible = "stericsson,ab8500-clk";
#clock-cells = <1>;
};
Allwinner A80 Display Engine Clock Control Binding
--------------------------------------------------
Required properties :
- compatible: must contain one of the following compatibles:
- "allwinner,sun9i-a80-de-clks"
- reg: Must contain the registers base address and length
- clocks: phandle to the clocks feeding the display engine subsystem.
Three are needed:
- "mod": the display engine module clock
- "dram": the DRAM bus clock for the system
- "bus": the bus clock for the whole display engine subsystem
- clock-names: Must contain the clock names described just above
- resets: phandle to the reset control for the display engine subsystem.
- #clock-cells : must contain 1
- #reset-cells : must contain 1
Example:
de_clocks: clock@3000000 {
compatible = "allwinner,sun9i-a80-de-clks";
reg = <0x03000000 0x30>;
clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
clock-names = "mod", "dram", "bus";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Allwinner A80 USB Clock Control Binding
---------------------------------------
Required properties :
- compatible: must contain one of the following compatibles:
- "allwinner,sun9i-a80-usb-clocks"
- reg: Must contain the registers base address and length
- clocks: phandle to the clocks feeding the USB subsystem. Two are needed:
- "bus": the bus clock for the whole USB subsystem
- "hosc": the high frequency oscillator (usually at 24MHz)
- clock-names: Must contain the clock names described just above
- #clock-cells : must contain 1
- #reset-cells : must contain 1
Example:
usb_clocks: clock@a08000 {
compatible = "allwinner,sun9i-a80-usb-clks";
reg = <0x00a08000 0x8>;
clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
clock-names = "bus", "hosc";
#clock-cells = <1>;
#reset-cells = <1>;
};
...@@ -7,6 +7,8 @@ Required properties : ...@@ -7,6 +7,8 @@ Required properties :
- "allwinner,sun8i-a23-ccu" - "allwinner,sun8i-a23-ccu"
- "allwinner,sun8i-a33-ccu" - "allwinner,sun8i-a33-ccu"
- "allwinner,sun8i-h3-ccu" - "allwinner,sun8i-h3-ccu"
- "allwinner,sun8i-v3s-ccu"
- "allwinner,sun9i-a80-ccu"
- "allwinner,sun50i-a64-ccu" - "allwinner,sun50i-a64-ccu"
- reg: Must contain the registers base address and length - reg: Must contain the registers base address and length
......
Binding for TO CDCE925 programmable I2C clock synthesizers. Binding for TI CDCE913/925/937/949 programmable I2C clock synthesizers.
Reference Reference
This binding uses the common clock binding[1]. This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] http://www.ti.com/product/cdce925 [2] http://www.ti.com/product/cdce913
[3] http://www.ti.com/product/cdce925
[4] http://www.ti.com/product/cdce937
[5] http://www.ti.com/product/cdce949
The driver provides clock sources for each output Y1 through Y5. The driver provides clock sources for each output Y1 through Y5.
Required properties: Required properties:
- compatible: Shall be "ti,cdce925" - compatible: Shall be one of the following:
- "ti,cdce913": 1-PLL, 3 Outputs
- "ti,cdce925": 2-PLL, 5 Outputs
- "ti,cdce937": 3-PLL, 7 Outputs
- "ti,cdce949": 4-PLL, 9 Outputs
- reg: I2C device address. - reg: I2C device address.
- clocks: Points to a fixed parent clock that provides the input frequency. - clocks: Points to a fixed parent clock that provides the input frequency.
- #clock-cells: From common clock bindings: Shall be 1. - #clock-cells: From common clock bindings: Shall be 1.
...@@ -18,7 +25,7 @@ Optional properties: ...@@ -18,7 +25,7 @@ Optional properties:
- xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
board, or to compensate for external influences. board, or to compensate for external influences.
For both PLL1 and PLL2 an optional child node can be used to specify spread For all PLL1, PLL2, ... an optional child node can be used to specify spread
spectrum clocking parameters for a board. spectrum clocking parameters for a board.
- spread-spectrum: SSC mode as defined in the data sheet. - spread-spectrum: SSC mode as defined in the data sheet.
- spread-spectrum-center: Use "centered" mode instead of "max" mode. When - spread-spectrum-center: Use "centered" mode instead of "max" mode. When
......
...@@ -13,6 +13,9 @@ Required properties: ...@@ -13,6 +13,9 @@ Required properties:
"zte,zx296718-lsp1crm": "zte,zx296718-lsp1crm":
zx296718 device level clock selection and gating zx296718 device level clock selection and gating
"zte,zx296718-audiocrm":
zx296718 audio clock selection, divider and gating
- reg: Address and length of the register set - reg: Address and length of the register set
The clock consumer should specify the desired clock by having the clock The clock consumer should specify the desired clock by having the clock
......
...@@ -6270,6 +6270,11 @@ S: Maintained ...@@ -6270,6 +6270,11 @@ S: Maintained
F: drivers/mfd/lpc_ich.c F: drivers/mfd/lpc_ich.c
F: drivers/gpio/gpio-ich.c F: drivers/gpio/gpio-ich.c
IDT VersaClock 5 CLOCK DRIVER
M: Marek Vasut <marek.vasut@gmail.com>
S: Maintained
F: drivers/clk/clk-versaclock5.c
IDE SUBSYSTEM IDE SUBSYSTEM
M: "David S. Miller" <davem@davemloft.net> M: "David S. Miller" <davem@davemloft.net>
L: linux-ide@vger.kernel.org L: linux-ide@vger.kernel.org
......
...@@ -65,8 +65,9 @@ framebuffer@0 { ...@@ -65,8 +65,9 @@ framebuffer@0 {
compatible = "allwinner,simple-framebuffer", compatible = "allwinner,simple-framebuffer",
"simple-framebuffer"; "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi"; allwinner,pipeline = "de_be0-lcd0-hdmi";
clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>, clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_HDMI>,
<&ahb_gates 43>, <&ahb_gates 44>; <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DRAM_DE_BE>,
<&ccu CLK_DE_BE>, <&ccu CLK_HDMI>;
status = "disabled"; status = "disabled";
}; };
...@@ -74,8 +75,8 @@ framebuffer@1 { ...@@ -74,8 +75,8 @@ framebuffer@1 {
compatible = "allwinner,simple-framebuffer", compatible = "allwinner,simple-framebuffer",
"simple-framebuffer"; "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0"; allwinner,pipeline = "de_be0-lcd0";
clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>, clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
<&ahb_gates 44>; <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
status = "disabled"; status = "disabled";
}; };
...@@ -83,77 +84,19 @@ framebuffer@2 { ...@@ -83,77 +84,19 @@ framebuffer@2 {
compatible = "allwinner,simple-framebuffer", compatible = "allwinner,simple-framebuffer",
"simple-framebuffer"; "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0"; allwinner,pipeline = "de_be0-lcd0-tve0";
clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>, clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
<&ahb_gates 36>, <&ahb_gates 44>; <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
<&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
status = "disabled"; status = "disabled";
}; };
}; };
clocks {
ahb_gates: clk@01c20060 {
#clock-cells = <1>;
compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
clock-indices = <0>, <1>,
<2>, <5>, <6>,
<7>, <8>, <9>,
<10>, <13>,
<14>, <17>, <18>,
<20>, <21>, <22>,
<26>, <28>, <32>,
<34>, <36>, <40>,
<43>, <44>,
<46>, <51>,
<52>;
clock-output-names = "ahb_usbotg", "ahb_ehci",
"ahb_ohci", "ahb_ss", "ahb_dma",
"ahb_bist", "ahb_mmc0", "ahb_mmc1",
"ahb_mmc2", "ahb_nand",
"ahb_sdram", "ahb_emac", "ahb_ts",
"ahb_spi0", "ahb_spi1", "ahb_spi2",
"ahb_gps", "ahb_stimer", "ahb_ve",
"ahb_tve", "ahb_lcd", "ahb_csi",
"ahb_hdmi", "ahb_de_be",
"ahb_de_fe", "ahb_iep",
"ahb_mali400";
};
apb0_gates: clk@01c20068 {
#clock-cells = <1>;
compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
clock-indices = <0>, <3>,
<5>, <6>,
<10>;
clock-output-names = "apb0_codec", "apb0_iis",
"apb0_pio", "apb0_ir",
"apb0_keypad";
};
apb1_gates: clk@01c2006c {
#clock-cells = <1>;
compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
clock-indices = <0>, <1>,
<2>, <16>,
<17>, <18>,
<19>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
"apb1_i2c2", "apb1_uart0",
"apb1_uart1", "apb1_uart2",
"apb1_uart3";
};
};
soc@01c00000 { soc@01c00000 {
emac: ethernet@01c0b000 { emac: ethernet@01c0b000 {
compatible = "allwinner,sun4i-a10-emac"; compatible = "allwinner,sun4i-a10-emac";
reg = <0x01c0b000 0x1000>; reg = <0x01c0b000 0x1000>;
interrupts = <55>; interrupts = <55>;
clocks = <&ahb_gates 17>; clocks = <&ccu CLK_AHB_EMAC>;
allwinner,sram = <&emac_sram 1>; allwinner,sram = <&emac_sram 1>;
status = "disabled"; status = "disabled";
}; };
...@@ -169,7 +112,7 @@ mdio: mdio@01c0b080 { ...@@ -169,7 +112,7 @@ mdio: mdio@01c0b080 {
pwm: pwm@01c20e00 { pwm: pwm@01c20e00 {
compatible = "allwinner,sun5i-a10s-pwm"; compatible = "allwinner,sun5i-a10s-pwm";
reg = <0x01c20e00 0xc>; reg = <0x01c20e00 0xc>;
clocks = <&osc24M>; clocks = <&ccu CLK_HOSC>;
#pwm-cells = <3>; #pwm-cells = <3>;
status = "disabled"; status = "disabled";
}; };
...@@ -180,7 +123,7 @@ uart0: serial@01c28000 { ...@@ -180,7 +123,7 @@ uart0: serial@01c28000 {
interrupts = <1>; interrupts = <1>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb1_gates 16>; clocks = <&ccu CLK_APB1_UART0>;
status = "disabled"; status = "disabled";
}; };
...@@ -190,12 +133,16 @@ uart2: serial@01c28800 { ...@@ -190,12 +133,16 @@ uart2: serial@01c28800 {
interrupts = <3>; interrupts = <3>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb1_gates 18>; clocks = <&ccu CLK_APB1_UART2>;
status = "disabled"; status = "disabled";
}; };
}; };
}; };
&ccu {
compatible = "allwinner,sun5i-a10s-ccu";
};
&pio { &pio {
compatible = "allwinner,sun5i-a10s-pinctrl"; compatible = "allwinner,sun5i-a10s-pinctrl";
......
...@@ -61,8 +61,8 @@ framebuffer@0 { ...@@ -61,8 +61,8 @@ framebuffer@0 {
compatible = "allwinner,simple-framebuffer", compatible = "allwinner,simple-framebuffer",
"simple-framebuffer"; "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0"; allwinner,pipeline = "de_be0-lcd0";
clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&de_be_clk>, clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
<&tcon_ch0_clk>, <&dram_gates 26>; <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
status = "disabled"; status = "disabled";
}; };
}; };
...@@ -99,114 +99,6 @@ cpu_crit: cpu_crit { ...@@ -99,114 +99,6 @@ cpu_crit: cpu_crit {
}; };
}; };
clocks {
ahb_gates: clk@01c20060 {
#clock-cells = <1>;
compatible = "allwinner,sun5i-a13-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
clock-indices = <0>, <1>,
<2>, <5>, <6>,
<7>, <8>, <9>,
<10>, <13>,
<14>, <20>,
<21>, <22>,
<28>, <32>, <34>,
<36>, <40>, <44>,
<46>, <51>,
<52>;
clock-output-names = "ahb_usbotg", "ahb_ehci",
"ahb_ohci", "ahb_ss", "ahb_dma",
"ahb_bist", "ahb_mmc0", "ahb_mmc1",
"ahb_mmc2", "ahb_nand",
"ahb_sdram", "ahb_spi0",
"ahb_spi1", "ahb_spi2",
"ahb_stimer", "ahb_ve", "ahb_tve",
"ahb_lcd", "ahb_csi", "ahb_de_be",
"ahb_de_fe", "ahb_iep",
"ahb_mali400";
};
apb0_gates: clk@01c20068 {
#clock-cells = <1>;
compatible = "allwinner,sun5i-a13-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
clock-indices = <0>, <5>,
<6>;
clock-output-names = "apb0_codec", "apb0_pio",
"apb0_ir";
};
apb1_gates: clk@01c2006c {
#clock-cells = <1>;
compatible = "allwinner,sun5i-a13-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
clock-indices = <0>, <1>,
<2>, <17>,
<19>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
"apb1_i2c2", "apb1_uart1",
"apb1_uart3";
};
dram_gates: clk@01c20100 {
#clock-cells = <1>;
compatible = "allwinner,sun5i-a13-dram-gates-clk",
"allwinner,sun4i-a10-gates-clk";
reg = <0x01c20100 0x4>;
clocks = <&pll5 0>;
clock-indices = <0>,
<1>,
<25>,
<26>,
<29>,
<31>;
clock-output-names = "dram_ve",
"dram_csi",
"dram_de_fe",
"dram_de_be",
"dram_ace",
"dram_iep";
};
de_be_clk: clk@01c20104 {
#clock-cells = <0>;
#reset-cells = <0>;
compatible = "allwinner,sun4i-a10-display-clk";
reg = <0x01c20104 0x4>;
clocks = <&pll3>, <&pll7>, <&pll5 1>;
clock-output-names = "de-be";
};
de_fe_clk: clk@01c2010c {
#clock-cells = <0>;
#reset-cells = <0>;
compatible = "allwinner,sun4i-a10-display-clk";
reg = <0x01c2010c 0x4>;
clocks = <&pll3>, <&pll7>, <&pll5 1>;
clock-output-names = "de-fe";
};
tcon_ch0_clk: clk@01c20118 {
#clock-cells = <0>;
#reset-cells = <1>;
compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
reg = <0x01c20118 0x4>;
clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
clock-output-names = "tcon-ch0-sclk";
};
tcon_ch1_clk: clk@01c2012c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
reg = <0x01c2012c 0x4>;
clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
clock-output-names = "tcon-ch1-sclk";
};
};
display-engine { display-engine {
compatible = "allwinner,sun5i-a13-display-engine"; compatible = "allwinner,sun5i-a13-display-engine";
allwinner,pipelines = <&fe0>; allwinner,pipelines = <&fe0>;
...@@ -217,11 +109,11 @@ tcon0: lcd-controller@01c0c000 { ...@@ -217,11 +109,11 @@ tcon0: lcd-controller@01c0c000 {
compatible = "allwinner,sun5i-a13-tcon"; compatible = "allwinner,sun5i-a13-tcon";
reg = <0x01c0c000 0x1000>; reg = <0x01c0c000 0x1000>;
interrupts = <44>; interrupts = <44>;
resets = <&tcon_ch0_clk 1>; resets = <&ccu RST_LCD>;
reset-names = "lcd"; reset-names = "lcd";
clocks = <&ahb_gates 36>, clocks = <&ccu CLK_AHB_LCD>,
<&tcon_ch0_clk>, <&ccu CLK_TCON_CH0>,
<&tcon_ch1_clk>; <&ccu CLK_TCON_CH1>;
clock-names = "ahb", clock-names = "ahb",
"tcon-ch0", "tcon-ch0",
"tcon-ch1"; "tcon-ch1";
...@@ -254,7 +146,7 @@ tcon0_out: port@1 { ...@@ -254,7 +146,7 @@ tcon0_out: port@1 {
pwm: pwm@01c20e00 { pwm: pwm@01c20e00 {
compatible = "allwinner,sun5i-a13-pwm"; compatible = "allwinner,sun5i-a13-pwm";
reg = <0x01c20e00 0xc>; reg = <0x01c20e00 0xc>;
clocks = <&osc24M>; clocks = <&ccu CLK_HOSC>;
#pwm-cells = <3>; #pwm-cells = <3>;
status = "disabled"; status = "disabled";
}; };
...@@ -263,11 +155,11 @@ fe0: display-frontend@01e00000 { ...@@ -263,11 +155,11 @@ fe0: display-frontend@01e00000 {
compatible = "allwinner,sun5i-a13-display-frontend"; compatible = "allwinner,sun5i-a13-display-frontend";
reg = <0x01e00000 0x20000>; reg = <0x01e00000 0x20000>;
interrupts = <47>; interrupts = <47>;
clocks = <&ahb_gates 46>, <&de_fe_clk>, clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
<&dram_gates 25>; <&ccu CLK_DRAM_DE_FE>;
clock-names = "ahb", "mod", clock-names = "ahb", "mod",
"ram"; "ram";
resets = <&de_fe_clk>; resets = <&ccu RST_DE_FE>;
status = "disabled"; status = "disabled";
ports { ports {
...@@ -290,14 +182,14 @@ fe0_out_be0: endpoint@0 { ...@@ -290,14 +182,14 @@ fe0_out_be0: endpoint@0 {
be0: display-backend@01e60000 { be0: display-backend@01e60000 {
compatible = "allwinner,sun5i-a13-display-backend"; compatible = "allwinner,sun5i-a13-display-backend";
reg = <0x01e60000 0x10000>; reg = <0x01e60000 0x10000>;
clocks = <&ahb_gates 44>, <&de_be_clk>, clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
<&dram_gates 26>; <&ccu CLK_DRAM_DE_BE>;
clock-names = "ahb", "mod", clock-names = "ahb", "mod",
"ram"; "ram";
resets = <&de_be_clk>; resets = <&ccu RST_DE_BE>;
status = "disabled"; status = "disabled";
assigned-clocks = <&de_be_clk>; assigned-clocks = <&ccu CLK_DE_BE>;
assigned-clock-rates = <300000000>; assigned-clock-rates = <300000000>;
ports { ports {
...@@ -330,6 +222,10 @@ be0_out_tcon0: endpoint@0 { ...@@ -330,6 +222,10 @@ be0_out_tcon0: endpoint@0 {
}; };
}; };
&ccu {
compatible = "allwinner,sun5i-a13-ccu";
};
&cpu0 { &cpu0 {
clock-latency = <244144>; /* 8 32k periods */ clock-latency = <244144>; /* 8 32k periods */
operating-points = < operating-points = <
......
This diff is collapsed.
...@@ -51,9 +51,9 @@ framebuffer@1 { ...@@ -51,9 +51,9 @@ framebuffer@1 {
compatible = "allwinner,simple-framebuffer", compatible = "allwinner,simple-framebuffer",
"simple-framebuffer"; "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0"; allwinner,pipeline = "de_be0-lcd0-tve0";
clocks = <&ahb_gates 34>, <&ahb_gates 36>, clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
<&ahb_gates 44>, <&de_be_clk>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
<&tcon_ch1_clk>, <&dram_gates 26>; <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
status = "disabled"; status = "disabled";
}; };
}; };
...@@ -62,8 +62,8 @@ soc@01c00000 { ...@@ -62,8 +62,8 @@ soc@01c00000 {
tve0: tv-encoder@01c0a000 { tve0: tv-encoder@01c0a000 {
compatible = "allwinner,sun4i-a10-tv-encoder"; compatible = "allwinner,sun4i-a10-tv-encoder";
reg = <0x01c0a000 0x1000>; reg = <0x01c0a000 0x1000>;
clocks = <&ahb_gates 34>; clocks = <&ccu CLK_AHB_TVE>;
resets = <&tcon_ch0_clk 0>; resets = <&ccu RST_TVE>;
status = "disabled"; status = "disabled";
port { port {
......
This diff is collapsed.
This diff is collapsed.
...@@ -2787,10 +2787,6 @@ config X86_DMA_REMAP ...@@ -2787,10 +2787,6 @@ config X86_DMA_REMAP
bool bool
depends on STA2X11 depends on STA2X11
config PMC_ATOM
def_bool y
depends on PCI
source "net/Kconfig" source "net/Kconfig"
source "drivers/Kconfig" source "drivers/Kconfig"
......
obj-$(CONFIG_PMC_ATOM) += pmc_atom.o
obj-$(CONFIG_PUNIT_ATOM_DEBUG) += punit_atom_debug.o obj-$(CONFIG_PUNIT_ATOM_DEBUG) += punit_atom_debug.o
...@@ -18,6 +18,7 @@ ...@@ -18,6 +18,7 @@
#include <linux/mutex.h> #include <linux/mutex.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/platform_data/clk-lpss.h> #include <linux/platform_data/clk-lpss.h>
#include <linux/platform_data/x86/pmc_atom.h>
#include <linux/pm_domain.h> #include <linux/pm_domain.h>
#include <linux/pm_runtime.h> #include <linux/pm_runtime.h>
#include <linux/delay.h> #include <linux/delay.h>
...@@ -31,7 +32,6 @@ ACPI_MODULE_NAME("acpi_lpss"); ...@@ -31,7 +32,6 @@ ACPI_MODULE_NAME("acpi_lpss");
#include <asm/cpu_device_id.h> #include <asm/cpu_device_id.h>
#include <asm/intel-family.h> #include <asm/intel-family.h>
#include <asm/iosf_mbi.h> #include <asm/iosf_mbi.h>
#include <asm/pmc_atom.h>
#define LPSS_ADDR(desc) ((unsigned long)&desc) #define LPSS_ADDR(desc) ((unsigned long)&desc)
......
...@@ -95,16 +95,17 @@ config COMMON_CLK_CDCE706 ...@@ -95,16 +95,17 @@ config COMMON_CLK_CDCE706
This driver supports TI CDCE706 programmable 3-PLL clock synthesizer. This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
config COMMON_CLK_CDCE925 config COMMON_CLK_CDCE925
tristate "Clock driver for TI CDCE925 devices" tristate "Clock driver for TI CDCE913/925/937/949 devices"
depends on I2C depends on I2C
depends on OF depends on OF
select REGMAP_I2C select REGMAP_I2C
help help
---help--- ---help---
This driver supports the TI CDCE925 programmable clock synthesizer. This driver supports the TI CDCE913/925/937/949 programmable clock
The chip contains two PLLs with spread-spectrum clocking support and synthesizer. Each chip has different number of PLLs and outputs.
five output dividers. The driver only supports the following setup, For example, the CDCE925 contains two PLLs with spread-spectrum
and uses a fixed setting for the output muxes. clocking support and five output dividers. The driver only supports
the following setup, and uses a fixed setting for the output muxes.
Y1 is derived from the input clock Y1 is derived from the input clock
Y2 and Y3 derive from PLL1 Y2 and Y3 derive from PLL1
Y4 and Y5 derive from PLL2 Y4 and Y5 derive from PLL2
...@@ -198,6 +199,16 @@ config COMMON_CLK_OXNAS ...@@ -198,6 +199,16 @@ config COMMON_CLK_OXNAS
---help--- ---help---
Support for the OXNAS SoC Family clocks. Support for the OXNAS SoC Family clocks.
config COMMON_CLK_VC5
tristate "Clock driver for IDT VersaClock5 devices"
depends on I2C
depends on OF
select REGMAP_I2C
help
---help---
This driver supports the IDT VersaClock5 programmable clock
generator.
source "drivers/clk/bcm/Kconfig" source "drivers/clk/bcm/Kconfig"
source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/hisilicon/Kconfig"
source "drivers/clk/mediatek/Kconfig" source "drivers/clk/mediatek/Kconfig"
......
...@@ -46,6 +46,7 @@ obj-$(CONFIG_ARCH_TANGO) += clk-tango4.o ...@@ -46,6 +46,7 @@ obj-$(CONFIG_ARCH_TANGO) += clk-tango4.o
obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
obj-$(CONFIG_ARCH_U300) += clk-u300.o obj-$(CONFIG_ARCH_U300) += clk-u300.o
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
...@@ -87,6 +88,8 @@ obj-y += ti/ ...@@ -87,6 +88,8 @@ obj-y += ti/
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_ARCH_U8500) += ux500/
obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/ obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
ifeq ($(CONFIG_COMMON_CLK), y)
obj-$(CONFIG_X86) += x86/ obj-$(CONFIG_X86) += x86/
endif
obj-$(CONFIG_ARCH_ZX) += zte/ obj-$(CONFIG_ARCH_ZX) += zte/
obj-$(CONFIG_ARCH_ZYNQ) += zynq/ obj-$(CONFIG_ARCH_ZYNQ) += zynq/
...@@ -182,6 +182,7 @@ static int i2s_pll_clk_probe(struct platform_device *pdev) ...@@ -182,6 +182,7 @@ static int i2s_pll_clk_probe(struct platform_device *pdev)
if (IS_ERR(pll_clk->base)) if (IS_ERR(pll_clk->base))
return PTR_ERR(pll_clk->base); return PTR_ERR(pll_clk->base);
memset(&init, 0, sizeof(init));
clk_name = node->name; clk_name = node->name;
init.name = clk_name; init.name = clk_name;
init.ops = &i2s_pll_ops; init.ops = &i2s_pll_ops;
......
This diff is collapsed.
/* /*
* Driver for TI Dual PLL CDCE925 clock synthesizer * Driver for TI Multi PLL CDCE913/925/937/949 clock synthesizer
* *
* This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1 * This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1,
* and Y4/Y5 to PLL2. PLL frequency is set on a first-come-first-serve * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve
* basis. Clients can directly request any frequency that the chip can * basis. Clients can directly request any frequency that the chip can
* deliver using the standard clk framework. In addition, the device can * deliver using the standard clk framework. In addition, the device can
* be configured and activated via the devicetree. * be configured and activated via the devicetree.
...@@ -19,11 +19,32 @@ ...@@ -19,11 +19,32 @@
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/gcd.h> #include <linux/gcd.h>
/* The chip has 2 PLLs which can be routed through dividers to 5 outputs. /* Each chip has different number of PLLs and outputs, for example:
* The CECE925 has 2 PLLs which can be routed through dividers to 5 outputs.
* Model this as 2 PLL clocks which are parents to the outputs. * Model this as 2 PLL clocks which are parents to the outputs.
*/ */
#define NUMBER_OF_PLLS 2
#define NUMBER_OF_OUTPUTS 5 enum {
CDCE913,
CDCE925,
CDCE937,
CDCE949,
};
struct clk_cdce925_chip_info {
int num_plls;
int num_outputs;
};
static const struct clk_cdce925_chip_info clk_cdce925_chip_info_tbl[] = {
[CDCE913] = { .num_plls = 1, .num_outputs = 3 },
[CDCE925] = { .num_plls = 2, .num_outputs = 5 },
[CDCE937] = { .num_plls = 3, .num_outputs = 7 },
[CDCE949] = { .num_plls = 4, .num_outputs = 9 },
};
#define MAX_NUMBER_OF_PLLS 4
#define MAX_NUMBER_OF_OUTPUTS 9
#define CDCE925_REG_GLOBAL1 0x01 #define CDCE925_REG_GLOBAL1 0x01
#define CDCE925_REG_Y1SPIPDIVH 0x02 #define CDCE925_REG_Y1SPIPDIVH 0x02
...@@ -43,7 +64,7 @@ struct clk_cdce925_output { ...@@ -43,7 +64,7 @@ struct clk_cdce925_output {
struct clk_hw hw; struct clk_hw hw;
struct clk_cdce925_chip *chip; struct clk_cdce925_chip *chip;
u8 index; u8 index;
u16 pdiv; /* 1..127 for Y2-Y5; 1..1023 for Y1 */ u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */
}; };
#define to_clk_cdce925_output(_hw) \ #define to_clk_cdce925_output(_hw) \
container_of(_hw, struct clk_cdce925_output, hw) container_of(_hw, struct clk_cdce925_output, hw)
...@@ -60,8 +81,9 @@ struct clk_cdce925_pll { ...@@ -60,8 +81,9 @@ struct clk_cdce925_pll {
struct clk_cdce925_chip { struct clk_cdce925_chip {
struct regmap *regmap; struct regmap *regmap;
struct i2c_client *i2c_client; struct i2c_client *i2c_client;
struct clk_cdce925_pll pll[NUMBER_OF_PLLS]; const struct clk_cdce925_chip_info *chip_info;
struct clk_cdce925_output clk[NUMBER_OF_OUTPUTS]; struct clk_cdce925_pll pll[MAX_NUMBER_OF_PLLS];
struct clk_cdce925_output clk[MAX_NUMBER_OF_OUTPUTS];
}; };
/* ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** */ /* ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** */
...@@ -284,6 +306,18 @@ static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv) ...@@ -284,6 +306,18 @@ static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv)
case 4: case 4:
regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv); regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv);
break; break;
case 5:
regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv);
break;
case 6:
regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv);
break;
case 7:
regmap_update_bits(data->chip->regmap, 0x46, 0x7F, pdiv);
break;
case 8:
regmap_update_bits(data->chip->regmap, 0x47, 0x7F, pdiv);
break;
} }
} }
...@@ -302,6 +336,14 @@ static void cdce925_clk_activate(struct clk_cdce925_output *data) ...@@ -302,6 +336,14 @@ static void cdce925_clk_activate(struct clk_cdce925_output *data)
case 4: case 4:
regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03); regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03);
break; break;
case 5:
case 6:
regmap_update_bits(data->chip->regmap, 0x34, 0x03, 0x03);
break;
case 7:
case 8:
regmap_update_bits(data->chip->regmap, 0x44, 0x03, 0x03);
break;
} }
} }
...@@ -474,15 +516,6 @@ static const struct clk_ops cdce925_clk_y1_ops = { ...@@ -474,15 +516,6 @@ static const struct clk_ops cdce925_clk_y1_ops = {
.set_rate = cdce925_clk_y1_set_rate, .set_rate = cdce925_clk_y1_set_rate,
}; };
static struct regmap_config cdce925_regmap_config = {
.name = "configuration0",
.reg_bits = 8,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
.max_register = 0x2F,
};
#define CDCE925_I2C_COMMAND_BLOCK_TRANSFER 0x00 #define CDCE925_I2C_COMMAND_BLOCK_TRANSFER 0x00
#define CDCE925_I2C_COMMAND_BYTE_TRANSFER 0x80 #define CDCE925_I2C_COMMAND_BYTE_TRANSFER 0x80
...@@ -582,13 +615,19 @@ static int cdce925_probe(struct i2c_client *client, ...@@ -582,13 +615,19 @@ static int cdce925_probe(struct i2c_client *client,
struct clk_cdce925_chip *data; struct clk_cdce925_chip *data;
struct device_node *node = client->dev.of_node; struct device_node *node = client->dev.of_node;
const char *parent_name; const char *parent_name;
const char *pll_clk_name[NUMBER_OF_PLLS] = {NULL,}; const char *pll_clk_name[MAX_NUMBER_OF_PLLS] = {NULL,};
struct clk_init_data init; struct clk_init_data init;
u32 value; u32 value;
int i; int i;
int err; int err;
struct device_node *np_output; struct device_node *np_output;
char child_name[6]; char child_name[6];
struct regmap_config config = {
.name = "configuration0",
.reg_bits = 8,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
};
dev_dbg(&client->dev, "%s\n", __func__); dev_dbg(&client->dev, "%s\n", __func__);
data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
...@@ -596,8 +635,11 @@ static int cdce925_probe(struct i2c_client *client, ...@@ -596,8 +635,11 @@ static int cdce925_probe(struct i2c_client *client,
return -ENOMEM; return -ENOMEM;
data->i2c_client = client; data->i2c_client = client;
data->chip_info = &clk_cdce925_chip_info_tbl[id->driver_data];
config.max_register = CDCE925_OFFSET_PLL +
data->chip_info->num_plls * 0x10 - 1;
data->regmap = devm_regmap_init(&client->dev, &regmap_cdce925_bus, data->regmap = devm_regmap_init(&client->dev, &regmap_cdce925_bus,
&client->dev, &cdce925_regmap_config); &client->dev, &config);
if (IS_ERR(data->regmap)) { if (IS_ERR(data->regmap)) {
dev_err(&client->dev, "failed to allocate register map\n"); dev_err(&client->dev, "failed to allocate register map\n");
return PTR_ERR(data->regmap); return PTR_ERR(data->regmap);
...@@ -626,7 +668,7 @@ static int cdce925_probe(struct i2c_client *client, ...@@ -626,7 +668,7 @@ static int cdce925_probe(struct i2c_client *client,
init.num_parents = parent_name ? 1 : 0; init.num_parents = parent_name ? 1 : 0;
/* Register PLL clocks */ /* Register PLL clocks */
for (i = 0; i < NUMBER_OF_PLLS; ++i) { for (i = 0; i < data->chip_info->num_plls; ++i) {
pll_clk_name[i] = kasprintf(GFP_KERNEL, "%s.pll%d", pll_clk_name[i] = kasprintf(GFP_KERNEL, "%s.pll%d",
client->dev.of_node->name, i); client->dev.of_node->name, i);
init.name = pll_clk_name[i]; init.name = pll_clk_name[i];
...@@ -684,7 +726,7 @@ static int cdce925_probe(struct i2c_client *client, ...@@ -684,7 +726,7 @@ static int cdce925_probe(struct i2c_client *client,
init.ops = &cdce925_clk_ops; init.ops = &cdce925_clk_ops;
init.flags = CLK_SET_RATE_PARENT; init.flags = CLK_SET_RATE_PARENT;
init.num_parents = 1; init.num_parents = 1;
for (i = 1; i < NUMBER_OF_OUTPUTS; ++i) { for (i = 1; i < data->chip_info->num_outputs; ++i) {
init.name = kasprintf(GFP_KERNEL, "%s.Y%d", init.name = kasprintf(GFP_KERNEL, "%s.Y%d",
client->dev.of_node->name, i+1); client->dev.of_node->name, i+1);
data->clk[i].chip = data; data->clk[i].chip = data;
...@@ -702,6 +744,16 @@ static int cdce925_probe(struct i2c_client *client, ...@@ -702,6 +744,16 @@ static int cdce925_probe(struct i2c_client *client,
/* Mux Y4/5 to PLL2 */ /* Mux Y4/5 to PLL2 */
init.parent_names = &pll_clk_name[1]; init.parent_names = &pll_clk_name[1];
break; break;
case 5:
case 6:
/* Mux Y6/7 to PLL3 */
init.parent_names = &pll_clk_name[2];
break;
case 7:
case 8:
/* Mux Y8/9 to PLL4 */
init.parent_names = &pll_clk_name[3];
break;
} }
err = devm_clk_hw_register(&client->dev, &data->clk[i].hw); err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
kfree(init.name); /* clock framework made a copy of the name */ kfree(init.name); /* clock framework made a copy of the name */
...@@ -720,7 +772,7 @@ static int cdce925_probe(struct i2c_client *client, ...@@ -720,7 +772,7 @@ static int cdce925_probe(struct i2c_client *client,
err = 0; err = 0;
error: error:
for (i = 0; i < NUMBER_OF_PLLS; ++i) for (i = 0; i < data->chip_info->num_plls; ++i)
/* clock framework made a copy of the name */ /* clock framework made a copy of the name */
kfree(pll_clk_name[i]); kfree(pll_clk_name[i]);
...@@ -728,13 +780,19 @@ static int cdce925_probe(struct i2c_client *client, ...@@ -728,13 +780,19 @@ static int cdce925_probe(struct i2c_client *client,
} }
static const struct i2c_device_id cdce925_id[] = { static const struct i2c_device_id cdce925_id[] = {
{ "cdce925", 0 }, { "cdce913", CDCE913 },
{ "cdce925", CDCE925 },
{ "cdce937", CDCE937 },
{ "cdce949", CDCE949 },
{ } { }
}; };
MODULE_DEVICE_TABLE(i2c, cdce925_id); MODULE_DEVICE_TABLE(i2c, cdce925_id);
static const struct of_device_id clk_cdce925_of_match[] = { static const struct of_device_id clk_cdce925_of_match[] = {
{ .compatible = "ti,cdce913" },
{ .compatible = "ti,cdce925" }, { .compatible = "ti,cdce925" },
{ .compatible = "ti,cdce937" },
{ .compatible = "ti,cdce949" },
{ }, { },
}; };
MODULE_DEVICE_TABLE(of, clk_cdce925_of_match); MODULE_DEVICE_TABLE(of, clk_cdce925_of_match);
...@@ -750,5 +808,5 @@ static struct i2c_driver cdce925_driver = { ...@@ -750,5 +808,5 @@ static struct i2c_driver cdce925_driver = {
module_i2c_driver(cdce925_driver); module_i2c_driver(cdce925_driver);
MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>"); MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
MODULE_DESCRIPTION("cdce925 driver"); MODULE_DESCRIPTION("TI CDCE913/925/937/949 driver");
MODULE_LICENSE("GPL"); MODULE_LICENSE("GPL");
...@@ -40,8 +40,9 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier) ...@@ -40,8 +40,9 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
return 0; return 0;
pclk = of_clk_get_from_provider(&clkspec); pclk = of_clk_get_from_provider(&clkspec);
if (IS_ERR(pclk)) { if (IS_ERR(pclk)) {
pr_warn("clk: couldn't get parent clock %d for %s\n", if (PTR_ERR(pclk) != -EPROBE_DEFER)
index, node->full_name); pr_warn("clk: couldn't get parent clock %d for %s\n",
index, node->full_name);
return PTR_ERR(pclk); return PTR_ERR(pclk);
} }
...@@ -55,8 +56,9 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier) ...@@ -55,8 +56,9 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
} }
clk = of_clk_get_from_provider(&clkspec); clk = of_clk_get_from_provider(&clkspec);
if (IS_ERR(clk)) { if (IS_ERR(clk)) {
pr_warn("clk: couldn't get assigned clock %d for %s\n", if (PTR_ERR(clk) != -EPROBE_DEFER)
index, node->full_name); pr_warn("clk: couldn't get assigned clock %d for %s\n",
index, node->full_name);
rc = PTR_ERR(clk); rc = PTR_ERR(clk);
goto err; goto err;
} }
...@@ -99,8 +101,9 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier) ...@@ -99,8 +101,9 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier)
clk = of_clk_get_from_provider(&clkspec); clk = of_clk_get_from_provider(&clkspec);
if (IS_ERR(clk)) { if (IS_ERR(clk)) {
pr_warn("clk: couldn't get clock %d for %s\n", if (PTR_ERR(clk) != -EPROBE_DEFER)
index, node->full_name); pr_warn("clk: couldn't get clock %d for %s\n",
index, node->full_name);
return PTR_ERR(clk); return PTR_ERR(clk);
} }
......
...@@ -59,6 +59,10 @@ struct cs2000_priv { ...@@ -59,6 +59,10 @@ struct cs2000_priv {
struct i2c_client *client; struct i2c_client *client;
struct clk *clk_in; struct clk *clk_in;
struct clk *ref_clk; struct clk *ref_clk;
/* suspend/resume */
unsigned long saved_rate;
unsigned long saved_parent_rate;
}; };
static const struct of_device_id cs2000_of_match[] = { static const struct of_device_id cs2000_of_match[] = {
...@@ -286,6 +290,9 @@ static int __cs2000_set_rate(struct cs2000_priv *priv, int ch, ...@@ -286,6 +290,9 @@ static int __cs2000_set_rate(struct cs2000_priv *priv, int ch,
if (ret < 0) if (ret < 0)
return ret; return ret;
priv->saved_rate = rate;
priv->saved_parent_rate = parent_rate;
return 0; return 0;
} }
...@@ -489,9 +496,24 @@ static int cs2000_probe(struct i2c_client *client, ...@@ -489,9 +496,24 @@ static int cs2000_probe(struct i2c_client *client,
return ret; return ret;
} }
static int cs2000_resume(struct device *dev)
{
struct cs2000_priv *priv = dev_get_drvdata(dev);
int ch = 0; /* it uses ch0 only at this point */
return __cs2000_set_rate(priv, ch,
priv->saved_rate,
priv->saved_parent_rate);
}
static const struct dev_pm_ops cs2000_pm_ops = {
.resume_early = cs2000_resume,
};
static struct i2c_driver cs2000_driver = { static struct i2c_driver cs2000_driver = {
.driver = { .driver = {
.name = "cs2000-cp", .name = "cs2000-cp",
.pm = &cs2000_pm_ops,
.of_match_table = cs2000_of_match, .of_match_table = cs2000_of_match,
}, },
.probe = cs2000_probe, .probe = cs2000_probe,
......
...@@ -290,13 +290,15 @@ static int scpi_clocks_probe(struct platform_device *pdev) ...@@ -290,13 +290,15 @@ static int scpi_clocks_probe(struct platform_device *pdev)
of_node_put(child); of_node_put(child);
return ret; return ret;
} }
}
/* Add the virtual cpufreq device */
cpufreq_dev = platform_device_register_simple("scpi-cpufreq",
-1, NULL, 0);
if (IS_ERR(cpufreq_dev))
pr_warn("unable to register cpufreq device");
if (match->data != &scpi_dvfs_ops)
continue;
/* Add the virtual cpufreq device if it's DVFS clock provider */
cpufreq_dev = platform_device_register_simple("scpi-cpufreq",
-1, NULL, 0);
if (IS_ERR(cpufreq_dev))
pr_warn("unable to register cpufreq device");
}
return 0; return 0;
} }
......
This diff is collapsed.
This diff is collapsed.
...@@ -97,7 +97,8 @@ static int wm831x_fll_prepare(struct clk_hw *hw) ...@@ -97,7 +97,8 @@ static int wm831x_fll_prepare(struct clk_hw *hw)
if (ret != 0) if (ret != 0)
dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret); dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret);
usleep_range(2000, 2000); /* wait 2-3 ms for new frequency taking effect */
usleep_range(2000, 3000);
return ret; return ret;
} }
......
...@@ -14,6 +14,13 @@ config COMMON_CLK_HI3519 ...@@ -14,6 +14,13 @@ config COMMON_CLK_HI3519
help help
Build the clock driver for hi3519. Build the clock driver for hi3519.
config COMMON_CLK_HI3660
bool "Hi3660 Clock Driver"
depends on ARCH_HISI || COMPILE_TEST
default ARCH_HISI
help
Build the clock driver for hi3660.
config COMMON_CLK_HI3798CV200 config COMMON_CLK_HI3798CV200
tristate "Hi3798CV200 Clock Driver" tristate "Hi3798CV200 Clock Driver"
depends on ARCH_HISI || COMPILE_TEST depends on ARCH_HISI || COMPILE_TEST
......
...@@ -9,6 +9,7 @@ obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o ...@@ -9,6 +9,7 @@ obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o
obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
obj-$(CONFIG_RESET_HISI) += reset.o obj-$(CONFIG_RESET_HISI) += reset.o
......
This diff is collapsed.
...@@ -120,6 +120,7 @@ struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name, ...@@ -120,6 +120,7 @@ struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name,
sclk->bit_idx = bit_idx; sclk->bit_idx = bit_idx;
sclk->flags = clk_gate_flags; sclk->flags = clk_gate_flags;
sclk->hw.init = &init; sclk->hw.init = &init;
sclk->lock = lock;
clk = clk_register(dev, &sclk->hw); clk = clk_register(dev, &sclk->hw);
if (IS_ERR(clk)) if (IS_ERR(clk))
......
...@@ -592,15 +592,20 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) ...@@ -592,15 +592,20 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
imx6q_mmdc_ch1_mask_handshake(base); imx6q_mmdc_ch1_mask_handshake(base);
/* if (clk_on_imx6qp()) {
* The LDB_DI0/1_SEL muxes are registered read-only due to a hardware clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
* bug. Set the muxes to the requested values before registering the clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
* ldb_di_sel clocks. } else {
*/ /*
init_ldb_clks(np, base); * The LDB_DI0/1_SEL muxes are registered read-only due to a hardware
* bug. Set the muxes to the requested values before registering the
* ldb_di_sel clocks.
*/
init_ldb_clks(np, base);
clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_ldb("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_ldb("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
}
clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
......
...@@ -803,6 +803,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) ...@@ -803,6 +803,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
clks[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_gate4("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0); clks[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_gate4("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0);
clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate4("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0); clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate4("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0);
clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate4("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0); clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate4("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0);
clks[IMX7D_OCOTP_CLK] = imx_clk_gate4("ocotp_clk", "ipg_root_clk", base + 0x4230, 0);
clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4420, 0); clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4420, 0);
clks[IMX7D_SDMA_CORE_CLK] = imx_clk_gate4("sdma_root_clk", "ahb_root_clk", base + 0x4480, 0); clks[IMX7D_SDMA_CORE_CLK] = imx_clk_gate4("sdma_root_clk", "ahb_root_clk", base + 0x4480, 0);
clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate4("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0); clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate4("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0);
......
...@@ -21,6 +21,9 @@ ...@@ -21,6 +21,9 @@
#define PLL_NUM_OFFSET 0x10 #define PLL_NUM_OFFSET 0x10
#define PLL_DENOM_OFFSET 0x20 #define PLL_DENOM_OFFSET 0x20
#define PLL_VF610_NUM_OFFSET 0x20
#define PLL_VF610_DENOM_OFFSET 0x30
#define BM_PLL_POWER (0x1 << 12) #define BM_PLL_POWER (0x1 << 12)
#define BM_PLL_LOCK (0x1 << 31) #define BM_PLL_LOCK (0x1 << 31)
#define IMX7_ENET_PLL_POWER (0x1 << 5) #define IMX7_ENET_PLL_POWER (0x1 << 5)
...@@ -300,6 +303,99 @@ static const struct clk_ops clk_pllv3_av_ops = { ...@@ -300,6 +303,99 @@ static const struct clk_ops clk_pllv3_av_ops = {
.set_rate = clk_pllv3_av_set_rate, .set_rate = clk_pllv3_av_set_rate,
}; };
struct clk_pllv3_vf610_mf {
u32 mfi; /* integer part, can be 20 or 22 */
u32 mfn; /* numerator, 30-bit value */
u32 mfd; /* denominator, 30-bit value, must be less than mfn */
};
static unsigned long clk_pllv3_vf610_mf_to_rate(unsigned long parent_rate,
struct clk_pllv3_vf610_mf mf)
{
u64 temp64;
temp64 = parent_rate;
temp64 *= mf.mfn;
do_div(temp64, mf.mfd);
return (parent_rate * mf.mfi) + temp64;
}
static struct clk_pllv3_vf610_mf clk_pllv3_vf610_rate_to_mf(
unsigned long parent_rate, unsigned long rate)
{
struct clk_pllv3_vf610_mf mf;
u64 temp64;
mf.mfi = (rate >= 22 * parent_rate) ? 22 : 20;
mf.mfd = 0x3fffffff; /* use max supported value for best accuracy */
if (rate <= parent_rate * mf.mfi)
mf.mfn = 0;
else if (rate >= parent_rate * (mf.mfi + 1))
mf.mfn = mf.mfd - 1;
else {
/* rate = parent_rate * (mfi + mfn/mfd) */
temp64 = rate - parent_rate * mf.mfi;
temp64 *= mf.mfd;
do_div(temp64, parent_rate);
mf.mfn = temp64;
}
return mf;
}
static unsigned long clk_pllv3_vf610_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_pllv3 *pll = to_clk_pllv3(hw);
struct clk_pllv3_vf610_mf mf;
mf.mfn = readl_relaxed(pll->base + PLL_VF610_NUM_OFFSET);
mf.mfd = readl_relaxed(pll->base + PLL_VF610_DENOM_OFFSET);
mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;
return clk_pllv3_vf610_mf_to_rate(parent_rate, mf);
}
static long clk_pllv3_vf610_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_pllv3_vf610_mf mf = clk_pllv3_vf610_rate_to_mf(*prate, rate);
return clk_pllv3_vf610_mf_to_rate(*prate, mf);
}
static int clk_pllv3_vf610_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_pllv3 *pll = to_clk_pllv3(hw);
struct clk_pllv3_vf610_mf mf =
clk_pllv3_vf610_rate_to_mf(parent_rate, rate);
u32 val;
val = readl_relaxed(pll->base);
if (mf.mfi == 20)
val &= ~pll->div_mask; /* clear bit for mfi=20 */
else
val |= pll->div_mask; /* set bit for mfi=22 */
writel_relaxed(val, pll->base);
writel_relaxed(mf.mfn, pll->base + PLL_VF610_NUM_OFFSET);
writel_relaxed(mf.mfd, pll->base + PLL_VF610_DENOM_OFFSET);
return clk_pllv3_wait_lock(pll);
}
static const struct clk_ops clk_pllv3_vf610_ops = {
.prepare = clk_pllv3_prepare,
.unprepare = clk_pllv3_unprepare,
.is_prepared = clk_pllv3_is_prepared,
.recalc_rate = clk_pllv3_vf610_recalc_rate,
.round_rate = clk_pllv3_vf610_round_rate,
.set_rate = clk_pllv3_vf610_set_rate,
};
static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw, static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate) unsigned long parent_rate)
{ {
...@@ -334,6 +430,9 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, ...@@ -334,6 +430,9 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
case IMX_PLLV3_SYS: case IMX_PLLV3_SYS:
ops = &clk_pllv3_sys_ops; ops = &clk_pllv3_sys_ops;
break; break;
case IMX_PLLV3_SYS_VF610:
ops = &clk_pllv3_vf610_ops;
break;
case IMX_PLLV3_USB_VF610: case IMX_PLLV3_USB_VF610:
pll->div_shift = 1; pll->div_shift = 1;
case IMX_PLLV3_USB: case IMX_PLLV3_USB:
......
...@@ -219,8 +219,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) ...@@ -219,8 +219,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", PLL6_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); clk[VF610_CLK_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", PLL6_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clk[VF610_CLK_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", PLL7_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); clk[VF610_CLK_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", PLL7_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1); clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS_VF610, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1);
clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1); clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_SYS_VF610, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1);
clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll3", "pll3_bypass_src", PLL3_CTRL, 0x2); clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll3", "pll3_bypass_src", PLL3_CTRL, 0x2);
clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", PLL4_CTRL, 0x7f); clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", PLL4_CTRL, 0x7f);
clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3); clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3);
......
...@@ -34,6 +34,7 @@ enum imx_pllv3_type { ...@@ -34,6 +34,7 @@ enum imx_pllv3_type {
IMX_PLLV3_AV, IMX_PLLV3_AV,
IMX_PLLV3_ENET, IMX_PLLV3_ENET,
IMX_PLLV3_ENET_IMX7, IMX_PLLV3_ENET_IMX7,
IMX_PLLV3_SYS_VF610,
}; };
struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
......
...@@ -8,52 +8,53 @@ config COMMON_CLK_MEDIATEK ...@@ -8,52 +8,53 @@ config COMMON_CLK_MEDIATEK
config COMMON_CLK_MT2701 config COMMON_CLK_MT2701
bool "Clock driver for Mediatek MT2701" bool "Clock driver for Mediatek MT2701"
depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
select COMMON_CLK_MEDIATEK select COMMON_CLK_MEDIATEK
default ARCH_MEDIATEK default ARCH_MEDIATEK && ARM
---help--- ---help---
This driver supports Mediatek MT2701 basic clocks. This driver supports Mediatek MT2701 basic clocks.
config COMMON_CLK_MT2701_MMSYS config COMMON_CLK_MT2701_MMSYS
bool "Clock driver for Mediatek MT2701 mmsys" bool "Clock driver for Mediatek MT2701 mmsys"
select COMMON_CLK_MT2701 depends on COMMON_CLK_MT2701
---help--- ---help---
This driver supports Mediatek MT2701 mmsys clocks. This driver supports Mediatek MT2701 mmsys clocks.
config COMMON_CLK_MT2701_IMGSYS config COMMON_CLK_MT2701_IMGSYS
bool "Clock driver for Mediatek MT2701 imgsys" bool "Clock driver for Mediatek MT2701 imgsys"
select COMMON_CLK_MT2701 depends on COMMON_CLK_MT2701
---help--- ---help---
This driver supports Mediatek MT2701 imgsys clocks. This driver supports Mediatek MT2701 imgsys clocks.
config COMMON_CLK_MT2701_VDECSYS config COMMON_CLK_MT2701_VDECSYS
bool "Clock driver for Mediatek MT2701 vdecsys" bool "Clock driver for Mediatek MT2701 vdecsys"
select COMMON_CLK_MT2701 depends on COMMON_CLK_MT2701
---help--- ---help---
This driver supports Mediatek MT2701 vdecsys clocks. This driver supports Mediatek MT2701 vdecsys clocks.
config COMMON_CLK_MT2701_HIFSYS config COMMON_CLK_MT2701_HIFSYS
bool "Clock driver for Mediatek MT2701 hifsys" bool "Clock driver for Mediatek MT2701 hifsys"
select COMMON_CLK_MT2701 depends on COMMON_CLK_MT2701
---help--- ---help---
This driver supports Mediatek MT2701 hifsys clocks. This driver supports Mediatek MT2701 hifsys clocks.
config COMMON_CLK_MT2701_ETHSYS config COMMON_CLK_MT2701_ETHSYS
bool "Clock driver for Mediatek MT2701 ethsys" bool "Clock driver for Mediatek MT2701 ethsys"
select COMMON_CLK_MT2701 depends on COMMON_CLK_MT2701
---help--- ---help---
This driver supports Mediatek MT2701 ethsys clocks. This driver supports Mediatek MT2701 ethsys clocks.
config COMMON_CLK_MT2701_BDPSYS config COMMON_CLK_MT2701_BDPSYS
bool "Clock driver for Mediatek MT2701 bdpsys" bool "Clock driver for Mediatek MT2701 bdpsys"
select COMMON_CLK_MT2701 depends on COMMON_CLK_MT2701
---help--- ---help---
This driver supports Mediatek MT2701 bdpsys clocks. This driver supports Mediatek MT2701 bdpsys clocks.
config COMMON_CLK_MT8135 config COMMON_CLK_MT8135
bool "Clock driver for Mediatek MT8135" bool "Clock driver for Mediatek MT8135"
depends on ARCH_MEDIATEK || COMPILE_TEST depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
select COMMON_CLK_MEDIATEK select COMMON_CLK_MEDIATEK
default ARCH_MEDIATEK default ARCH_MEDIATEK && ARM
---help--- ---help---
This driver supports Mediatek MT8135 clocks. This driver supports Mediatek MT8135 clocks.
......
...@@ -607,7 +607,6 @@ static int meson8b_clkc_probe(struct platform_device *pdev) ...@@ -607,7 +607,6 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
/* Populate the base address for the MPEG clks */ /* Populate the base address for the MPEG clks */
meson8b_mpeg_clk_sel.reg = clk_base + (u32)meson8b_mpeg_clk_sel.reg; meson8b_mpeg_clk_sel.reg = clk_base + (u32)meson8b_mpeg_clk_sel.reg;
meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg; meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg;
meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg;
/* Populate base address for gates */ /* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++) for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++)
......
...@@ -9,7 +9,7 @@ obj-$(CONFIG_ARMADA_39X_CLK) += armada-39x.o ...@@ -9,7 +9,7 @@ obj-$(CONFIG_ARMADA_39X_CLK) += armada-39x.o
obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-xtal.o obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-xtal.o
obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-tbg.o obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-tbg.o
obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-periph.o obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-periph.o
obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o mv98dx3236.o
obj-$(CONFIG_ARMADA_AP806_SYSCON) += ap806-system-controller.o obj-$(CONFIG_ARMADA_AP806_SYSCON) += ap806-system-controller.o
obj-$(CONFIG_ARMADA_CP110_SYSCON) += cp110-system-controller.o obj-$(CONFIG_ARMADA_CP110_SYSCON) += cp110-system-controller.o
obj-$(CONFIG_DOVE_CLK) += dove.o dove-divider.o obj-$(CONFIG_DOVE_CLK) += dove.o dove-divider.o
......
...@@ -55,21 +55,39 @@ static int ap806_syscon_clk_probe(struct platform_device *pdev) ...@@ -55,21 +55,39 @@ static int ap806_syscon_clk_probe(struct platform_device *pdev)
freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK; freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
switch (freq_mode) { switch (freq_mode) {
case 0x0 ... 0x5: case 0x0:
case 0x1:
cpuclk_freq = 2000; cpuclk_freq = 2000;
break; break;
case 0x6 ... 0xB: case 0x6:
case 0x7:
cpuclk_freq = 1800; cpuclk_freq = 1800;
break; break;
case 0xC ... 0x11: case 0x4:
case 0xB:
case 0xD:
cpuclk_freq = 1600; cpuclk_freq = 1600;
break; break;
case 0x12 ... 0x16: case 0x1a:
cpuclk_freq = 1400; cpuclk_freq = 1400;
break; break;
case 0x17 ... 0x19: case 0x14:
case 0x17:
cpuclk_freq = 1300; cpuclk_freq = 1300;
break; break;
case 0x19:
cpuclk_freq = 1200;
break;
case 0x13:
case 0x1d:
cpuclk_freq = 1000;
break;
case 0x1c:
cpuclk_freq = 800;
break;
case 0x1b:
cpuclk_freq = 600;
break;
default: default:
dev_err(&pdev->dev, "invalid SAR value\n"); dev_err(&pdev->dev, "invalid SAR value\n");
return -EINVAL; return -EINVAL;
......
...@@ -52,6 +52,12 @@ static u32 __init axp_get_tclk_freq(void __iomem *sar) ...@@ -52,6 +52,12 @@ static u32 __init axp_get_tclk_freq(void __iomem *sar)
return 250000000; return 250000000;
} }
/* MV98DX3236 TCLK frequency is fixed to 200MHz */
static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar)
{
return 200000000;
}
static const u32 axp_cpu_freqs[] __initconst = { static const u32 axp_cpu_freqs[] __initconst = {
1000000000, 1000000000,
1066000000, 1066000000,
...@@ -89,6 +95,12 @@ static u32 __init axp_get_cpu_freq(void __iomem *sar) ...@@ -89,6 +95,12 @@ static u32 __init axp_get_cpu_freq(void __iomem *sar)
return cpu_freq; return cpu_freq;
} }
/* MV98DX3236 CLK frequency is fixed to 800MHz */
static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar)
{
return 800000000;
}
static const int axp_nbclk_ratios[32][2] __initconst = { static const int axp_nbclk_ratios[32][2] __initconst = {
{0, 1}, {1, 2}, {2, 2}, {2, 2}, {0, 1}, {1, 2}, {2, 2}, {2, 2},
{1, 2}, {1, 2}, {1, 1}, {2, 3}, {1, 2}, {1, 2}, {1, 1}, {2, 3},
...@@ -158,6 +170,11 @@ static const struct coreclk_soc_desc axp_coreclks = { ...@@ -158,6 +170,11 @@ static const struct coreclk_soc_desc axp_coreclks = {
.num_ratios = ARRAY_SIZE(axp_coreclk_ratios), .num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
}; };
static const struct coreclk_soc_desc mv98dx3236_coreclks = {
.get_tclk_freq = mv98dx3236_get_tclk_freq,
.get_cpu_freq = mv98dx3236_get_cpu_freq,
};
/* /*
* Clock Gating Control * Clock Gating Control
*/ */
...@@ -195,6 +212,15 @@ static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = { ...@@ -195,6 +212,15 @@ static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = {
{ } { }
}; };
static const struct clk_gating_soc_desc mv98dx3236_gating_desc[] __initconst = {
{ "ge1", NULL, 3, 0 },
{ "ge0", NULL, 4, 0 },
{ "pex00", NULL, 5, 0 },
{ "sdio", NULL, 17, 0 },
{ "xor0", NULL, 22, 0 },
{ }
};
static void __init axp_clk_init(struct device_node *np) static void __init axp_clk_init(struct device_node *np)
{ {
struct device_node *cgnp = struct device_node *cgnp =
......
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...@@ -245,3 +245,11 @@ static void __init of_cpu_clk_setup(struct device_node *node) ...@@ -245,3 +245,11 @@ static void __init of_cpu_clk_setup(struct device_node *node)
CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock", CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
of_cpu_clk_setup); of_cpu_clk_setup);
static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
{
of_clk_add_provider(node, of_clk_src_simple_get, NULL);
}
CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
of_mv98dx3236_cpu_clk_setup);
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