Commit 5dac808a authored by Ville Syrjälä's avatar Ville Syrjälä

drm/i915: s/plane_res_b/blocks/ etc.

Rename a bunch of the skl+ watermark struct members to
have sensible names. Avoids me having to think what
plane_res_b/etc. means.

Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210305153610.12177-7-ville.syrjala@linux.intel.comReviewed-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
parent a5941b47
...@@ -9216,12 +9216,12 @@ static void verify_wm_state(struct intel_crtc *crtc, ...@@ -9216,12 +9216,12 @@ static void verify_wm_state(struct intel_crtc *crtc,
drm_err(&dev_priv->drm, drm_err(&dev_priv->drm,
"[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
plane->base.base.id, plane->base.name, level, plane->base.base.id, plane->base.name, level,
sw_wm_level->plane_en, sw_wm_level->enable,
sw_wm_level->plane_res_b, sw_wm_level->blocks,
sw_wm_level->plane_res_l, sw_wm_level->lines,
hw_wm_level->plane_en, hw_wm_level->enable,
hw_wm_level->plane_res_b, hw_wm_level->blocks,
hw_wm_level->plane_res_l); hw_wm_level->lines);
} }
hw_wm_level = &hw->wm.planes[plane->id].trans_wm; hw_wm_level = &hw->wm.planes[plane->id].trans_wm;
...@@ -9231,12 +9231,12 @@ static void verify_wm_state(struct intel_crtc *crtc, ...@@ -9231,12 +9231,12 @@ static void verify_wm_state(struct intel_crtc *crtc,
drm_err(&dev_priv->drm, drm_err(&dev_priv->drm,
"[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
plane->base.base.id, plane->base.name, plane->base.base.id, plane->base.name,
sw_wm_level->plane_en, sw_wm_level->enable,
sw_wm_level->plane_res_b, sw_wm_level->blocks,
sw_wm_level->plane_res_l, sw_wm_level->lines,
hw_wm_level->plane_en, hw_wm_level->enable,
hw_wm_level->plane_res_b, hw_wm_level->blocks,
hw_wm_level->plane_res_l); hw_wm_level->lines);
} }
/* DDB */ /* DDB */
......
...@@ -725,9 +725,9 @@ struct intel_pipe_wm { ...@@ -725,9 +725,9 @@ struct intel_pipe_wm {
struct skl_wm_level { struct skl_wm_level {
u16 min_ddb_alloc; u16 min_ddb_alloc;
u16 plane_res_b; u16 blocks;
u8 plane_res_l; u8 lines;
bool plane_en; bool enable;
bool ignore_lines; bool ignore_lines;
bool can_sagv; bool can_sagv;
}; };
......
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