Commit 5e93cbad authored by Ngai-Mint Kwan's avatar Ngai-Mint Kwan Committed by Jeff Kirsher

fm10k: Reset mailbox global interrupts

When a data path reset is initiated, write control to the PCIE_GMBX is
yanked from the switch manager. The switch manager writes to this
register to clear mailbox global interrupt bits as part of its mailbox
interrupt handling routine. When the device recovers from the data path
reset and these bits are not cleared, it will prevent future mailbox
global interrupts from being triggered. Upon confirming that the device
has exited from a data path reset, clear these bits to ensure the proper
functioning of the mailbox global interrupt.
Signed-off-by: default avatarNgai-Mint Kwan <ngai-mint.kwan@intel.com>
Signed-off-by: default avatarJacob Keller <jacob.e.keller@intel.com>
Tested-by: default avatarKrishneil Singh <Krishneil.k.singh@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 9d73edee
...@@ -41,6 +41,8 @@ struct fm10k_mbx_info; ...@@ -41,6 +41,8 @@ struct fm10k_mbx_info;
#define FM10K_MBX_ACK_INTERRUPT 0x00000010 #define FM10K_MBX_ACK_INTERRUPT 0x00000010
#define FM10K_MBX_INTERRUPT_ENABLE 0x00000020 #define FM10K_MBX_INTERRUPT_ENABLE 0x00000020
#define FM10K_MBX_INTERRUPT_DISABLE 0x00000040 #define FM10K_MBX_INTERRUPT_DISABLE 0x00000040
#define FM10K_MBX_GLOBAL_REQ_INTERRUPT 0x00000200
#define FM10K_MBX_GLOBAL_ACK_INTERRUPT 0x00000400
#define FM10K_MBICR(_n) ((_n) + 0x18840) #define FM10K_MBICR(_n) ((_n) + 0x18840)
#define FM10K_GMBX 0x18842 #define FM10K_GMBX 0x18842
......
...@@ -77,6 +77,10 @@ static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw) ...@@ -77,6 +77,10 @@ static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw)
if (!(reg & FM10K_IP_NOTINRESET)) if (!(reg & FM10K_IP_NOTINRESET))
err = FM10K_ERR_RESET_FAILED; err = FM10K_ERR_RESET_FAILED;
/* Reset mailbox global interrupts */
reg = FM10K_MBX_GLOBAL_REQ_INTERRUPT | FM10K_MBX_GLOBAL_ACK_INTERRUPT;
fm10k_write_reg(hw, FM10K_GMBX, reg);
out: out:
return err; return err;
} }
......
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