Commit 5f885448 authored by Hans de Goede's avatar Hans de Goede Committed by Khalid Elmously

ASoC: rt5670: Correct RT5670_LDO_SEL_MASK

BugLink: https://bugs.launchpad.net/bugs/1889928

commit 5cacc6f5 upstream.

The RT5670_PWR_ANLG1 register has 3 bits to select the LDO voltage,
so the correct mask is 0x7 not 0x3.

Because of this wrong mask we were programming the ldo bits
to a setting of binary 001 (0x05 & 0x03) instead of binary 101
when moving to SND_SOC_BIAS_PREPARE.

According to the datasheet 001 is a reserved value, so no idea
what it did, since the driver was working fine before I guess we
got lucky and it does something which is ok.

Fixes: 5e8351de ("ASoC: add RT5670 CODEC driver")
Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20200628155231.71089-3-hdegoede@redhat.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: default avatarKamal Mostafa <kamal@canonical.com>
Signed-off-by: default avatarKhalid Elmously <khalid.elmously@canonical.com>
parent 0f5a2ea9
...@@ -760,7 +760,7 @@ ...@@ -760,7 +760,7 @@
#define RT5670_PWR_VREF2_BIT 4 #define RT5670_PWR_VREF2_BIT 4
#define RT5670_PWR_FV2 (0x1 << 3) #define RT5670_PWR_FV2 (0x1 << 3)
#define RT5670_PWR_FV2_BIT 3 #define RT5670_PWR_FV2_BIT 3
#define RT5670_LDO_SEL_MASK (0x3) #define RT5670_LDO_SEL_MASK (0x7)
#define RT5670_LDO_SEL_SFT 0 #define RT5670_LDO_SEL_SFT 0
/* Power Management for Analog 2 (0x64) */ /* Power Management for Analog 2 (0x64) */
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment