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Commit 60713996 authored by Ben Dooks's avatar Ben Dooks
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ARM: Merge for-2635/s5pv210-clock 

Merge branch 'for-2635/s5pv210-clock' into for-linus/samsung2
parents d16067b2 f64cacc3
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Showing with 720 additions and 122 deletions
arch/arm/mach-s5pv210/clock.c
View file @ 60713996
......@@ -31,6 +31,128 @@
#include <plat/clock-clksrc.h>
#include <plat/s5pv210.h>
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
.id = -1,
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
};
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
.id = -1,
},
.sources = &clk_src_epll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
};
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
.id = -1,
},
.sources = &clk_src_mpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
};
static struct clk *clkset_armclk_list[] = {
[0] = &clk_mout_apll.clk,
[1] = &clk_mout_mpll.clk,
};
static struct clksrc_sources clkset_armclk = {
.sources = clkset_armclk_list,
.nr_sources = ARRAY_SIZE(clkset_armclk_list),
};
static struct clksrc_clk clk_armclk = {
.clk = {
.name = "armclk",
.id = -1,
},
.sources = &clkset_armclk,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
};
static struct clksrc_clk clk_hclk_msys = {
.clk = {
.name = "hclk_msys",
.id = -1,
.parent = &clk_armclk.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
};
static struct clksrc_clk clk_pclk_msys = {
.clk = {
.name = "pclk_msys",
.id = -1,
.parent = &clk_hclk_msys.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
};
static struct clksrc_clk clk_sclk_a2m = {
.clk = {
.name = "sclk_a2m",
.id = -1,
.parent = &clk_mout_apll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
};
static struct clk *clkset_hclk_sys_list[] = {
[0] = &clk_mout_mpll.clk,
[1] = &clk_sclk_a2m.clk,
};
static struct clksrc_sources clkset_hclk_sys = {
.sources = clkset_hclk_sys_list,
.nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
};
static struct clksrc_clk clk_hclk_dsys = {
.clk = {
.name = "hclk_dsys",
.id = -1,
},
.sources = &clkset_hclk_sys,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
};
static struct clksrc_clk clk_pclk_dsys = {
.clk = {
.name = "pclk_dsys",
.id = -1,
.parent = &clk_hclk_dsys.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
};
static struct clksrc_clk clk_hclk_psys = {
.clk = {
.name = "hclk_psys",
.id = -1,
},
.sources = &clkset_hclk_sys,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
};
static struct clksrc_clk clk_pclk_psys = {
.clk = {
.name = "pclk_psys",
.id = -1,
.parent = &clk_hclk_psys.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
};
static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
......@@ -51,176 +173,226 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
}
static struct clk clk_h200 = {
.name = "hclk200",
static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable);
}
static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
}
static struct clk clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m",
.id = -1,
.rate = 27000000,
};
static struct clk clk_h100 = {
.name = "hclk100",
static struct clk clk_sclk_hdmiphy = {
.name = "sclk_hdmiphy",
.id = -1,
};
static struct clk clk_h166 = {
.name = "hclk166",
static struct clk clk_sclk_usbphy0 = {
.name = "sclk_usbphy0",
.id = -1,
};
static struct clk clk_h133 = {
.name = "hclk133",
static struct clk clk_sclk_usbphy1 = {
.name = "sclk_usbphy1",
.id = -1,
};
static struct clk clk_p100 = {
.name = "pclk100",
static struct clk clk_pcmcdclk0 = {
.name = "pcmcdclk",
.id = -1,
};
static struct clk clk_p83 = {
.name = "pclk83",
static struct clk clk_pcmcdclk1 = {
.name = "pcmcdclk",
.id = -1,
};
static struct clk clk_p66 = {
.name = "pclk66",
static struct clk clk_pcmcdclk2 = {
.name = "pcmcdclk",
.id = -1,
};
static struct clk *sys_clks[] = {
&clk_h200,
&clk_h100,
&clk_h166,
&clk_h133,
&clk_p100,
&clk_p83,
&clk_p66
static struct clk *clkset_vpllsrc_list[] = {
[0] = &clk_fin_vpll,
[1] = &clk_sclk_hdmi27m,
};
static struct clksrc_sources clkset_vpllsrc = {
.sources = clkset_vpllsrc_list,
.nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
};
static struct clksrc_clk clk_vpllsrc = {
.clk = {
.name = "vpll_src",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 7),
},
.sources = &clkset_vpllsrc,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
};
static struct clk *clkset_sclk_vpll_list[] = {
[0] = &clk_vpllsrc.clk,
[1] = &clk_fout_vpll,
};
static struct clksrc_sources clkset_sclk_vpll = {
.sources = clkset_sclk_vpll_list,
.nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
};
static struct clksrc_clk clk_sclk_vpll = {
.clk = {
.name = "sclk_vpll",
.id = -1,
},
.sources = &clkset_sclk_vpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
};
static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) / 2;
}
static struct clk_ops clk_hclk_imem_ops = {
.get_rate = s5pv210_clk_imem_get_rate,
};
static struct clk init_clocks_disable[] = {
{
.name = "rot",
.id = -1,
.parent = &clk_h166,
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1<<29),
}, {
.name = "otg",
.id = -1,
.parent = &clk_h133,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<16),
}, {
.name = "usb-host",
.id = -1,
.parent = &clk_h133,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<17),
}, {
.name = "lcd",
.id = -1,
.parent = &clk_h166,
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<0),
}, {
.name = "cfcon",
.id = 0,
.parent = &clk_h133,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<25),
}, {
.name = "hsmmc",
.id = 0,
.parent = &clk_h133,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<16),
}, {
.name = "hsmmc",
.id = 1,
.parent = &clk_h133,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<17),
}, {
.name = "hsmmc",
.id = 2,
.parent = &clk_h133,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<18),
}, {
.name = "hsmmc",
.id = 3,
.parent = &clk_h133,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<19),
}, {
.name = "systimer",
.id = -1,
.parent = &clk_p66,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<16),
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_p66,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<22),
}, {
.name = "rtc",
.id = -1,
.parent = &clk_p66,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<15),
}, {
.name = "i2c",
.id = 0,
.parent = &clk_p66,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<7),
}, {
.name = "i2c",
.id = 1,
.parent = &clk_p66,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<8),
}, {
.name = "i2c",
.id = 2,
.parent = &clk_p66,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<9),
}, {
.name = "spi",
.id = 0,
.parent = &clk_p66,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<12),
}, {
.name = "spi",
.id = 1,
.parent = &clk_p66,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<13),
}, {
.name = "spi",
.id = 2,
.parent = &clk_p66,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<14),
}, {
.name = "timers",
.id = -1,
.parent = &clk_p66,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<23),
}, {
.name = "adc",
.id = -1,
.parent = &clk_p66,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<24),
}, {
.name = "keypad",
.id = -1,
.parent = &clk_p66,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<21),
}, {
......@@ -246,106 +418,537 @@ static struct clk init_clocks_disable[] = {
static struct clk init_clocks[] = {
{
.name = "hclk_imem",
.id = -1,
.parent = &clk_hclk_msys.clk,
.ctrlbit = (1 << 5),
.enable = s5pv210_clk_ip0_ctrl,
.ops = &clk_hclk_imem_ops,
}, {
.name = "uart",
.id = 0,
.parent = &clk_p66,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<7),
}, {
.name = "uart",
.id = 1,
.parent = &clk_p66,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<8),
}, {
.name = "uart",
.id = 2,
.parent = &clk_p66,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<9),
}, {
.name = "uart",
.id = 3,
.parent = &clk_p66,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<10),
},
};
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
static struct clk *clkset_uart_list[] = {
[6] = &clk_mout_mpll.clk,
[7] = &clk_mout_epll.clk,
};
static struct clksrc_sources clkset_uart = {
.sources = clkset_uart_list,
.nr_sources = ARRAY_SIZE(clkset_uart_list),
};
static struct clk *clkset_group1_list[] = {
[0] = &clk_sclk_a2m.clk,
[1] = &clk_mout_mpll.clk,
[2] = &clk_mout_epll.clk,
[3] = &clk_sclk_vpll.clk,
};
static struct clksrc_sources clkset_group1 = {
.sources = clkset_group1_list,
.nr_sources = ARRAY_SIZE(clkset_group1_list),
};
static struct clk *clkset_sclk_onenand_list[] = {
[0] = &clk_hclk_psys.clk,
[1] = &clk_hclk_dsys.clk,
};
static struct clksrc_sources clkset_sclk_onenand = {
.sources = clkset_sclk_onenand_list,
.nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list),
};
static struct clk *clkset_sclk_dac_list[] = {
[0] = &clk_sclk_vpll.clk,
[1] = &clk_sclk_hdmiphy,
};
static struct clksrc_sources clkset_sclk_dac = {
.sources = clkset_sclk_dac_list,
.nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
};
static struct clksrc_clk clk_sclk_dac = {
.clk = {
.name = "sclk_dac",
.id = -1,
.ctrlbit = (1 << 10),
.enable = s5pv210_clk_ip1_ctrl,
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
.sources = &clkset_sclk_dac,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
};
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
static struct clksrc_clk clk_sclk_pixel = {
.clk = {
.name = "sclk_pixel",
.id = -1,
.parent = &clk_sclk_vpll.clk,
},
.sources = &clk_src_epll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
};
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
static struct clk *clkset_sclk_hdmi_list[] = {
[0] = &clk_sclk_pixel.clk,
[1] = &clk_sclk_hdmiphy,
};
static struct clksrc_sources clkset_sclk_hdmi = {
.sources = clkset_sclk_hdmi_list,
.nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
};
static struct clksrc_clk clk_sclk_hdmi = {
.clk = {
.name = "sclk_hdmi",
.id = -1,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1 << 11),
},
.sources = &clk_src_mpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
.sources = &clkset_sclk_hdmi,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
};
static struct clk *clkset_uart_list[] = {
static struct clk *clkset_sclk_mixer_list[] = {
[0] = &clk_sclk_dac.clk,
[1] = &clk_sclk_hdmi.clk,
};
static struct clksrc_sources clkset_sclk_mixer = {
.sources = clkset_sclk_mixer_list,
.nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
};
static struct clk *clkset_sclk_audio0_list[] = {
[0] = &clk_ext_xtal_mux,
[1] = &clk_pcmcdclk0,
[2] = &clk_sclk_hdmi27m,
[3] = &clk_sclk_usbphy0,
[4] = &clk_sclk_usbphy1,
[5] = &clk_sclk_hdmiphy,
[6] = &clk_mout_mpll.clk,
[7] = &clk_mout_epll.clk,
[8] = &clk_sclk_vpll.clk,
};
static struct clksrc_sources clkset_uart = {
.sources = clkset_uart_list,
.nr_sources = ARRAY_SIZE(clkset_uart_list),
static struct clksrc_sources clkset_sclk_audio0 = {
.sources = clkset_sclk_audio0_list,
.nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
};
static struct clksrc_clk clk_sclk_audio0 = {
.clk = {
.name = "sclk_audio",
.id = 0,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 4),
},
.sources = &clkset_sclk_audio0,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
};
static struct clk *clkset_sclk_audio1_list[] = {
[0] = &clk_ext_xtal_mux,
[1] = &clk_pcmcdclk1,
[2] = &clk_sclk_hdmi27m,
[3] = &clk_sclk_usbphy0,
[4] = &clk_sclk_usbphy1,
[5] = &clk_sclk_hdmiphy,
[6] = &clk_mout_mpll.clk,
[7] = &clk_mout_epll.clk,
[8] = &clk_sclk_vpll.clk,
};
static struct clksrc_sources clkset_sclk_audio1 = {
.sources = clkset_sclk_audio1_list,
.nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list),
};
static struct clksrc_clk clk_sclk_audio1 = {
.clk = {
.name = "sclk_audio",
.id = 1,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 5),
},
.sources = &clkset_sclk_audio1,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
};
static struct clk *clkset_sclk_audio2_list[] = {
[0] = &clk_ext_xtal_mux,
[1] = &clk_pcmcdclk0,
[2] = &clk_sclk_hdmi27m,
[3] = &clk_sclk_usbphy0,
[4] = &clk_sclk_usbphy1,
[5] = &clk_sclk_hdmiphy,
[6] = &clk_mout_mpll.clk,
[7] = &clk_mout_epll.clk,
[8] = &clk_sclk_vpll.clk,
};
static struct clksrc_sources clkset_sclk_audio2 = {
.sources = clkset_sclk_audio2_list,
.nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list),
};
static struct clksrc_clk clk_sclk_audio2 = {
.clk = {
.name = "sclk_audio",
.id = 2,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 6),
},
.sources = &clkset_sclk_audio2,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
};
static struct clk *clkset_sclk_spdif_list[] = {
[0] = &clk_sclk_audio0.clk,
[1] = &clk_sclk_audio1.clk,
[2] = &clk_sclk_audio2.clk,
};
static struct clksrc_sources clkset_sclk_spdif = {
.sources = clkset_sclk_spdif_list,
.nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
};
static struct clk *clkset_group2_list[] = {
[0] = &clk_ext_xtal_mux,
[1] = &clk_xusbxti,
[2] = &clk_sclk_hdmi27m,
[3] = &clk_sclk_usbphy0,
[4] = &clk_sclk_usbphy1,
[5] = &clk_sclk_hdmiphy,
[6] = &clk_mout_mpll.clk,
[7] = &clk_mout_epll.clk,
[8] = &clk_sclk_vpll.clk,
};
static struct clksrc_sources clkset_group2 = {
.sources = clkset_group2_list,
.nr_sources = ARRAY_SIZE(clkset_group2_list),
};
static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "uclk1",
.name = "sclk_dmc",
.id = -1,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
}, {
.clk = {
.name = "sclk_onenand",
.id = -1,
},
.sources = &clkset_sclk_onenand,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
.reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
}, {
.clk = {
.name = "uclk1",
.id = 0,
.ctrlbit = (1<<17),
.enable = s5pv210_clk_ip3_ctrl,
},
.sources = &clkset_uart,
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
}
}, {
.clk = {
.name = "uclk1",
.id = 1,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 18),
},
.sources = &clkset_uart,
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
}, {
.clk = {
.name = "uclk1",
.id = 2,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 19),
},
.sources = &clkset_uart,
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
}, {
.clk = {
.name = "uclk1",
.id = 3,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 20),
},
.sources = &clkset_uart,
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
}, {
.clk = {
.name = "sclk_mixer",
.id = -1,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1 << 9),
},
.sources = &clkset_sclk_mixer,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
}, {
.clk = {
.name = "sclk_spdif",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 27),
},
.sources = &clkset_sclk_spdif,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
}, {
.clk = {
.name = "sclk_fimc",
.id = 0,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 24),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
}, {
.clk = {
.name = "sclk_fimc",
.id = 1,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 25),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
}, {
.clk = {
.name = "sclk_fimc",
.id = 2,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 26),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
}, {
.clk = {
.name = "sclk_cam",
.id = 0,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
}, {
.clk = {
.name = "sclk_cam",
.id = 1,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
}, {
.clk = {
.name = "sclk_fimd",
.id = -1,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
}, {
.clk = {
.name = "sclk_mmc",
.id = 0,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1 << 16),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_mmc",
.id = 1,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1 << 17),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "sclk_mmc",
.id = 2,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1 << 18),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
}, {
.clk = {
.name = "sclk_mmc",
.id = 3,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1 << 19),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
}, {
.clk = {
.name = "sclk_mfc",
.id = -1,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 16),
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "sclk_g2d",
.id = -1,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 12),
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
}, {
.clk = {
.name = "sclk_g3d",
.id = -1,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 8),
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_csis",
.id = -1,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 31),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
}, {
.clk = {
.name = "sclk_spi",
.id = 0,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 12),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_spi",
.id = 1,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 13),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "sclk_pwi",
.id = -1,
.enable = &s5pv210_clk_ip4_ctrl,
.ctrlbit = (1 << 2),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
}, {
.clk = {
.name = "sclk_pwm",
.id = -1,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 23),
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
},
};
/* Clock initialisation code */
static struct clksrc_clk *init_parents[] = {
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
&clk_mout_epll,
&clk_mout_mpll,
&clk_armclk,
&clk_hclk_msys,
&clk_sclk_a2m,
&clk_hclk_dsys,
&clk_hclk_psys,
&clk_pclk_msys,
&clk_pclk_dsys,
&clk_pclk_psys,
&clk_vpllsrc,
&clk_sclk_vpll,
&clk_sclk_dac,
&clk_sclk_pixel,
&clk_sclk_hdmi,
};
#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
void __init_or_cpufreq s5pv210_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long xtal;
unsigned long vpllsrc;
unsigned long armclk;
unsigned long hclk200;
unsigned long hclk166;
unsigned long hclk133;
unsigned long pclk100;
unsigned long pclk83;
unsigned long pclk66;
unsigned long hclk_msys;
unsigned long hclk_dsys;
unsigned long hclk_psys;
unsigned long pclk_msys;
unsigned long pclk_dsys;
unsigned long pclk_psys;
unsigned long apll;
unsigned long mpll;
unsigned long epll;
unsigned long vpll;
unsigned int ptr;
u32 clkdiv0, clkdiv1;
......@@ -368,59 +971,46 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld",
apll, mpll, epll);
armclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_APLL);
if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX200_MASK)
hclk200 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200);
else
hclk200 = armclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200);
if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX166_MASK) {
hclk166 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M);
hclk166 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166);
} else
hclk166 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166);
if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX133_MASK) {
hclk133 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M);
hclk133 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133);
} else
hclk133 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133);
pclk100 = hclk200 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK100);
pclk83 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83);
pclk66 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66);
printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld, \
HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
armclk, hclk200, hclk166, hclk133, pclk100, pclk83, pclk66);
vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
clk_fout_apll.rate = apll;
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_vpll.rate = vpll;
clk_f.rate = armclk;
clk_h.rate = hclk133;
clk_p.rate = pclk66;
clk_p66.rate = pclk66;
clk_p83.rate = pclk83;
clk_h133.rate = hclk133;
clk_h166.rate = hclk166;
clk_h200.rate = hclk200;
printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
apll, mpll, epll, vpll);
armclk = clk_get_rate(&clk_armclk.clk);
hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
"HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
armclk, hclk_msys, hclk_dsys, hclk_psys,
pclk_msys, pclk_dsys, pclk_psys);
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
s3c_set_clksrc(init_parents[ptr], true);
clk_f.rate = armclk;
clk_h.rate = hclk_psys;
clk_p.rate = pclk_psys;
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
}
static struct clk *clks[] __initdata = {
&clk_mout_epll.clk,
&clk_mout_mpll.clk,
&clk_sclk_hdmi27m,
&clk_sclk_hdmiphy,
&clk_sclk_usbphy0,
&clk_sclk_usbphy1,
&clk_pcmcdclk0,
&clk_pcmcdclk1,
&clk_pcmcdclk2,
};
void __init s5pv210_register_clocks(void)
......@@ -433,13 +1023,12 @@ void __init s5pv210_register_clocks(void)
if (ret > 0)
printk(KERN_ERR "Failed to register %u clocks\n", ret);
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
ret = s3c24xx_register_clocks(sys_clks, ARRAY_SIZE(sys_clks));
if (ret > 0)
printk(KERN_ERR "Failed to register system clocks\n");
clkp = init_clocks_disable;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
......
arch/arm/plat-s5p/clock.c
View file @ 60713996
......@@ -74,6 +74,13 @@ struct clk clk_fout_epll = {
.ctrlbit = (1 << 31),
};
/* VPLL clock output */
struct clk clk_fout_vpll = {
.name = "fout_vpll",
.id = -1,
.ctrlbit = (1 << 31),
};
/* ARM clock */
struct clk clk_arm = {
.name = "armclk",
......@@ -138,6 +145,7 @@ static struct clk *s5p_clks[] __initdata = {
&clk_fout_apll,
&clk_fout_mpll,
&clk_fout_epll,
&clk_fout_vpll,
&clk_arm,
&clk_vpll,
};
......
arch/arm/plat-s5p/include/plat/s5p-clock.h
View file @ 60713996
......@@ -28,6 +28,7 @@ extern struct clk clk_48m;
extern struct clk clk_fout_apll;
extern struct clk clk_fout_mpll;
extern struct clk clk_fout_epll;
extern struct clk clk_fout_vpll;
extern struct clk clk_arm;
extern struct clk clk_vpll;
......
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