Commit 60f01d7a authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Sudeep Holla

arm64: dts: juno: add coresight CPU debug nodes

Add Coresight CPU debug nodes for Juno r0, r1 & r2. The CPU
debug areas are mapped at the same address for all revisions,
like the ETM, even though the CPUs have changed from r1 to r2.

Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mathieu Poirier <mathieu.porier@linaro.org>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
[arranged nodes in ascending order with respect to register addresses]
Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
parent 2ea659a9
...@@ -202,6 +202,15 @@ stm_out_port: endpoint { ...@@ -202,6 +202,15 @@ stm_out_port: endpoint {
}; };
}; };
cpu_debug0: cpu_debug@22010000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0x22010000 0x0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
etm0: etm@22040000 { etm0: etm@22040000 {
compatible = "arm,coresight-etm4x", "arm,primecell"; compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x22040000 0 0x1000>; reg = <0 0x22040000 0 0x1000>;
...@@ -252,6 +261,15 @@ cluster0_funnel_in_port1: endpoint { ...@@ -252,6 +261,15 @@ cluster0_funnel_in_port1: endpoint {
}; };
}; };
cpu_debug1: cpu_debug@22110000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0x22110000 0x0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
etm1: etm@22140000 { etm1: etm@22140000 {
compatible = "arm,coresight-etm4x", "arm,primecell"; compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x22140000 0 0x1000>; reg = <0 0x22140000 0 0x1000>;
...@@ -266,6 +284,15 @@ cluster0_etm1_out_port: endpoint { ...@@ -266,6 +284,15 @@ cluster0_etm1_out_port: endpoint {
}; };
}; };
cpu_debug2: cpu_debug@23010000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0x23010000 0x0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
etm2: etm@23040000 { etm2: etm@23040000 {
compatible = "arm,coresight-etm4x", "arm,primecell"; compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23040000 0 0x1000>; reg = <0 0x23040000 0 0x1000>;
...@@ -330,6 +357,15 @@ cluster1_funnel_in_port3: endpoint { ...@@ -330,6 +357,15 @@ cluster1_funnel_in_port3: endpoint {
}; };
}; };
cpu_debug3: cpu_debug@23110000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0x23110000 0x0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
etm3: etm@23140000 { etm3: etm@23140000 {
compatible = "arm,coresight-etm4x", "arm,primecell"; compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23140000 0 0x1000>; reg = <0 0x23140000 0 0x1000>;
...@@ -344,6 +380,15 @@ cluster1_etm1_out_port: endpoint { ...@@ -344,6 +380,15 @@ cluster1_etm1_out_port: endpoint {
}; };
}; };
cpu_debug4: cpu_debug@23210000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0x23210000 0x0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
etm4: etm@23240000 { etm4: etm@23240000 {
compatible = "arm,coresight-etm4x", "arm,primecell"; compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23240000 0 0x1000>; reg = <0 0x23240000 0 0x1000>;
...@@ -358,6 +403,15 @@ cluster1_etm2_out_port: endpoint { ...@@ -358,6 +403,15 @@ cluster1_etm2_out_port: endpoint {
}; };
}; };
cpu_debug5: cpu_debug@23310000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0x23310000 0x0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
};
etm5: etm@23340000 { etm5: etm@23340000 {
compatible = "arm,coresight-etm4x", "arm,primecell"; compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23340000 0 0x1000>; reg = <0 0x23340000 0 0x1000>;
......
...@@ -281,3 +281,27 @@ &replicator_in_port0 { ...@@ -281,3 +281,27 @@ &replicator_in_port0 {
&stm_out_port { &stm_out_port {
remote-endpoint = <&csys1_funnel_in_port0>; remote-endpoint = <&csys1_funnel_in_port0>;
}; };
&cpu_debug0 {
cpu = <&A57_0>;
};
&cpu_debug1 {
cpu = <&A57_1>;
};
&cpu_debug2 {
cpu = <&A53_0>;
};
&cpu_debug3 {
cpu = <&A53_1>;
};
&cpu_debug4 {
cpu = <&A53_2>;
};
&cpu_debug5 {
cpu = <&A53_3>;
};
...@@ -281,3 +281,27 @@ &replicator_in_port0 { ...@@ -281,3 +281,27 @@ &replicator_in_port0 {
&stm_out_port { &stm_out_port {
remote-endpoint = <&csys1_funnel_in_port0>; remote-endpoint = <&csys1_funnel_in_port0>;
}; };
&cpu_debug0 {
cpu = <&A72_0>;
};
&cpu_debug1 {
cpu = <&A72_1>;
};
&cpu_debug2 {
cpu = <&A53_0>;
};
&cpu_debug3 {
cpu = <&A53_1>;
};
&cpu_debug4 {
cpu = <&A53_2>;
};
&cpu_debug5 {
cpu = <&A53_3>;
};
...@@ -268,3 +268,27 @@ main_funnel_in_port2: endpoint { ...@@ -268,3 +268,27 @@ main_funnel_in_port2: endpoint {
}; };
}; };
}; };
&cpu_debug0 {
cpu = <&A57_0>;
};
&cpu_debug1 {
cpu = <&A57_1>;
};
&cpu_debug2 {
cpu = <&A53_0>;
};
&cpu_debug3 {
cpu = <&A53_1>;
};
&cpu_debug4 {
cpu = <&A53_2>;
};
&cpu_debug5 {
cpu = <&A53_3>;
};
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