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Commit 60fe9ff9 authored by Jiaran Zhang's avatar Jiaran Zhang Committed by David S. Miller
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net: hns3: initialize each member of structure array on a separate line 

To make the format of each member initialization of structure array
clearer, initialize each member on a separate line.
Signed-off-by: default avatarJiaran Zhang <zhangjiaran@huawei.com>
Signed-off-by: default avatarGuangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 49f9df5b
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Showing with 1116 additions and 549 deletions
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
View file @ 60fe9ff9
......@@ -4,468 +4,895 @@
#include "hclge_err.h"
static const struct hclge_hw_error hclge_imp_tcm_ecc_int[] = {
{ .int_msk = BIT(1), .msg = "imp_itcm0_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(3), .msg = "imp_itcm1_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(5), .msg = "imp_itcm2_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(7), .msg = "imp_itcm3_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(9), .msg = "imp_dtcm0_mem0_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(11), .msg = "imp_dtcm0_mem1_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(13), .msg = "imp_dtcm1_mem0_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(15), .msg = "imp_dtcm1_mem1_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(17), .msg = "imp_itcm4_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(1),
.msg = "imp_itcm0_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(3),
.msg = "imp_itcm1_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(5),
.msg = "imp_itcm2_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(7),
.msg = "imp_itcm3_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(9),
.msg = "imp_dtcm0_mem0_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(11),
.msg = "imp_dtcm0_mem1_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(13),
.msg = "imp_dtcm1_mem0_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(15),
.msg = "imp_dtcm1_mem1_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(17),
.msg = "imp_itcm4_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_cmdq_nic_mem_ecc_int[] = {
{ .int_msk = BIT(1), .msg = "cmdq_nic_rx_depth_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(3), .msg = "cmdq_nic_tx_depth_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(5), .msg = "cmdq_nic_rx_tail_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(7), .msg = "cmdq_nic_tx_tail_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(9), .msg = "cmdq_nic_rx_head_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(11), .msg = "cmdq_nic_tx_head_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(13), .msg = "cmdq_nic_rx_addr_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(15), .msg = "cmdq_nic_tx_addr_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(17), .msg = "cmdq_rocee_rx_depth_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(19), .msg = "cmdq_rocee_tx_depth_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(21), .msg = "cmdq_rocee_rx_tail_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(23), .msg = "cmdq_rocee_tx_tail_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(25), .msg = "cmdq_rocee_rx_head_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(27), .msg = "cmdq_rocee_tx_head_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(29), .msg = "cmdq_rocee_rx_addr_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(31), .msg = "cmdq_rocee_tx_addr_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(1),
.msg = "cmdq_nic_rx_depth_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(3),
.msg = "cmdq_nic_tx_depth_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(5),
.msg = "cmdq_nic_rx_tail_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(7),
.msg = "cmdq_nic_tx_tail_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(9),
.msg = "cmdq_nic_rx_head_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(11),
.msg = "cmdq_nic_tx_head_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(13),
.msg = "cmdq_nic_rx_addr_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(15),
.msg = "cmdq_nic_tx_addr_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(17),
.msg = "cmdq_rocee_rx_depth_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(19),
.msg = "cmdq_rocee_tx_depth_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(21),
.msg = "cmdq_rocee_rx_tail_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(23),
.msg = "cmdq_rocee_tx_tail_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(25),
.msg = "cmdq_rocee_rx_head_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(27),
.msg = "cmdq_rocee_tx_head_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(29),
.msg = "cmdq_rocee_rx_addr_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(31),
.msg = "cmdq_rocee_tx_addr_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_tqp_int_ecc_int[] = {
{ .int_msk = BIT(6), .msg = "tqp_int_cfg_even_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(7), .msg = "tqp_int_cfg_odd_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(8), .msg = "tqp_int_ctrl_even_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(9), .msg = "tqp_int_ctrl_odd_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(10), .msg = "tx_que_scan_int_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(11), .msg = "rx_que_scan_int_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(6),
.msg = "tqp_int_cfg_even_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(7),
.msg = "tqp_int_cfg_odd_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(8),
.msg = "tqp_int_ctrl_even_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(9),
.msg = "tqp_int_ctrl_odd_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(10),
.msg = "tx_que_scan_int_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(11),
.msg = "rx_que_scan_int_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_msix_sram_ecc_int[] = {
{ .int_msk = BIT(1), .msg = "msix_nic_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(3), .msg = "msix_rocee_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(1),
.msg = "msix_nic_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(3),
.msg = "msix_rocee_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_igu_int[] = {
{ .int_msk = BIT(0), .msg = "igu_rx_buf0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "igu_rx_buf1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "igu_rx_buf0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "igu_rx_buf1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_igu_egu_tnl_int[] = {
{ .int_msk = BIT(0), .msg = "rx_buf_overflow",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(1), .msg = "rx_stp_fifo_overflow",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "rx_stp_fifo_underflow",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "tx_buf_overflow",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(4), .msg = "tx_buf_underrun",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "rx_stp_buf_overflow",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "rx_buf_overflow",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(1),
.msg = "rx_stp_fifo_overflow",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "rx_stp_fifo_underflow",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "tx_buf_overflow",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(4),
.msg = "tx_buf_underrun",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "rx_stp_buf_overflow",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ncsi_err_int[] = {
{ .int_msk = BIT(1), .msg = "ncsi_tx_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(1),
.msg = "ncsi_tx_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ppp_mpf_abnormal_int_st1[] = {
{ .int_msk = BIT(0), .msg = "vf_vlan_ad_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(1), .msg = "umv_mcast_group_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "umv_key_mem0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "umv_key_mem1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(4), .msg = "umv_key_mem2_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "umv_key_mem3_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(6), .msg = "umv_ad_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(7), .msg = "rss_tc_mode_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(8), .msg = "rss_idt_mem0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(9), .msg = "rss_idt_mem1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(10), .msg = "rss_idt_mem2_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(11), .msg = "rss_idt_mem3_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(12), .msg = "rss_idt_mem4_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(13), .msg = "rss_idt_mem5_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(14), .msg = "rss_idt_mem6_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(15), .msg = "rss_idt_mem7_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(16), .msg = "rss_idt_mem8_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(17), .msg = "rss_idt_mem9_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(18), .msg = "rss_idt_mem10_ecc_m1bit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(19), .msg = "rss_idt_mem11_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(20), .msg = "rss_idt_mem12_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(21), .msg = "rss_idt_mem13_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(22), .msg = "rss_idt_mem14_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(23), .msg = "rss_idt_mem15_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(24), .msg = "port_vlan_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(25), .msg = "mcast_linear_table_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(26), .msg = "mcast_result_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(27), .msg = "flow_director_ad_mem0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(28), .msg = "flow_director_ad_mem1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(29), .msg = "rx_vlan_tag_memory_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(30), .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "vf_vlan_ad_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(1),
.msg = "umv_mcast_group_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "umv_key_mem0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "umv_key_mem1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(4),
.msg = "umv_key_mem2_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "umv_key_mem3_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(6),
.msg = "umv_ad_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(7),
.msg = "rss_tc_mode_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(8),
.msg = "rss_idt_mem0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(9),
.msg = "rss_idt_mem1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(10),
.msg = "rss_idt_mem2_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(11),
.msg = "rss_idt_mem3_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(12),
.msg = "rss_idt_mem4_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(13),
.msg = "rss_idt_mem5_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(14),
.msg = "rss_idt_mem6_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(15),
.msg = "rss_idt_mem7_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(16),
.msg = "rss_idt_mem8_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(17),
.msg = "rss_idt_mem9_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(18),
.msg = "rss_idt_mem10_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(19),
.msg = "rss_idt_mem11_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(20),
.msg = "rss_idt_mem12_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(21),
.msg = "rss_idt_mem13_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(22),
.msg = "rss_idt_mem14_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(23),
.msg = "rss_idt_mem15_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(24),
.msg = "port_vlan_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(25),
.msg = "mcast_linear_table_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(26),
.msg = "mcast_result_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(27),
.msg = "flow_director_ad_mem0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(28),
.msg = "flow_director_ad_mem1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(29),
.msg = "rx_vlan_tag_memory_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(30),
.msg = "Tx_UP_mapping_config_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ppp_pf_abnormal_int[] = {
{ .int_msk = BIT(0), .msg = "tx_vlan_tag_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(1), .msg = "rss_list_tc_unassigned_queue_err",
.reset_level = HNAE3_NONE_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "tx_vlan_tag_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(1),
.msg = "rss_list_tc_unassigned_queue_err",
.reset_level = HNAE3_NONE_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ppp_mpf_abnormal_int_st3[] = {
{ .int_msk = BIT(0), .msg = "hfs_fifo_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(1), .msg = "rslt_descr_fifo_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "tx_vlan_tag_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "FD_CN0_memory_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(4), .msg = "FD_CN1_memory_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "GRO_AD_memory_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "hfs_fifo_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(1),
.msg = "rslt_descr_fifo_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "tx_vlan_tag_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "FD_CN0_memory_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(4),
.msg = "FD_CN1_memory_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "GRO_AD_memory_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_tm_sch_rint[] = {
{ .int_msk = BIT(1), .msg = "tm_sch_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "tm_sch_port_shap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "tm_sch_port_shap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(4), .msg = "tm_sch_pg_pshap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "tm_sch_pg_pshap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(6), .msg = "tm_sch_pg_cshap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(7), .msg = "tm_sch_pg_cshap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(8), .msg = "tm_sch_pri_pshap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(9), .msg = "tm_sch_pri_pshap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(10), .msg = "tm_sch_pri_cshap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(11), .msg = "tm_sch_pri_cshap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(12), .msg = "tm_sch_port_shap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(13), .msg = "tm_sch_port_shap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(14), .msg = "tm_sch_pg_pshap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(15), .msg = "tm_sch_pg_pshap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(16), .msg = "tm_sch_pg_cshap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(17), .msg = "tm_sch_pg_cshap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(18), .msg = "tm_sch_pri_pshap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(19), .msg = "tm_sch_pri_pshap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(20), .msg = "tm_sch_pri_cshap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(21), .msg = "tm_sch_pri_cshap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(22), .msg = "tm_sch_rq_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(23), .msg = "tm_sch_rq_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(24), .msg = "tm_sch_nq_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(25), .msg = "tm_sch_nq_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(26), .msg = "tm_sch_roce_up_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(27), .msg = "tm_sch_roce_up_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(28), .msg = "tm_sch_rcb_byte_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(29), .msg = "tm_sch_rcb_byte_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(30), .msg = "tm_sch_ssu_byte_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(31), .msg = "tm_sch_ssu_byte_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(1),
.msg = "tm_sch_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "tm_sch_port_shap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "tm_sch_port_shap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(4),
.msg = "tm_sch_pg_pshap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "tm_sch_pg_pshap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(6),
.msg = "tm_sch_pg_cshap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(7),
.msg = "tm_sch_pg_cshap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(8),
.msg = "tm_sch_pri_pshap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(9),
.msg = "tm_sch_pri_pshap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(10),
.msg = "tm_sch_pri_cshap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(11),
.msg = "tm_sch_pri_cshap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(12),
.msg = "tm_sch_port_shap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(13),
.msg = "tm_sch_port_shap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(14),
.msg = "tm_sch_pg_pshap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(15),
.msg = "tm_sch_pg_pshap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(16),
.msg = "tm_sch_pg_cshap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(17),
.msg = "tm_sch_pg_cshap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(18),
.msg = "tm_sch_pri_pshap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(19),
.msg = "tm_sch_pri_pshap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(20),
.msg = "tm_sch_pri_cshap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(21),
.msg = "tm_sch_pri_cshap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(22),
.msg = "tm_sch_rq_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(23),
.msg = "tm_sch_rq_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(24),
.msg = "tm_sch_nq_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(25),
.msg = "tm_sch_nq_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(26),
.msg = "tm_sch_roce_up_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(27),
.msg = "tm_sch_roce_up_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(28),
.msg = "tm_sch_rcb_byte_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(29),
.msg = "tm_sch_rcb_byte_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(30),
.msg = "tm_sch_ssu_byte_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(31),
.msg = "tm_sch_ssu_byte_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_qcn_fifo_rint[] = {
{ .int_msk = BIT(0), .msg = "qcn_shap_gp0_sch_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(1), .msg = "qcn_shap_gp0_sch_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "qcn_shap_gp1_sch_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "qcn_shap_gp1_sch_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(4), .msg = "qcn_shap_gp2_sch_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "qcn_shap_gp2_sch_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(6), .msg = "qcn_shap_gp3_sch_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(7), .msg = "qcn_shap_gp3_sch_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(8), .msg = "qcn_shap_gp0_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(9), .msg = "qcn_shap_gp0_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(10), .msg = "qcn_shap_gp1_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(11), .msg = "qcn_shap_gp1_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(12), .msg = "qcn_shap_gp2_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(13), .msg = "qcn_shap_gp2_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(14), .msg = "qcn_shap_gp3_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(15), .msg = "qcn_shap_gp3_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(16), .msg = "qcn_byte_info_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(17), .msg = "qcn_byte_info_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "qcn_shap_gp0_sch_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(1),
.msg = "qcn_shap_gp0_sch_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "qcn_shap_gp1_sch_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "qcn_shap_gp1_sch_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(4),
.msg = "qcn_shap_gp2_sch_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "qcn_shap_gp2_sch_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(6),
.msg = "qcn_shap_gp3_sch_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(7),
.msg = "qcn_shap_gp3_sch_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(8),
.msg = "qcn_shap_gp0_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(9),
.msg = "qcn_shap_gp0_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(10),
.msg = "qcn_shap_gp1_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(11),
.msg = "qcn_shap_gp1_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(12),
.msg = "qcn_shap_gp2_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(13),
.msg = "qcn_shap_gp2_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(14),
.msg = "qcn_shap_gp3_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(15),
.msg = "qcn_shap_gp3_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(16),
.msg = "qcn_byte_info_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(17),
.msg = "qcn_byte_info_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_qcn_ecc_rint[] = {
{ .int_msk = BIT(1), .msg = "qcn_byte_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "qcn_time_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "qcn_fb_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(7), .msg = "qcn_link_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(9), .msg = "qcn_rate_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(11), .msg = "qcn_tmplt_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(13), .msg = "qcn_shap_cfg_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(15), .msg = "qcn_gp0_barrel_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(17), .msg = "qcn_gp1_barrel_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(19), .msg = "qcn_gp2_barrel_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(21), .msg = "qcn_gp3_barral_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(1),
.msg = "qcn_byte_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "qcn_time_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "qcn_fb_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(7),
.msg = "qcn_link_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(9),
.msg = "qcn_rate_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(11),
.msg = "qcn_tmplt_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(13),
.msg = "qcn_shap_cfg_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(15),
.msg = "qcn_gp0_barrel_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(17),
.msg = "qcn_gp1_barrel_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(19),
.msg = "qcn_gp2_barrel_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(21),
.msg = "qcn_gp3_barral_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_mac_afifo_tnl_int[] = {
{ .int_msk = BIT(0), .msg = "egu_cge_afifo_ecc_1bit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(1), .msg = "egu_cge_afifo_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "egu_lge_afifo_ecc_1bit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(3), .msg = "egu_lge_afifo_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(4), .msg = "cge_igu_afifo_ecc_1bit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(5), .msg = "cge_igu_afifo_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(6), .msg = "lge_igu_afifo_ecc_1bit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(7), .msg = "lge_igu_afifo_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(8), .msg = "cge_igu_afifo_overflow_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(9), .msg = "lge_igu_afifo_overflow_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(10), .msg = "egu_cge_afifo_underrun_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(11), .msg = "egu_lge_afifo_underrun_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(12), .msg = "egu_ge_afifo_underrun_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(13), .msg = "ge_igu_afifo_overflow_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "egu_cge_afifo_ecc_1bit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(1),
.msg = "egu_cge_afifo_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "egu_lge_afifo_ecc_1bit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(3),
.msg = "egu_lge_afifo_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(4),
.msg = "cge_igu_afifo_ecc_1bit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(5),
.msg = "cge_igu_afifo_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(6),
.msg = "lge_igu_afifo_ecc_1bit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(7),
.msg = "lge_igu_afifo_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(8),
.msg = "cge_igu_afifo_overflow_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(9),
.msg = "lge_igu_afifo_overflow_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(10),
.msg = "egu_cge_afifo_underrun_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(11),
.msg = "egu_lge_afifo_underrun_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(12),
.msg = "egu_ge_afifo_underrun_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(13),
.msg = "ge_igu_afifo_overflow_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st2[] = {
{ .int_msk = BIT(13), .msg = "rpu_rx_pkt_bit32_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(14), .msg = "rpu_rx_pkt_bit33_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(15), .msg = "rpu_rx_pkt_bit34_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(16), .msg = "rpu_rx_pkt_bit35_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(17), .msg = "rcb_tx_ring_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(18), .msg = "rcb_rx_ring_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(19), .msg = "rcb_tx_fbd_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(20), .msg = "rcb_rx_ebd_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(21), .msg = "rcb_tso_info_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(22), .msg = "rcb_tx_int_info_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(23), .msg = "rcb_rx_int_info_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(24), .msg = "tpu_tx_pkt_0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(25), .msg = "tpu_tx_pkt_1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(26), .msg = "rd_bus_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(27), .msg = "wr_bus_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(28), .msg = "reg_search_miss",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(29), .msg = "rx_q_search_miss",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(30), .msg = "ooo_ecc_err_detect",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(31), .msg = "ooo_ecc_err_multpl",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(13),
.msg = "rpu_rx_pkt_bit32_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(14),
.msg = "rpu_rx_pkt_bit33_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(15),
.msg = "rpu_rx_pkt_bit34_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(16),
.msg = "rpu_rx_pkt_bit35_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(17),
.msg = "rcb_tx_ring_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(18),
.msg = "rcb_rx_ring_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(19),
.msg = "rcb_tx_fbd_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(20),
.msg = "rcb_rx_ebd_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(21),
.msg = "rcb_tso_info_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(22),
.msg = "rcb_tx_int_info_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(23),
.msg = "rcb_rx_int_info_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(24),
.msg = "tpu_tx_pkt_0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(25),
.msg = "tpu_tx_pkt_1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(26),
.msg = "rd_bus_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(27),
.msg = "wr_bus_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(28),
.msg = "reg_search_miss",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(29),
.msg = "rx_q_search_miss",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(30),
.msg = "ooo_ecc_err_detect",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(31),
.msg = "ooo_ecc_err_multpl",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st3[] = {
{ .int_msk = BIT(4), .msg = "gro_bd_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "gro_context_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(6), .msg = "rx_stash_cfg_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(7), .msg = "axi_rd_fbd_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(4),
.msg = "gro_bd_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "gro_context_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(6),
.msg = "rx_stash_cfg_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(7),
.msg = "axi_rd_fbd_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ppu_pf_abnormal_int[] = {
{ .int_msk = BIT(0), .msg = "over_8bd_no_fe",
.reset_level = HNAE3_FUNC_RESET },
{ .int_msk = BIT(1), .msg = "tso_mss_cmp_min_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(2), .msg = "tso_mss_cmp_max_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(3), .msg = "tx_rd_fbd_poison",
.reset_level = HNAE3_FUNC_RESET },
{ .int_msk = BIT(4), .msg = "rx_rd_ebd_poison",
.reset_level = HNAE3_FUNC_RESET },
{ .int_msk = BIT(5), .msg = "buf_wait_timeout",
.reset_level = HNAE3_NONE_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "over_8bd_no_fe",
.reset_level = HNAE3_FUNC_RESET
}, {
.int_msk = BIT(1),
.msg = "tso_mss_cmp_min_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(2),
.msg = "tso_mss_cmp_max_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(3),
.msg = "tx_rd_fbd_poison",
.reset_level = HNAE3_FUNC_RESET
}, {
.int_msk = BIT(4),
.msg = "rx_rd_ebd_poison",
.reset_level = HNAE3_FUNC_RESET
}, {
.int_msk = BIT(5),
.msg = "buf_wait_timeout",
.reset_level = HNAE3_NONE_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ssu_com_err_int[] = {
{ .int_msk = BIT(0), .msg = "buf_sum_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(1), .msg = "ppp_mb_num_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(2), .msg = "ppp_mbid_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "ppp_rlt_mac_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(4), .msg = "ppp_rlt_host_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "cks_edit_position_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(6), .msg = "cks_edit_condition_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(7), .msg = "vlan_edit_condition_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(8), .msg = "vlan_num_ot_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(9), .msg = "vlan_num_in_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "buf_sum_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(1),
.msg = "ppp_mb_num_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(2),
.msg = "ppp_mbid_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "ppp_rlt_mac_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(4),
.msg = "ppp_rlt_host_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "cks_edit_position_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(6),
.msg = "cks_edit_condition_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(7),
.msg = "vlan_edit_condition_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(8),
.msg = "vlan_num_ot_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(9),
.msg = "vlan_num_in_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
#define HCLGE_SSU_MEM_ECC_ERR(x) \
{ .int_msk = BIT(x), .msg = "ssu_mem" #x "_ecc_mbit_err", \
.reset_level = HNAE3_GLOBAL_RESET }
{ \
.int_msk = BIT(x), \
.msg = "ssu_mem" #x "_ecc_mbit_err", \
.reset_level = HNAE3_GLOBAL_RESET \
}
static const struct hclge_hw_error hclge_ssu_mem_ecc_err_int[] = {
HCLGE_SSU_MEM_ECC_ERR(0),
......@@ -504,131 +931,269 @@ static const struct hclge_hw_error hclge_ssu_mem_ecc_err_int[] = {
};
static const struct hclge_hw_error hclge_ssu_port_based_err_int[] = {
{ .int_msk = BIT(0), .msg = "roc_pkt_without_key_port",
.reset_level = HNAE3_FUNC_RESET },
{ .int_msk = BIT(1), .msg = "tpu_pkt_without_key_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "igu_pkt_without_key_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "roc_eof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(4), .msg = "tpu_eof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "igu_eof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(6), .msg = "roc_sof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(7), .msg = "tpu_sof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(8), .msg = "igu_sof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(11), .msg = "ets_rd_int_rx_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(12), .msg = "ets_wr_int_rx_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(13), .msg = "ets_rd_int_tx_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(14), .msg = "ets_wr_int_tx_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "roc_pkt_without_key_port",
.reset_level = HNAE3_FUNC_RESET
}, {
.int_msk = BIT(1),
.msg = "tpu_pkt_without_key_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "igu_pkt_without_key_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "roc_eof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(4),
.msg = "tpu_eof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "igu_eof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(6),
.msg = "roc_sof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(7),
.msg = "tpu_sof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(8),
.msg = "igu_sof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(11),
.msg = "ets_rd_int_rx_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(12),
.msg = "ets_wr_int_rx_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(13),
.msg = "ets_rd_int_tx_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(14),
.msg = "ets_wr_int_tx_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ssu_fifo_overflow_int[] = {
{ .int_msk = BIT(0), .msg = "ig_mac_inf_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(1), .msg = "ig_host_inf_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "ig_roc_buf_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "ig_host_data_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(4), .msg = "ig_host_key_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "tx_qcn_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(6), .msg = "rx_qcn_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(7), .msg = "tx_pf_rd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(8), .msg = "rx_pf_rd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(9), .msg = "qm_eof_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(10), .msg = "mb_rlt_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(11), .msg = "dup_uncopy_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(12), .msg = "dup_cnt_rd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(13), .msg = "dup_cnt_drop_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(14), .msg = "dup_cnt_wrb_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(15), .msg = "host_cmd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(16), .msg = "mac_cmd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(17), .msg = "host_cmd_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(18), .msg = "mac_cmd_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(19), .msg = "dup_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(20), .msg = "out_queue_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(21), .msg = "bank2_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(22), .msg = "bank1_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(23), .msg = "bank0_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "ig_mac_inf_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(1),
.msg = "ig_host_inf_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "ig_roc_buf_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "ig_host_data_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(4),
.msg = "ig_host_key_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "tx_qcn_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(6),
.msg = "rx_qcn_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(7),
.msg = "tx_pf_rd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(8),
.msg = "rx_pf_rd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(9),
.msg = "qm_eof_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(10),
.msg = "mb_rlt_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(11),
.msg = "dup_uncopy_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(12),
.msg = "dup_cnt_rd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(13),
.msg = "dup_cnt_drop_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(14),
.msg = "dup_cnt_wrb_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(15),
.msg = "host_cmd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(16),
.msg = "mac_cmd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(17),
.msg = "host_cmd_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(18),
.msg = "mac_cmd_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(19),
.msg = "dup_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(20),
.msg = "out_queue_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(21),
.msg = "bank2_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(22),
.msg = "bank1_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(23),
.msg = "bank0_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ssu_ets_tcg_int[] = {
{ .int_msk = BIT(0), .msg = "ets_rd_int_rx_tcg",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(1), .msg = "ets_wr_int_rx_tcg",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "ets_rd_int_tx_tcg",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "ets_wr_int_tx_tcg",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "ets_rd_int_rx_tcg",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(1),
.msg = "ets_wr_int_rx_tcg",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "ets_rd_int_tx_tcg",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "ets_wr_int_tx_tcg",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ssu_port_based_pf_int[] = {
{ .int_msk = BIT(0), .msg = "roc_pkt_without_key_port",
.reset_level = HNAE3_FUNC_RESET },
{ .int_msk = BIT(9), .msg = "low_water_line_err_port",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(10), .msg = "hi_water_line_err_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "roc_pkt_without_key_port",
.reset_level = HNAE3_FUNC_RESET
}, {
.int_msk = BIT(9),
.msg = "low_water_line_err_port",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(10),
.msg = "hi_water_line_err_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_rocee_qmm_ovf_err_int[] = {
{ .int_msk = 0, .msg = "rocee qmm ovf: sgid invalid err" },
{ .int_msk = 0x4, .msg = "rocee qmm ovf: sgid ovf err" },
{ .int_msk = 0x8, .msg = "rocee qmm ovf: smac invalid err" },
{ .int_msk = 0xC, .msg = "rocee qmm ovf: smac ovf err" },
{ .int_msk = 0x10, .msg = "rocee qmm ovf: cqc invalid err" },
{ .int_msk = 0x11, .msg = "rocee qmm ovf: cqc ovf err" },
{ .int_msk = 0x12, .msg = "rocee qmm ovf: cqc hopnum err" },
{ .int_msk = 0x13, .msg = "rocee qmm ovf: cqc ba0 err" },
{ .int_msk = 0x14, .msg = "rocee qmm ovf: srqc invalid err" },
{ .int_msk = 0x15, .msg = "rocee qmm ovf: srqc ovf err" },
{ .int_msk = 0x16, .msg = "rocee qmm ovf: srqc hopnum err" },
{ .int_msk = 0x17, .msg = "rocee qmm ovf: srqc ba0 err" },
{ .int_msk = 0x18, .msg = "rocee qmm ovf: mpt invalid err" },
{ .int_msk = 0x19, .msg = "rocee qmm ovf: mpt ovf err" },
{ .int_msk = 0x1A, .msg = "rocee qmm ovf: mpt hopnum err" },
{ .int_msk = 0x1B, .msg = "rocee qmm ovf: mpt ba0 err" },
{ .int_msk = 0x1C, .msg = "rocee qmm ovf: qpc invalid err" },
{ .int_msk = 0x1D, .msg = "rocee qmm ovf: qpc ovf err" },
{ .int_msk = 0x1E, .msg = "rocee qmm ovf: qpc hopnum err" },
{ .int_msk = 0x1F, .msg = "rocee qmm ovf: qpc ba0 err" },
{ /* sentinel */ }
{
.int_msk = 0,
.msg = "rocee qmm ovf: sgid invalid err"
}, {
.int_msk = 0x4,
.msg = "rocee qmm ovf: sgid ovf err"
}, {
.int_msk = 0x8,
.msg = "rocee qmm ovf: smac invalid err"
}, {
.int_msk = 0xC,
.msg = "rocee qmm ovf: smac ovf err"
}, {
.int_msk = 0x10,
.msg = "rocee qmm ovf: cqc invalid err"
}, {
.int_msk = 0x11,
.msg = "rocee qmm ovf: cqc ovf err"
}, {
.int_msk = 0x12,
.msg = "rocee qmm ovf: cqc hopnum err"
}, {
.int_msk = 0x13,
.msg = "rocee qmm ovf: cqc ba0 err"
}, {
.int_msk = 0x14,
.msg = "rocee qmm ovf: srqc invalid err"
}, {
.int_msk = 0x15,
.msg = "rocee qmm ovf: srqc ovf err"
}, {
.int_msk = 0x16,
.msg = "rocee qmm ovf: srqc hopnum err"
}, {
.int_msk = 0x17,
.msg = "rocee qmm ovf: srqc ba0 err"
}, {
.int_msk = 0x18,
.msg = "rocee qmm ovf: mpt invalid err"
}, {
.int_msk = 0x19,
.msg = "rocee qmm ovf: mpt ovf err"
}, {
.int_msk = 0x1A,
.msg = "rocee qmm ovf: mpt hopnum err"
}, {
.int_msk = 0x1B,
.msg = "rocee qmm ovf: mpt ba0 err"
}, {
.int_msk = 0x1C,
.msg = "rocee qmm ovf: qpc invalid err"
}, {
.int_msk = 0x1D,
.msg = "rocee qmm ovf: qpc ovf err"
}, {
.int_msk = 0x1E,
.msg = "rocee qmm ovf: qpc hopnum err"
}, {
.int_msk = 0x1F,
.msg = "rocee qmm ovf: qpc ba0 err"
}, {
/* sentinel */
}
};
static const struct hclge_hw_module_id hclge_hw_module_id_st[] = {
......@@ -1709,34 +2274,36 @@ static void hclge_handle_rocee_ras_error(struct hnae3_ae_dev *ae_dev)
static const struct hclge_hw_blk hw_blk[] = {
{
.msk = BIT(0), .name = "IGU_EGU",
.msk = BIT(0),
.name = "IGU_EGU",
.config_err_int = hclge_config_igu_egu_hw_err_int,
},
{
.msk = BIT(1), .name = "PPP",
}, {
.msk = BIT(1),
.name = "PPP",
.config_err_int = hclge_config_ppp_hw_err_int,
},
{
.msk = BIT(2), .name = "SSU",
}, {
.msk = BIT(2),
.name = "SSU",
.config_err_int = hclge_config_ssu_hw_err_int,
},
{
.msk = BIT(3), .name = "PPU",
}, {
.msk = BIT(3),
.name = "PPU",
.config_err_int = hclge_config_ppu_hw_err_int,
},
{
.msk = BIT(4), .name = "TM",
}, {
.msk = BIT(4),
.name = "TM",
.config_err_int = hclge_config_tm_hw_err_int,
},
{
.msk = BIT(5), .name = "COMMON",
}, {
.msk = BIT(5),
.name = "COMMON",
.config_err_int = hclge_config_common_hw_err_int,
},
{
.msk = BIT(8), .name = "MAC",
}, {
.msk = BIT(8),
.name = "MAC",
.config_err_int = hclge_config_mac_err_int,
},
{ /* sentinel */ }
}, {
/* sentinel */
}
};
static void hclge_config_all_msix_error(struct hclge_dev *hdev, bool enable)
......
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