Commit 61417aaa authored by Thierry Reding's avatar Thierry Reding

drm/tegra: sor: Unify clock setup for eDP, HDMI and DP

With the clocks modelled consistently across SoC generations, the clock
setup for eDP, HDMI and DP can now be unified.
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent bae88815
...@@ -527,6 +527,14 @@ static const char * const tegra_clk_sor_pad_parents[2][2] = { ...@@ -527,6 +527,14 @@ static const char * const tegra_clk_sor_pad_parents[2][2] = {
{ "pll_d2_out0", "pll_dp" }, { "pll_d2_out0", "pll_dp" },
}; };
/*
* Implementing ->set_parent() here isn't really required because the parent
* will be explicitly selected in the driver code via the DP_CLK_SEL mux in
* the SOR_CLK_CNTRL register. This is primarily for compatibility with the
* Tegra186 and later SoC generations where the BPMP implements this clock
* and doesn't expose the mux via the common clock framework.
*/
static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index) static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
{ {
struct tegra_clk_sor_pad *pad = to_pad(hw); struct tegra_clk_sor_pad *pad = to_pad(hw);
...@@ -1987,10 +1995,36 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) ...@@ -1987,10 +1995,36 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
tegra_sor_writel(sor, value, SOR_XBAR_CTRL); tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
/* switch to DP parent clock */ /*
err = tegra_sor_set_parent_clock(sor, sor->clk_dp); * Switch the pad clock to the DP clock. Note that we cannot actually
if (err < 0) * do this because Tegra186 and later don't support clk_set_parent()
dev_err(sor->dev, "failed to set parent clock: %d\n", err); * on the sorX_pad_clkout clocks. We already do the equivalent above
* using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
*/
#if 0
err = clk_set_parent(sor->clk_pad, sor->clk_dp);
if (err < 0) {
dev_err(sor->dev, "failed to select pad parent clock: %d\n",
err);
return;
}
#endif
/* switch the SOR clock to the pad clock */
err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
if (err < 0) {
dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
err);
return;
}
/* switch the output clock to the parent pixel clock */
err = clk_set_parent(sor->clk, sor->clk_parent);
if (err < 0) {
dev_err(sor->dev, "failed to select output parent clock: %d\n",
err);
return;
}
/* use DP-A protocol */ /* use DP-A protocol */
value = tegra_sor_readl(sor, SOR_STATE1); value = tegra_sor_readl(sor, SOR_STATE1);
...@@ -2661,16 +2695,34 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) ...@@ -2661,16 +2695,34 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
tegra_sor_writel(sor, value, SOR_XBAR_CTRL); tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
/* switch to parent clock */ /*
err = clk_set_parent(sor->clk, sor->clk_parent); * Switch the pad clock to the DP clock. Note that we cannot actually
* do this because Tegra186 and later don't support clk_set_parent()
* on the sorX_pad_clkout clocks. We already do the equivalent above
* using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
*/
#if 0
err = clk_set_parent(sor->clk_pad, sor->clk_dp);
if (err < 0) { if (err < 0) {
dev_err(sor->dev, "failed to set parent clock: %d\n", err); dev_err(sor->dev, "failed to select pad parent clock: %d\n",
err);
return; return;
} }
#endif
/* switch the SOR clock to the pad clock */
err = tegra_sor_set_parent_clock(sor, sor->clk_pad); err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
if (err < 0) { if (err < 0) {
dev_err(sor->dev, "failed to set pad clock: %d\n", err); dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
err);
return;
}
/* switch the output clock to the parent pixel clock */
err = clk_set_parent(sor->clk, sor->clk_parent);
if (err < 0) {
dev_err(sor->dev, "failed to select output parent clock: %d\n",
err);
return; return;
} }
...@@ -3061,16 +3113,34 @@ static void tegra_sor_dp_enable(struct drm_encoder *encoder) ...@@ -3061,16 +3113,34 @@ static void tegra_sor_dp_enable(struct drm_encoder *encoder)
tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
tegra_sor_writel(sor, value, SOR_XBAR_CTRL); tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
/* switch to DP parent clock */ /*
* Switch the pad clock to the DP clock. Note that we cannot actually
* do this because Tegra186 and later don't support clk_set_parent()
* on the sorX_pad_clkout clocks. We already do the equivalent above
* using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
*/
#if 0
err = clk_set_parent(sor->clk_pad, sor->clk_parent);
if (err < 0) {
dev_err(sor->dev, "failed to select pad parent clock: %d\n",
err);
return;
}
#endif
/* switch the SOR clock to the pad clock */
err = tegra_sor_set_parent_clock(sor, sor->clk_pad); err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
if (err < 0) { if (err < 0) {
dev_err(sor->dev, "failed to switch to pad clock: %d\n", err); dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
err);
return; return;
} }
/* switch the output clock to the parent pixel clock */
err = clk_set_parent(sor->clk, sor->clk_parent); err = clk_set_parent(sor->clk, sor->clk_parent);
if (err < 0) { if (err < 0) {
dev_err(sor->dev, "failed to switch to parent clock: %d\n", err); dev_err(sor->dev, "failed to select output parent clock: %d\n",
err);
return; return;
} }
......
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