Commit 626ad0e2 authored by Russell King's avatar Russell King

Merge flint.arm.linux.org.uk:/usr/src/linux-bk-2.5/linux-2.5

into flint.arm.linux.org.uk:/usr/src/linux-bk-2.5/linux-2.5-rmk
parents 702d27c7 3b32b128
...@@ -396,6 +396,12 @@ proc_types: ...@@ -396,6 +396,12 @@ proc_types:
b __armv4_cache_off b __armv4_cache_off
mov pc, lr mov pc, lr
.word 0x41129200 @ ARM920T
.word 0xff00fff0
b __cache_on
b __armv4_cache_off
b __armv4_cache_flush
.word 0x4401a100 @ sa110 / sa1100 .word 0x4401a100 @ sa110 / sa1100
.word 0xffffffe0 .word 0xffffffe0
b __cache_on b __cache_on
......
...@@ -33,10 +33,10 @@ ...@@ -33,10 +33,10 @@
/* /*
* Logical Physical * Logical Physical
* e8000000 40000000 PCI memory * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
* ec000000 62000000 PCI config space * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
* ed000000 61000000 PCI V3 regs * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
* ee000000 60000000 PCI IO * ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
* ef000000 Cache flush * ef000000 Cache flush
* f1000000 10000000 Core module registers * f1000000 10000000 Core module registers
* f1100000 11000000 System controller registers * f1100000 11000000 System controller registers
...@@ -67,7 +67,7 @@ static struct map_desc integrator_io_desc[] __initdata = { ...@@ -67,7 +67,7 @@ static struct map_desc integrator_io_desc[] __initdata = {
{ IO_ADDRESS(INTEGRATOR_GPIO_BASE), INTEGRATOR_GPIO_BASE, SZ_4K , DOMAIN_IO, 0, 1}, { IO_ADDRESS(INTEGRATOR_GPIO_BASE), INTEGRATOR_GPIO_BASE, SZ_4K , DOMAIN_IO, 0, 1},
{ PCI_MEMORY_VADDR, PHYS_PCI_MEM_BASE, SZ_16M , DOMAIN_IO, 0, 1}, { PCI_MEMORY_VADDR, PHYS_PCI_MEM_BASE, SZ_16M , DOMAIN_IO, 0, 1},
{ PCI_CONFIG_VADDR, PHYS_PCI_CONFIG_BASE, SZ_16M , DOMAIN_IO, 0, 1}, { PCI_CONFIG_VADDR, PHYS_PCI_CONFIG_BASE, SZ_16M , DOMAIN_IO, 0, 1},
{ PCI_V3_VADDR, PHYS_PCI_V3_BASE, SZ_512K , DOMAIN_IO, 0, 1}, { PCI_V3_VADDR, PHYS_PCI_V3_BASE, SZ_64K , DOMAIN_IO, 0, 1},
{ PCI_IO_VADDR, PHYS_PCI_IO_BASE, SZ_64K , DOMAIN_IO, 0, 1}, { PCI_IO_VADDR, PHYS_PCI_IO_BASE, SZ_64K , DOMAIN_IO, 0, 1},
LAST_DESC LAST_DESC
}; };
......
...@@ -50,7 +50,7 @@ ...@@ -50,7 +50,7 @@
* 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
* 50000000 - 5FFFFFFF PCI memory. 256M prefetchable * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
* 60000000 - 60FFFFFF PCI IO. 16M * 60000000 - 60FFFFFF PCI IO. 16M
* 68000000 - 68FFFFFF PCI Configuration. 16M * 61000000 - 61FFFFFF PCI Configuration. 16M
* *
* There are three V3 windows, each described by a pair of V3 registers. * There are three V3 windows, each described by a pair of V3 registers.
* These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2. * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
...@@ -58,14 +58,6 @@ ...@@ -58,14 +58,6 @@
* can be used either for PCI I/O or for I20 accesses. By default, uHAL * can be used either for PCI I/O or for I20 accesses. By default, uHAL
* uses this only for PCI IO space. * uses this only for PCI IO space.
* *
* PCI Memory is mapped so that assigned addresses in PCI Memory match
* local bus memory addresses. In other words, if a PCI device is assigned
* address 80200000 then that address is a valid local bus address as well
* as a valid PCI Memory address. PCI IO addresses are mapped to start
* at zero. This means that local bus address 60000000 maps to PCI IO address
* 00000000 and so on. Device driver writers need to be aware of this
* distinction.
*
* Normally these spaces are mapped using the following base registers: * Normally these spaces are mapped using the following base registers:
* *
* Usage Local Bus Memory Base/Map registers used * Usage Local Bus Memory Base/Map registers used
...@@ -73,7 +65,7 @@ ...@@ -73,7 +65,7 @@
* Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
* Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1
* IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
* Cfg 68000000 - 68FFFFFF * Cfg 61000000 - 61FFFFFF
* *
* This means that I20 and PCI configuration space accesses will fail. * This means that I20 and PCI configuration space accesses will fail.
* When PCI configuration accesses are needed (via the uHAL PCI * When PCI configuration accesses are needed (via the uHAL PCI
...@@ -84,7 +76,7 @@ ...@@ -84,7 +76,7 @@
* Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
* Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0
* IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
* Cfg 68000000 - 68FFFFFF LB_BASE1/LB_MAP1 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1
* *
* To make this work, the code depends on overlapping windows working. * To make this work, the code depends on overlapping windows working.
* The V3 chip translates an address by checking its range within * The V3 chip translates an address by checking its range within
...@@ -174,10 +166,10 @@ ...@@ -174,10 +166,10 @@
static spinlock_t v3_lock = SPIN_LOCK_UNLOCKED; static spinlock_t v3_lock = SPIN_LOCK_UNLOCKED;
#define PCI_BUS_NONMEM_START 0x00000000 #define PCI_BUS_NONMEM_START 0x00000000
#define PCI_BUS_NONMEM_SIZE 0x10000000 #define PCI_BUS_NONMEM_SIZE SZ_256M
#define PCI_BUS_PREMEM_START 0x10000000 #define PCI_BUS_PREMEM_START PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE
#define PCI_BUS_PREMEM_SIZE 0x10000000 #define PCI_BUS_PREMEM_SIZE SZ_256M
#if PCI_BUS_NONMEM_START & 0x000fffff #if PCI_BUS_NONMEM_START & 0x000fffff
#error PCI_BUS_NONMEM_START must be megabyte aligned #error PCI_BUS_NONMEM_START must be megabyte aligned
...@@ -400,15 +392,15 @@ static struct pci_ops pci_v3_ops = { ...@@ -400,15 +392,15 @@ static struct pci_ops pci_v3_ops = {
static struct resource non_mem = { static struct resource non_mem = {
name: "PCI non-prefetchable", name: "PCI non-prefetchable",
start: 0x40000000 + PCI_BUS_NONMEM_START, start: PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START,
end: 0x40000000 + PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE - 1, end: PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE - 1,
flags: IORESOURCE_MEM, flags: IORESOURCE_MEM,
}; };
static struct resource pre_mem = { static struct resource pre_mem = {
name: "PCI prefetchable", name: "PCI prefetchable",
start: 0x40000000 + PCI_BUS_PREMEM_START, start: PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START,
end: 0x40000000 + PCI_BUS_PREMEM_START + PCI_BUS_PREMEM_SIZE - 1, end: PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START + PCI_BUS_PREMEM_SIZE - 1,
flags: IORESOURCE_MEM | IORESOURCE_PREFETCH, flags: IORESOURCE_MEM | IORESOURCE_PREFETCH,
}; };
...@@ -433,7 +425,7 @@ static int __init pci_v3_setup_resources(struct resource **resource) ...@@ -433,7 +425,7 @@ static int __init pci_v3_setup_resources(struct resource **resource)
*/ */
resource[0] = &ioport_resource; resource[0] = &ioport_resource;
resource[1] = &non_mem; resource[1] = &non_mem;
resource[2] = &pre_mem; // resource[2] = &pre_mem;
return 1; return 1;
} }
...@@ -530,7 +522,7 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys) ...@@ -530,7 +522,7 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
int ret = 0; int ret = 0;
if (nr == 0) { if (nr == 0) {
sys->mem_offset = 0x40000000; sys->mem_offset = PHYS_PCI_MEM_BASE;
ret = pci_v3_setup_resources(sys->resource); ret = pci_v3_setup_resources(sys->resource);
} }
......
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