Commit 62b6e9ff authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] Export except_vec_vi_{mori,lui,ori} as text symbols.
  [MIPS] mips-boards: More liberal check for mips-board console
  [MIPS] Misc fixes for plat_irq_dispatch functions
  [MIPS] Qemu: Fix Symmetric Uniprocessor support.
  [MIPS] VI: TRACE_IRQS_OFF clobbers $v0, so save & restore around call.
parents 8718d75e 7df42461
...@@ -542,6 +542,8 @@ config QEMU ...@@ -542,6 +542,8 @@ config QEMU
select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN
select ARCH_SPARSEMEM_ENABLE select ARCH_SPARSEMEM_ENABLE
select GENERIC_HARDIRQS_NO__DO_IRQ select GENERIC_HARDIRQS_NO__DO_IRQ
select NR_CPUS_DEFAULT_1
select SYS_SUPPORTS_SMP
help help
Qemu is a software emulator which among other architectures also Qemu is a software emulator which among other architectures also
can simulate a MIPS32 4Kc system. This patch adds support for the can simulate a MIPS32 4Kc system. This patch adds support for the
...@@ -1805,6 +1807,9 @@ config SMP ...@@ -1805,6 +1807,9 @@ config SMP
config SYS_SUPPORTS_SMP config SYS_SUPPORTS_SMP
bool bool
config NR_CPUS_DEFAULT_1
bool
config NR_CPUS_DEFAULT_2 config NR_CPUS_DEFAULT_2
bool bool
...@@ -1825,8 +1830,9 @@ config NR_CPUS_DEFAULT_64 ...@@ -1825,8 +1830,9 @@ config NR_CPUS_DEFAULT_64
config NR_CPUS config NR_CPUS
int "Maximum number of CPUs (2-64)" int "Maximum number of CPUs (2-64)"
range 2 64 range 1 64 if NR_CPUS_DEFAULT_1
depends on SMP depends on SMP
default "1" if NR_CPUS_DEFAULT_1
default "2" if NR_CPUS_DEFAULT_2 default "2" if NR_CPUS_DEFAULT_2
default "4" if NR_CPUS_DEFAULT_4 default "4" if NR_CPUS_DEFAULT_4
default "8" if NR_CPUS_DEFAULT_8 default "8" if NR_CPUS_DEFAULT_8
...@@ -1837,10 +1843,13 @@ config NR_CPUS ...@@ -1837,10 +1843,13 @@ config NR_CPUS
This allows you to specify the maximum number of CPUs which this This allows you to specify the maximum number of CPUs which this
kernel will support. The maximum supported value is 32 for 32-bit kernel will support. The maximum supported value is 32 for 32-bit
kernel and 64 for 64-bit kernels; the minimum value which makes kernel and 64 for 64-bit kernels; the minimum value which makes
sense is 2. sense is 1 for Qemu (useful only for kernel debugging purposes)
and 2 for all others.
This is purely to save memory - each supported CPU adds This is purely to save memory - each supported CPU adds
approximately eight kilobytes to the kernel image. approximately eight kilobytes to the kernel image. For best
performance should round up your number of processors to the next
power of two.
# #
# Timer Interrupt Frequency Configuration # Timer Interrupt Frequency Configuration
......
...@@ -194,7 +194,7 @@ static void vrc5477_irq_dispatch(void) ...@@ -194,7 +194,7 @@ static void vrc5477_irq_dispatch(void)
asmlinkage void plat_irq_dispatch(void) asmlinkage void plat_irq_dispatch(void)
{ {
unsigned int pending = read_c0_cause() & read_c0_status(); unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
if (pending & STATUSF_IP7) if (pending & STATUSF_IP7)
do_IRQ(CPU_IRQ_BASE + 7); do_IRQ(CPU_IRQ_BASE + 7);
......
...@@ -115,7 +115,7 @@ void __init arch_init_irq(void) ...@@ -115,7 +115,7 @@ void __init arch_init_irq(void)
asmlinkage void plat_irq_dispatch(void) asmlinkage void plat_irq_dispatch(void)
{ {
unsigned int pending = read_c0_status() & read_c0_cause(); unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP7) if (pending & STATUSF_IP7)
do_IRQ(CPU_IRQ_BASE + 7); do_IRQ(CPU_IRQ_BASE + 7);
......
...@@ -48,7 +48,7 @@ ...@@ -48,7 +48,7 @@
asmlinkage void plat_irq_dispatch(void) asmlinkage void plat_irq_dispatch(void)
{ {
unsigned int pending = read_c0_status() & read_c0_cause(); unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP4) /* int2 hardware line (timer) */ if (pending & STATUSF_IP4) /* int2 hardware line (timer) */
do_IRQ(4); do_IRQ(4);
......
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
asmlinkage void plat_irq_dispatch(void) asmlinkage void plat_irq_dispatch(void)
{ {
unsigned int pending = read_c0_status() & read_c0_cause(); unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP7) if (pending & STATUSF_IP7)
do_IRQ(WRPPMC_MIPS_TIMER_IRQ); /* CPU Compare/Count internal timer */ do_IRQ(WRPPMC_MIPS_TIMER_IRQ); /* CPU Compare/Count internal timer */
......
...@@ -122,7 +122,7 @@ static void ll_local_dev(void) ...@@ -122,7 +122,7 @@ static void ll_local_dev(void)
asmlinkage void plat_irq_dispatch(void) asmlinkage void plat_irq_dispatch(void)
{ {
unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; unsigned int pending = read_c0_cause() & read_c0_status();
if (pending & IE_IRQ5) if (pending & IE_IRQ5)
write_c0_compare(0); write_c0_compare(0);
......
...@@ -181,13 +181,13 @@ NESTED(except_vec_vi, 0, sp) ...@@ -181,13 +181,13 @@ NESTED(except_vec_vi, 0, sp)
* during service by SMTC kernel, we also want to * during service by SMTC kernel, we also want to
* pass the IM value to be cleared. * pass the IM value to be cleared.
*/ */
EXPORT(except_vec_vi_mori) FEXPORT(except_vec_vi_mori)
ori a0, $0, 0 ori a0, $0, 0
#endif /* CONFIG_MIPS_MT_SMTC */ #endif /* CONFIG_MIPS_MT_SMTC */
EXPORT(except_vec_vi_lui) FEXPORT(except_vec_vi_lui)
lui v0, 0 /* Patched */ lui v0, 0 /* Patched */
j except_vec_vi_handler j except_vec_vi_handler
EXPORT(except_vec_vi_ori) FEXPORT(except_vec_vi_ori)
ori v0, 0 /* Patched */ ori v0, 0 /* Patched */
.set pop .set pop
END(except_vec_vi) END(except_vec_vi)
...@@ -220,7 +220,17 @@ NESTED(except_vec_vi_handler, 0, sp) ...@@ -220,7 +220,17 @@ NESTED(except_vec_vi_handler, 0, sp)
_ehb _ehb
#endif /* CONFIG_MIPS_MT_SMTC */ #endif /* CONFIG_MIPS_MT_SMTC */
CLI CLI
#ifdef CONFIG_TRACE_IRQFLAGS
move s0, v0
#ifdef CONFIG_MIPS_MT_SMTC
move s1, a0
#endif
TRACE_IRQS_OFF TRACE_IRQS_OFF
#ifdef CONFIG_MIPS_MT_SMTC
move a0, s1
#endif
move v0, s0
#endif
LONG_L s0, TI_REGS($28) LONG_L s0, TI_REGS($28)
LONG_S sp, TI_REGS($28) LONG_S sp, TI_REGS($28)
......
...@@ -145,7 +145,7 @@ static void __init console_config(void) ...@@ -145,7 +145,7 @@ static void __init console_config(void)
char parity = '\0', bits = '\0', flow = '\0'; char parity = '\0', bits = '\0', flow = '\0';
char *s; char *s;
if ((strstr(prom_getcmdline(), "console=ttyS")) == NULL) { if ((strstr(prom_getcmdline(), "console=")) == NULL) {
s = prom_getenv("modetty0"); s = prom_getenv("modetty0");
if (s) { if (s) {
while (*s >= '0' && *s <= '9') while (*s >= '0' && *s <= '9')
......
...@@ -64,7 +64,7 @@ extern void ll_cpci_irq(void); ...@@ -64,7 +64,7 @@ extern void ll_cpci_irq(void);
asmlinkage void plat_irq_dispatch(void) asmlinkage void plat_irq_dispatch(void)
{ {
unsigned int pending = read_c0_cause() & read_c0_status(); unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
if (pending & STATUSF_IP0) if (pending & STATUSF_IP0)
do_IRQ(0); do_IRQ(0);
......
...@@ -83,15 +83,14 @@ static void timer_irqdispatch(int irq) ...@@ -83,15 +83,14 @@ static void timer_irqdispatch(int irq)
asmlinkage void plat_irq_dispatch(void) asmlinkage void plat_irq_dispatch(void)
{ {
unsigned int pending = read_c0_status() & read_c0_cause(); unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP2) if (pending & STATUSF_IP2)
hw0_irqdispatch(2); hw0_irqdispatch(2);
else if (pending & STATUSF_IP7) { else if (pending & STATUSF_IP7) {
if (read_c0_config7() & 0x01c0) if (read_c0_config7() & 0x01c0)
timer_irqdispatch(7); timer_irqdispatch(7);
} } else
spurious_interrupt(); spurious_interrupt();
} }
......
...@@ -46,3 +46,10 @@ void __init prom_prepare_cpus(unsigned int max_cpus) ...@@ -46,3 +46,10 @@ void __init prom_prepare_cpus(unsigned int max_cpus)
void prom_boot_secondary(int cpu, struct task_struct *idle) void prom_boot_secondary(int cpu, struct task_struct *idle)
{ {
} }
void __init plat_smp_setup(void)
{
}
void __init plat_prepare_cpus(unsigned int max_cpus)
{
}
...@@ -237,7 +237,7 @@ extern void indy_8254timer_irq(void); ...@@ -237,7 +237,7 @@ extern void indy_8254timer_irq(void);
asmlinkage void plat_irq_dispatch(void) asmlinkage void plat_irq_dispatch(void)
{ {
unsigned int pending = read_c0_cause(); unsigned int pending = read_c0_status() & read_c0_cause();
/* /*
* First we check for r4k counter/timer IRQ. * First we check for r4k counter/timer IRQ.
......
...@@ -454,7 +454,7 @@ static void ip32_irq5(void) ...@@ -454,7 +454,7 @@ static void ip32_irq5(void)
asmlinkage void plat_irq_dispatch(void) asmlinkage void plat_irq_dispatch(void)
{ {
unsigned int pending = read_c0_cause(); unsigned int pending = read_c0_status() & read_c0_cause();
if (likely(pending & IE_IRQ0)) if (likely(pending & IE_IRQ0))
ip32_irq0(); ip32_irq0();
......
...@@ -421,7 +421,7 @@ asmlinkage void plat_irq_dispatch(void) ...@@ -421,7 +421,7 @@ asmlinkage void plat_irq_dispatch(void)
* blasting the high 32 bits. * blasting the high 32 bits.
*/ */
pending = read_c0_cause() & read_c0_status(); pending = read_c0_cause() & read_c0_status() & ST0_IM;
#ifdef CONFIG_SIBYTE_SB1250_PROF #ifdef CONFIG_SIBYTE_SB1250_PROF
if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */ if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
......
...@@ -333,7 +333,7 @@ static void pcimt_hwint3(void) ...@@ -333,7 +333,7 @@ static void pcimt_hwint3(void)
static void sni_pcimt_hwint(void) static void sni_pcimt_hwint(void)
{ {
u32 pending = (read_c0_cause() & read_c0_status()); u32 pending = read_c0_cause() & read_c0_status();
if (pending & C_IRQ5) if (pending & C_IRQ5)
do_IRQ (MIPS_CPU_IRQ_BASE + 7); do_IRQ (MIPS_CPU_IRQ_BASE + 7);
......
...@@ -271,7 +271,7 @@ static void pcit_hwint0(void) ...@@ -271,7 +271,7 @@ static void pcit_hwint0(void)
static void sni_pcit_hwint(void) static void sni_pcit_hwint(void)
{ {
u32 pending = (read_c0_cause() & read_c0_status()); u32 pending = read_c0_cause() & read_c0_status();
if (pending & C_IRQ1) if (pending & C_IRQ1)
pcit_hwint1(); pcit_hwint1();
...@@ -285,7 +285,7 @@ static void sni_pcit_hwint(void) ...@@ -285,7 +285,7 @@ static void sni_pcit_hwint(void)
static void sni_pcit_hwint_cplus(void) static void sni_pcit_hwint_cplus(void)
{ {
u32 pending = (read_c0_cause() & read_c0_status()); u32 pending = read_c0_cause() & read_c0_status();
if (pending & C_IRQ0) if (pending & C_IRQ0)
pcit_hwint0(); pcit_hwint0();
......
...@@ -416,7 +416,7 @@ static int tx4927_irq_nested(void) ...@@ -416,7 +416,7 @@ static int tx4927_irq_nested(void)
asmlinkage void plat_irq_dispatch(void) asmlinkage void plat_irq_dispatch(void)
{ {
unsigned int pending = read_c0_status() & read_c0_cause(); unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP7) /* cpu timer */ if (pending & STATUSF_IP7) /* cpu timer */
do_IRQ(TX4927_IRQ_CPU_TIMER); do_IRQ(TX4927_IRQ_CPU_TIMER);
......
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