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Commit 63c7234f authored by Jakub Kicinski's avatar Jakub Kicinski
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Revert "octeon_ep_vf: add octeon_ep_vf driver" 

This reverts commit c902ba32.
This reverts commit 50648968.
This reverts commit 77cef1e0.
This reverts commit 8f8d322b.
This reverts commit 6ca7b548.
This reverts commit db468f92.
This reverts commit 5f8c64c2.
This reverts commit ebdc193b.

The driver needs more work.
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 5e5401d6
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Documentation/networking/device_drivers/ethernet/index.rst
View file @ 63c7234f
......@@ -42,7 +42,6 @@ Contents:
intel/ice
marvell/octeontx2
marvell/octeon_ep
marvell/octeon_ep_vf
mellanox/mlx5/index
microsoft/netvsc
neterion/s2io
......
Documentation/networking/device_drivers/ethernet/marvell/octeon_ep_vf.rst deleted 100644 → 0
View file @ 5e5401d6
.. SPDX-License-Identifier: GPL-2.0+
=======================================================================
Linux kernel networking driver for Marvell's Octeon PCI Endpoint NIC VF
=======================================================================
Network driver for Marvell's Octeon PCI EndPoint NIC VF.
Copyright (c) 2020 Marvell International Ltd.
Overview
========
This driver implements networking functionality of Marvell's Octeon PCI
EndPoint NIC VF.
Supported Devices
=================
Currently, this driver support following devices:
* Network controller: Cavium, Inc. Device b203
* Network controller: Cavium, Inc. Device b403
* Network controller: Cavium, Inc. Device b103
* Network controller: Cavium, Inc. Device b903
* Network controller: Cavium, Inc. Device ba03
* Network controller: Cavium, Inc. Device bc03
* Network controller: Cavium, Inc. Device bd03
MAINTAINERS
View file @ 63c7234f
......@@ -12861,15 +12861,6 @@ L: netdev@vger.kernel.org
S: Supported
F: drivers/net/ethernet/marvell/octeon_ep
MARVELL OCTEON ENDPOINT VF DRIVER
M: Veerasenareddy Burru <vburru@marvell.com>
M: Sathesh Edara <sedara@marvell.com>
M: Shinas Rasheed <srasheed@marvell.com>
M: Satananda Burla <sburla@marvell.com>
L: netdev@vger.kernel.org
S: Supported
F: drivers/net/ethernet/marvell/octeon_ep_vf
MARVELL OCTEONTX2 PHYSICAL FUNCTION DRIVER
M: Sunil Goutham <sgoutham@marvell.com>
M: Geetha sowjanya <gakula@marvell.com>
......
drivers/net/ethernet/marvell/Kconfig
View file @ 63c7234f
......@@ -180,7 +180,6 @@ config SKY2_DEBUG
source "drivers/net/ethernet/marvell/octeontx2/Kconfig"
source "drivers/net/ethernet/marvell/octeon_ep/Kconfig"
source "drivers/net/ethernet/marvell/octeon_ep_vf/Kconfig"
source "drivers/net/ethernet/marvell/prestera/Kconfig"
endif # NET_VENDOR_MARVELL
drivers/net/ethernet/marvell/Makefile
View file @ 63c7234f
......@@ -12,6 +12,5 @@ obj-$(CONFIG_PXA168_ETH) += pxa168_eth.o
obj-$(CONFIG_SKGE) += skge.o
obj-$(CONFIG_SKY2) += sky2.o
obj-y += octeon_ep/
obj-y += octeon_ep_vf/
obj-y += octeontx2/
obj-y += prestera/
drivers/net/ethernet/marvell/octeon_ep_vf/Kconfig deleted 100644 → 0
View file @ 5e5401d6
# SPDX-License-Identifier: GPL-2.0-only
#
# Marvell's Octeon PCI Endpoint NIC VF Driver Configuration
#
config OCTEON_EP_VF
tristate "Marvell Octeon PCI Endpoint NIC VF Driver"
depends on 64BIT
depends on PCI
help
This driver supports networking functionality of Marvell's
Octeon PCI Endpoint NIC VF.
To know the list of devices supported by this driver, refer
documentation in
<file:Documentation/networking/device_drivers/ethernet/marvell/octeon_ep_vf.rst>.
To compile this drivers as a module, choose M here. Name of the
module is octeon_ep_vf.
drivers/net/ethernet/marvell/octeon_ep_vf/Makefile deleted 100644 → 0
View file @ 5e5401d6
# SPDX-License-Identifier: GPL-2.0
#
# Network driver for Marvell's Octeon PCI Endpoint NIC VF
#
obj-$(CONFIG_OCTEON_EP_VF) += octeon_ep_vf.o
octeon_ep_vf-y := octep_vf_main.o octep_vf_cn9k.o octep_vf_cnxk.o \
octep_vf_tx.o octep_vf_rx.o octep_vf_mbox.o \
octep_vf_ethtool.o
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_config.h deleted 100644 → 0
View file @ 5e5401d6
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell Octeon EP (EndPoint) VF Ethernet Driver
*
* Copyright (C) 2020 Marvell.
*
*/
#ifndef _OCTEP_VF_CONFIG_H_
#define _OCTEP_VF_CONFIG_H_
/* Tx instruction types by length */
#define OCTEP_VF_32BYTE_INSTR 32
#define OCTEP_VF_64BYTE_INSTR 64
/* Tx Queue: maximum descriptors per ring */
#define OCTEP_VF_IQ_MAX_DESCRIPTORS 1024
/* Minimum input (Tx) requests to be enqueued to ring doorbell */
#define OCTEP_VF_DB_MIN 8
/* Packet threshold for Tx queue interrupt */
#define OCTEP_VF_IQ_INTR_THRESHOLD 0x0
/* Minimum watermark for backpressure */
#define OCTEP_VF_OQ_WMARK_MIN 256
/* Rx Queue: maximum descriptors per ring */
#define OCTEP_VF_OQ_MAX_DESCRIPTORS 1024
/* Rx buffer size: Use page size buffers.
* Build skb from allocated page buffer once the packet is received.
* When a gathered packet is received, make head page as skb head and
* page buffers in consecutive Rx descriptors as fragments.
*/
#define OCTEP_VF_OQ_BUF_SIZE (SKB_WITH_OVERHEAD(PAGE_SIZE))
#define OCTEP_VF_OQ_PKTS_PER_INTR 128
#define OCTEP_VF_OQ_REFILL_THRESHOLD (OCTEP_VF_OQ_MAX_DESCRIPTORS / 4)
#define OCTEP_VF_OQ_INTR_PKT_THRESHOLD 1
#define OCTEP_VF_OQ_INTR_TIME_THRESHOLD 10
#define OCTEP_VF_MSIX_NAME_SIZE (IFNAMSIZ + 32)
/* Tx Queue wake threshold
* wakeup a stopped Tx queue if minimum 2 descriptors are available.
* Even a skb with fragments consume only one Tx queue descriptor entry.
*/
#define OCTEP_VF_WAKE_QUEUE_THRESHOLD 2
/* Minimum MTU supported by Octeon network interface */
#define OCTEP_VF_MIN_MTU ETH_MIN_MTU
/* Maximum MTU supported by Octeon interface*/
#define OCTEP_VF_MAX_MTU (10000 - (ETH_HLEN + ETH_FCS_LEN))
/* Default MTU */
#define OCTEP_VF_DEFAULT_MTU 1500
/* Macros to get octeon config params */
#define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
#define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs)
#define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
#define CFG_GET_IQ_INSTR_SIZE(cfg) (64)
#define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
#define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold)
#define CFG_GET_OQ_NUM_DESC(cfg) ((cfg)->oq.num_descs)
#define CFG_GET_OQ_BUF_SIZE(cfg) ((cfg)->oq.buf_size)
#define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold)
#define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt)
#define CFG_GET_OQ_INTR_TIME(cfg) ((cfg)->oq.oq_intr_time)
#define CFG_GET_OQ_WMARK(cfg) ((cfg)->oq.wmark)
#define CFG_GET_PORTS_ACTIVE_IO_RINGS(cfg) ((cfg)->ring_cfg.active_io_rings)
#define CFG_GET_PORTS_MAX_IO_RINGS(cfg) ((cfg)->ring_cfg.max_io_rings)
#define CFG_GET_CORE_TICS_PER_US(cfg) ((cfg)->core_cfg.core_tics_per_us)
#define CFG_GET_COPROC_TICS_PER_US(cfg) ((cfg)->core_cfg.coproc_tics_per_us)
#define CFG_GET_IOQ_MSIX(cfg) ((cfg)->msix_cfg.ioq_msix)
/* Hardware Tx Queue configuration. */
struct octep_vf_iq_config {
/* Size of the Input queue (number of commands) */
u16 num_descs;
/* Command size - 32 or 64 bytes */
u16 instr_type;
/* Minimum number of commands pending to be posted to Octeon before driver
* hits the Input queue doorbell.
*/
u16 db_min;
/* Trigger the IQ interrupt when processed cmd count reaches
* this level.
*/
u32 intr_threshold;
};
/* Hardware Rx Queue configuration. */
struct octep_vf_oq_config {
/* Size of Output queue (number of descriptors) */
u16 num_descs;
/* Size of buffer in this Output queue. */
u16 buf_size;
/* The number of buffers that were consumed during packet processing
* by the driver on this Output queue before the driver attempts to
* replenish the descriptor ring with new buffers.
*/
u16 refill_threshold;
/* Interrupt Coalescing (Packet Count). Octeon will interrupt the host
* only if it sent as many packets as specified by this field.
* The driver usually does not use packet count interrupt coalescing.
*/
u32 oq_intr_pkt;
/* Interrupt Coalescing (Time Interval). Octeon will interrupt the host
* if at least one packet was sent in the time interval specified by
* this field. The driver uses time interval interrupt coalescing by
* default. The time is specified in microseconds.
*/
u32 oq_intr_time;
/* Water mark for backpressure.
* Output queue sends backpressure signal to source when
* free buffer count falls below wmark.
*/
u32 wmark;
};
/* Tx/Rx configuration */
struct octep_vf_ring_config {
/* Max number of IOQs */
u16 max_io_rings;
/* Number of active IOQs */
u16 active_io_rings;
};
/* Octeon MSI-x config. */
struct octep_vf_msix_config {
/* Number of IOQ interrupts */
u16 ioq_msix;
};
/* Data Structure to hold configuration limits and active config */
struct octep_vf_config {
/* Input Queue attributes. */
struct octep_vf_iq_config iq;
/* Output Queue attributes. */
struct octep_vf_oq_config oq;
/* MSI-X interrupt config */
struct octep_vf_msix_config msix_cfg;
/* NIC VF ring Configuration */
struct octep_vf_ring_config ring_cfg;
};
#endif /* _OCTEP_VF_CONFIG_H_ */
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h deleted 100644 → 0
View file @ 5e5401d6
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell Octeon EP (EndPoint) VF Ethernet Driver
*
* Copyright (C) 2020 Marvell.
*
*/
#ifndef _OCTEP_VF_MAIN_H_
#define _OCTEP_VF_MAIN_H_
#include "octep_vf_tx.h"
#include "octep_vf_rx.h"
#include "octep_vf_mbox.h"
#define OCTEP_VF_DRV_NAME "octeon_ep_vf"
#define OCTEP_VF_DRV_STRING "Marvell Octeon EndPoint NIC VF Driver"
#define OCTEP_PCI_DEVICE_ID_CN93_VF 0xB203 //93xx VF
#define OCTEP_PCI_DEVICE_ID_CNF95N_VF 0xB403 //95N VF
#define OCTEP_PCI_DEVICE_ID_CN98_VF 0xB103
#define OCTEP_PCI_DEVICE_ID_CN10KA_VF 0xB903
#define OCTEP_PCI_DEVICE_ID_CNF10KA_VF 0xBA03
#define OCTEP_PCI_DEVICE_ID_CNF10KB_VF 0xBC03
#define OCTEP_PCI_DEVICE_ID_CN10KB_VF 0xBD03
#define OCTEP_VF_MAX_QUEUES 63
#define OCTEP_VF_MAX_IQ OCTEP_VF_MAX_QUEUES
#define OCTEP_VF_MAX_OQ OCTEP_VF_MAX_QUEUES
#define OCTEP_VF_MAX_MSIX_VECTORS OCTEP_VF_MAX_OQ
#define OCTEP_VF_IQ_INTR_RESEND_BIT 59
#define OCTEP_VF_OQ_INTR_RESEND_BIT 59
#define IQ_INSTR_PENDING(iq) ({ typeof(iq) iq__ = (iq); \
((iq__)->host_write_index - (iq__)->flush_index) & \
(iq__)->ring_size_mask; \
})
#define IQ_INSTR_SPACE(iq) ({ typeof(iq) iq_ = (iq); \
(iq_)->max_count - IQ_INSTR_PENDING(iq_); \
})
#ifndef UINT64_MAX
#define UINT64_MAX ((u64)(~((u64)0))) /* 0xFFFFFFFFFFFFFFFF */
#endif
/* PCI address space mapping information.
* Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of
* Octeon gets mapped to different physical address spaces in
* the kernel.
*/
struct octep_vf_mmio {
/* The physical address to which the PCI address space is mapped. */
u8 __iomem *hw_addr;
/* Flag indicating the mapping was successful. */
int mapped;
};
struct octep_vf_hw_ops {
void (*setup_iq_regs)(struct octep_vf_device *oct, int q);
void (*setup_oq_regs)(struct octep_vf_device *oct, int q);
void (*setup_mbox_regs)(struct octep_vf_device *oct, int mbox);
irqreturn_t (*non_ioq_intr_handler)(void *ioq_vector);
irqreturn_t (*ioq_intr_handler)(void *ioq_vector);
void (*reinit_regs)(struct octep_vf_device *oct);
u32 (*update_iq_read_idx)(struct octep_vf_iq *iq);
void (*enable_interrupts)(struct octep_vf_device *oct);
void (*disable_interrupts)(struct octep_vf_device *oct);
void (*enable_io_queues)(struct octep_vf_device *oct);
void (*disable_io_queues)(struct octep_vf_device *oct);
void (*enable_iq)(struct octep_vf_device *oct, int q);
void (*disable_iq)(struct octep_vf_device *oct, int q);
void (*enable_oq)(struct octep_vf_device *oct, int q);
void (*disable_oq)(struct octep_vf_device *oct, int q);
void (*reset_io_queues)(struct octep_vf_device *oct);
void (*dump_registers)(struct octep_vf_device *oct);
};
/* Octeon mailbox data */
struct octep_vf_mbox_data {
/* Holds the offset of received data via mailbox. */
u32 data_index;
/* Holds the received data via mailbox. */
u8 recv_data[OCTEP_PFVF_MBOX_MAX_DATA_BUF_SIZE];
};
/* wrappers around work structs */
struct octep_vf_mbox_wk {
struct work_struct work;
void *ctxptr;
};
/* Octeon device mailbox */
struct octep_vf_mbox {
/* A mutex to protect access to this q_mbox. */
struct mutex lock;
u32 state;
/* SLI_MAC_PF_MBOX_INT for PF, SLI_PKT_MBOX_INT for VF. */
u8 __iomem *mbox_int_reg;
/* SLI_PKT_PF_VF_MBOX_SIG(0) for PF,
* SLI_PKT_PF_VF_MBOX_SIG(1) for VF.
*/
u8 __iomem *mbox_write_reg;
/* SLI_PKT_PF_VF_MBOX_SIG(1) for PF,
* SLI_PKT_PF_VF_MBOX_SIG(0) for VF.
*/
u8 __iomem *mbox_read_reg;
/* Octeon mailbox data */
struct octep_vf_mbox_data mbox_data;
/* Octeon mailbox work handler to process Mbox messages */
struct octep_vf_mbox_wk wk;
};
/* Tx/Rx queue vector per interrupt. */
struct octep_vf_ioq_vector {
char name[OCTEP_VF_MSIX_NAME_SIZE];
struct napi_struct napi;
struct octep_vf_device *octep_vf_dev;
struct octep_vf_iq *iq;
struct octep_vf_oq *oq;
cpumask_t affinity_mask;
};
/* Octeon hardware/firmware offload capability flags. */
#define OCTEP_VF_CAP_TX_CHECKSUM BIT(0)
#define OCTEP_VF_CAP_RX_CHECKSUM BIT(1)
#define OCTEP_VF_CAP_TSO BIT(2)
/* Link modes */
enum octep_vf_link_mode_bit_indices {
OCTEP_VF_LINK_MODE_10GBASE_T = 0,
OCTEP_VF_LINK_MODE_10GBASE_R,
OCTEP_VF_LINK_MODE_10GBASE_CR,
OCTEP_VF_LINK_MODE_10GBASE_KR,
OCTEP_VF_LINK_MODE_10GBASE_LR,
OCTEP_VF_LINK_MODE_10GBASE_SR,
OCTEP_VF_LINK_MODE_25GBASE_CR,
OCTEP_VF_LINK_MODE_25GBASE_KR,
OCTEP_VF_LINK_MODE_25GBASE_SR,
OCTEP_VF_LINK_MODE_40GBASE_CR4,
OCTEP_VF_LINK_MODE_40GBASE_KR4,
OCTEP_VF_LINK_MODE_40GBASE_LR4,
OCTEP_VF_LINK_MODE_40GBASE_SR4,
OCTEP_VF_LINK_MODE_50GBASE_CR2,
OCTEP_VF_LINK_MODE_50GBASE_KR2,
OCTEP_VF_LINK_MODE_50GBASE_SR2,
OCTEP_VF_LINK_MODE_50GBASE_CR,
OCTEP_VF_LINK_MODE_50GBASE_KR,
OCTEP_VF_LINK_MODE_50GBASE_LR,
OCTEP_VF_LINK_MODE_50GBASE_SR,
OCTEP_VF_LINK_MODE_100GBASE_CR4,
OCTEP_VF_LINK_MODE_100GBASE_KR4,
OCTEP_VF_LINK_MODE_100GBASE_LR4,
OCTEP_VF_LINK_MODE_100GBASE_SR4,
OCTEP_VF_LINK_MODE_NBITS
};
/* Hardware interface link state information. */
struct octep_vf_iface_link_info {
/* Bitmap of Supported link speeds/modes. */
u64 supported_modes;
/* Bitmap of Advertised link speeds/modes. */
u64 advertised_modes;
/* Negotiated link speed in Mbps. */
u32 speed;
/* MTU */
u16 mtu;
/* Autonegotiation state. */
#define OCTEP_VF_LINK_MODE_AUTONEG_SUPPORTED BIT(0)
#define OCTEP_VF_LINK_MODE_AUTONEG_ADVERTISED BIT(1)
u8 autoneg;
/* Pause frames setting. */
#define OCTEP_VF_LINK_MODE_PAUSE_SUPPORTED BIT(0)
#define OCTEP_VF_LINK_MODE_PAUSE_ADVERTISED BIT(1)
u8 pause;
/* Admin state of the link (ifconfig <iface> up/down */
u8 admin_up;
/* Operational state of the link: physical link is up down */
u8 oper_up;
};
/* Hardware interface stats information. */
struct octep_vf_iface_rxtx_stats {
/* Hardware Interface Rx statistics */
struct octep_vf_iface_rx_stats iface_rx_stats;
/* Hardware Interface Tx statistics */
struct octep_vf_iface_tx_stats iface_tx_stats;
};
struct octep_vf_fw_info {
/* pkind value to be used in every Tx hardware descriptor */
u8 pkind;
/* front size data */
u8 fsz;
/* supported rx offloads OCTEP_VF_RX_OFFLOAD_* */
u16 rx_ol_flags;
/* supported tx offloads OCTEP_VF_TX_OFFLOAD_* */
u16 tx_ol_flags;
};
/* The Octeon device specific private data structure.
* Each Octeon device has this structure to represent all its components.
*/
struct octep_vf_device {
struct octep_vf_config *conf;
/* Octeon Chip type. */
u16 chip_id;
u16 rev_id;
/* Device capabilities enabled */
u64 caps_enabled;
/* Device capabilities supported */
u64 caps_supported;
/* Pointer to basic Linux device */
struct device *dev;
/* Linux PCI device pointer */
struct pci_dev *pdev;
/* Netdev corresponding to the Octeon device */
struct net_device *netdev;
/* memory mapped io range */
struct octep_vf_mmio mmio;
/* MAC address */
u8 mac_addr[ETH_ALEN];
/* Tx queues (IQ: Instruction Queue) */
u16 num_iqs;
/* Pointers to Octeon Tx queues */
struct octep_vf_iq *iq[OCTEP_VF_MAX_IQ];
/* Rx queues (OQ: Output Queue) */
u16 num_oqs;
/* Pointers to Octeon Rx queues */
struct octep_vf_oq *oq[OCTEP_VF_MAX_OQ];
/* Hardware port number of the PCIe interface */
u16 pcie_port;
/* Hardware operations */
struct octep_vf_hw_ops hw_ops;
/* IRQ info */
u16 num_irqs;
u16 num_non_ioq_irqs;
char *non_ioq_irq_names;
struct msix_entry *msix_entries;
/* IOq information of it's corresponding MSI-X interrupt. */
struct octep_vf_ioq_vector *ioq_vector[OCTEP_VF_MAX_QUEUES];
/* Hardware Interface Tx statistics */
struct octep_vf_iface_tx_stats iface_tx_stats;
/* Hardware Interface Rx statistics */
struct octep_vf_iface_rx_stats iface_rx_stats;
/* Hardware Interface Link info like supported modes, aneg support */
struct octep_vf_iface_link_info link_info;
/* Mailbox to talk to VFs */
struct octep_vf_mbox *mbox;
/* Work entry to handle Tx timeout */
struct work_struct tx_timeout_task;
/* offset for iface stats */
u32 ctrl_mbox_ifstats_offset;
/* Negotiated Mbox version */
u32 mbox_neg_ver;
/* firmware info */
struct octep_vf_fw_info fw_info;
};
static inline u16 OCTEP_VF_MAJOR_REV(struct octep_vf_device *oct)
{
u16 rev = (oct->rev_id & 0xC) >> 2;
return (rev == 0) ? 1 : rev;
}
static inline u16 OCTEP_VF_MINOR_REV(struct octep_vf_device *oct)
{
return (oct->rev_id & 0x3);
}
/* Octeon CSR read/write access APIs */
#define octep_vf_write_csr(octep_vf_dev, reg_off, value) \
writel(value, (octep_vf_dev)->mmio.hw_addr + (reg_off))
#define octep_vf_write_csr64(octep_vf_dev, reg_off, val64) \
writeq(val64, (octep_vf_dev)->mmio.hw_addr + (reg_off))
#define octep_vf_read_csr(octep_vf_dev, reg_off) \
readl((octep_vf_dev)->mmio.hw_addr + (reg_off))
#define octep_vf_read_csr64(octep_vf_dev, reg_off) \
readq((octep_vf_dev)->mmio.hw_addr + (reg_off))
extern struct workqueue_struct *octep_vf_wq;
int octep_vf_device_setup(struct octep_vf_device *oct);
int octep_vf_setup_iqs(struct octep_vf_device *oct);
void octep_vf_free_iqs(struct octep_vf_device *oct);
void octep_vf_clean_iqs(struct octep_vf_device *oct);
int octep_vf_setup_oqs(struct octep_vf_device *oct);
void octep_vf_free_oqs(struct octep_vf_device *oct);
void octep_vf_oq_dbell_init(struct octep_vf_device *oct);
void octep_vf_device_setup_cn93(struct octep_vf_device *oct);
void octep_vf_device_setup_cnxk(struct octep_vf_device *oct);
int octep_vf_iq_process_completions(struct octep_vf_iq *iq, u16 budget);
int octep_vf_oq_process_rx(struct octep_vf_oq *oq, int budget);
void octep_vf_set_ethtool_ops(struct net_device *netdev);
int octep_vf_get_link_info(struct octep_vf_device *oct);
int octep_vf_get_if_stats(struct octep_vf_device *oct);
void octep_vf_mbox_work(struct work_struct *work);
#endif /* _OCTEP_VF_MAIN_H_ */
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_mbox.h deleted 100644 → 0
View file @ 5e5401d6
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell Octeon EP (EndPoint) Ethernet Driver
*
* Copyright (C) 2020 Marvell.
*
*/
#ifndef _OCTEP_VF_MBOX_H_
#define _OCTEP_VF_MBOX_H_
/* When a new command is implemented, VF Mbox version should be bumped.
*/
enum octep_pfvf_mbox_version {
OCTEP_PFVF_MBOX_VERSION_V0,
OCTEP_PFVF_MBOX_VERSION_V1,
OCTEP_PFVF_MBOX_VERSION_V2
};
#define OCTEP_PFVF_MBOX_VERSION_CURRENT OCTEP_PFVF_MBOX_VERSION_V2
enum octep_pfvf_mbox_opcode {
OCTEP_PFVF_MBOX_CMD_VERSION,
OCTEP_PFVF_MBOX_CMD_SET_MTU,
OCTEP_PFVF_MBOX_CMD_SET_MAC_ADDR,
OCTEP_PFVF_MBOX_CMD_GET_MAC_ADDR,
OCTEP_PFVF_MBOX_CMD_GET_LINK_INFO,
OCTEP_PFVF_MBOX_CMD_GET_STATS,
OCTEP_PFVF_MBOX_CMD_SET_RX_STATE,
OCTEP_PFVF_MBOX_CMD_SET_LINK_STATUS,
OCTEP_PFVF_MBOX_CMD_GET_LINK_STATUS,
OCTEP_PFVF_MBOX_CMD_GET_MTU,
OCTEP_PFVF_MBOX_CMD_DEV_REMOVE,
OCTEP_PFVF_MBOX_CMD_GET_FW_INFO,
OCTEP_PFVF_MBOX_CMD_SET_OFFLOADS,
OCTEP_PFVF_MBOX_NOTIF_LINK_STATUS,
OCTEP_PFVF_MBOX_CMD_MAX,
};
enum octep_pfvf_mbox_word_type {
OCTEP_PFVF_MBOX_TYPE_CMD,
OCTEP_PFVF_MBOX_TYPE_RSP_ACK,
OCTEP_PFVF_MBOX_TYPE_RSP_NACK,
};
enum octep_pfvf_mbox_cmd_status {
OCTEP_PFVF_MBOX_CMD_STATUS_NOT_SETUP = 1,
OCTEP_PFVF_MBOX_CMD_STATUS_TIMEDOUT = 2,
OCTEP_PFVF_MBOX_CMD_STATUS_NACK = 3,
OCTEP_PFVF_MBOX_CMD_STATUS_BUSY = 4,
OCTEP_PFVF_MBOX_CMD_STATUS_ERR = 5
};
enum octep_pfvf_link_status {
OCTEP_PFVF_LINK_STATUS_DOWN,
OCTEP_PFVF_LINK_STATUS_UP,
};
enum octep_pfvf_link_speed {
OCTEP_PFVF_LINK_SPEED_NONE,
OCTEP_PFVF_LINK_SPEED_1000,
OCTEP_PFVF_LINK_SPEED_10000,
OCTEP_PFVF_LINK_SPEED_25000,
OCTEP_PFVF_LINK_SPEED_40000,
OCTEP_PFVF_LINK_SPEED_50000,
OCTEP_PFVF_LINK_SPEED_100000,
OCTEP_PFVF_LINK_SPEED_LAST,
};
enum octep_pfvf_link_duplex {
OCTEP_PFVF_LINK_HALF_DUPLEX,
OCTEP_PFVF_LINK_FULL_DUPLEX,
};
enum octep_pfvf_link_autoneg {
OCTEP_PFVF_LINK_AUTONEG,
OCTEP_PFVF_LINK_FIXED,
};
#define OCTEP_PFVF_MBOX_TIMEOUT_WAIT_COUNT 8000
#define OCTEP_PFVF_MBOX_TIMEOUT_WAIT_UDELAY 1000
#define OCTEP_PFVF_MBOX_MAX_RETRIES 2
#define OCTEP_PFVF_MBOX_VERSION 0
#define OCTEP_PFVF_MBOX_MAX_DATA_SIZE 6
#define OCTEP_PFVF_MBOX_MAX_DATA_BUF_SIZE 320
#define OCTEP_PFVF_MBOX_MORE_FRAG_FLAG 1
union octep_pfvf_mbox_word {
u64 u64;
struct {
u64 opcode:8;
u64 type:2;
u64 rsvd:6;
u64 data:48;
} s;
struct {
u64 opcode:8;
u64 type:2;
u64 frag:1;
u64 rsvd:5;
u8 data[6];
} s_data;
struct {
u64 opcode:8;
u64 type:2;
u64 rsvd:6;
u64 version:48;
} s_version;
struct {
u64 opcode:8;
u64 type:2;
u64 rsvd:6;
u8 mac_addr[6];
} s_set_mac;
struct {
u64 opcode:8;
u64 type:2;
u64 rsvd:6;
u64 mtu:48;
} s_set_mtu;
struct {
u64 opcode:8;
u64 type:2;
u64 state:1;
u64 rsvd:53;
} s_link_state;
struct {
u64 opcode:8;
u64 type:2;
u64 status:1;
u64 rsvd:53;
} s_link_status;
struct {
u64 opcode:8;
u64 type:2;
u64 pkind:8;
u64 fsz:8;
u64 rx_ol_flags:16;
u64 tx_ol_flags:16;
u64 rsvd:6;
} s_fw_info;
struct {
u64 opcode:8;
u64 type:2;
u64 rsvd:22;
u64 rx_ol_flags:16;
u64 tx_ol_flags:16;
} s_offloads;
} __packed;
int octep_vf_setup_mbox(struct octep_vf_device *oct);
void octep_vf_delete_mbox(struct octep_vf_device *oct);
int octep_vf_mbox_send_cmd(struct octep_vf_device *oct, union octep_pfvf_mbox_word cmd,
union octep_pfvf_mbox_word *rsp);
int octep_vf_mbox_bulk_read(struct octep_vf_device *oct, enum octep_pfvf_mbox_opcode opcode,
u8 *data, int *size);
int octep_vf_mbox_set_mtu(struct octep_vf_device *oct, int mtu);
int octep_vf_mbox_set_mac_addr(struct octep_vf_device *oct, char *mac_addr);
int octep_vf_mbox_get_mac_addr(struct octep_vf_device *oct, char *mac_addr);
int octep_vf_mbox_version_check(struct octep_vf_device *oct);
int octep_vf_mbox_set_rx_state(struct octep_vf_device *oct, bool state);
int octep_vf_mbox_set_link_status(struct octep_vf_device *oct, bool status);
int octep_vf_mbox_get_link_status(struct octep_vf_device *oct, u8 *oper_up);
int octep_vf_mbox_dev_remove(struct octep_vf_device *oct);
int octep_vf_mbox_get_fw_info(struct octep_vf_device *oct);
int octep_vf_mbox_set_offloads(struct octep_vf_device *oct, u16 tx_offloads, u16 rx_offloads);
#endif
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cn9k.h deleted 100644 → 0
View file @ 5e5401d6
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell Octeon EP (EndPoint) VF Ethernet Driver
*
* Copyright (C) 2020 Marvell.
*
*/
#ifndef _OCTEP_VF_REGS_CN9K_H_
#define _OCTEP_VF_REGS_CN9K_H_
/*############################ RST #########################*/
#define CN93_VF_CONFIG_XPANSION_BAR 0x38
#define CN93_VF_CONFIG_PCIE_CAP 0x70
#define CN93_VF_CONFIG_PCIE_DEVCAP 0x74
#define CN93_VF_CONFIG_PCIE_DEVCTL 0x78
#define CN93_VF_CONFIG_PCIE_LINKCAP 0x7C
#define CN93_VF_CONFIG_PCIE_LINKCTL 0x80
#define CN93_VF_CONFIG_PCIE_SLOTCAP 0x84
#define CN93_VF_CONFIG_PCIE_SLOTCTL 0x88
#define CN93_VF_RING_OFFSET BIT_ULL(17)
/*###################### RING IN REGISTERS #########################*/
#define CN93_VF_SDP_R_IN_CONTROL_START 0x10000
#define CN93_VF_SDP_R_IN_ENABLE_START 0x10010
#define CN93_VF_SDP_R_IN_INSTR_BADDR_START 0x10020
#define CN93_VF_SDP_R_IN_INSTR_RSIZE_START 0x10030
#define CN93_VF_SDP_R_IN_INSTR_DBELL_START 0x10040
#define CN93_VF_SDP_R_IN_CNTS_START 0x10050
#define CN93_VF_SDP_R_IN_INT_LEVELS_START 0x10060
#define CN93_VF_SDP_R_IN_PKT_CNT_START 0x10080
#define CN93_VF_SDP_R_IN_BYTE_CNT_START 0x10090
#define CN93_VF_SDP_R_IN_CONTROL(ring) \
(CN93_VF_SDP_R_IN_CONTROL_START + ((ring) * CN93_VF_RING_OFFSET))
#define CN93_VF_SDP_R_IN_ENABLE(ring) \
(CN93_VF_SDP_R_IN_ENABLE_START + ((ring) * CN93_VF_RING_OFFSET))
#define CN93_VF_SDP_R_IN_INSTR_BADDR(ring) \
(CN93_VF_SDP_R_IN_INSTR_BADDR_START + ((ring) * CN93_VF_RING_OFFSET))
#define CN93_VF_SDP_R_IN_INSTR_RSIZE(ring) \
(CN93_VF_SDP_R_IN_INSTR_RSIZE_START + ((ring) * CN93_VF_RING_OFFSET))
#define CN93_VF_SDP_R_IN_INSTR_DBELL(ring) \
(CN93_VF_SDP_R_IN_INSTR_DBELL_START + ((ring) * CN93_VF_RING_OFFSET))
#define CN93_VF_SDP_R_IN_CNTS(ring) \
(CN93_VF_SDP_R_IN_CNTS_START + ((ring) * CN93_VF_RING_OFFSET))
#define CN93_VF_SDP_R_IN_INT_LEVELS(ring) \
(CN93_VF_SDP_R_IN_INT_LEVELS_START + ((ring) * CN93_VF_RING_OFFSET))
#define CN93_VF_SDP_R_IN_PKT_CNT(ring) \
(CN93_VF_SDP_R_IN_PKT_CNT_START + ((ring) * CN93_VF_RING_OFFSET))
#define CN93_VF_SDP_R_IN_BYTE_CNT(ring) \
(CN93_VF_SDP_R_IN_BYTE_CNT_START + ((ring) * CN93_VF_RING_OFFSET))
/*------------------ R_IN Masks ----------------*/
/** Rings per Virtual Function **/
#define CN93_VF_R_IN_CTL_RPVF_MASK (0xF)
#define CN93_VF_R_IN_CTL_RPVF_POS (48)
/* Number of instructions to be read in one MAC read request.
* setting to Max value(4)
**/
#define CN93_VF_R_IN_CTL_IDLE BIT_ULL(28)
#define CN93_VF_R_IN_CTL_RDSIZE (0x3ULL << 25)
#define CN93_VF_R_IN_CTL_IS_64B BIT_ULL(24)
#define CN93_VF_R_IN_CTL_D_NSR BIT_ULL(8)
#define CN93_VF_R_IN_CTL_D_ESR BIT_ULL(6)
#define CN93_VF_R_IN_CTL_D_ROR BIT_ULL(5)
#define CN93_VF_R_IN_CTL_NSR BIT_ULL(3)
#define CN93_VF_R_IN_CTL_ESR BIT_ULL(1)
#define CN93_VF_R_IN_CTL_ROR BIT_ULL(0)
#define CN93_VF_R_IN_CTL_MASK (CN93_VF_R_IN_CTL_RDSIZE | CN93_VF_R_IN_CTL_IS_64B)
/*###################### RING OUT REGISTERS #########################*/
#define CN93_VF_SDP_R_OUT_CNTS_START 0x10100
#define CN93_VF_SDP_R_OUT_INT_LEVELS_START 0x10110
#define CN93_VF_SDP_R_OUT_SLIST_BADDR_START 0x10120
#define CN93_VF_SDP_R_OUT_SLIST_RSIZE_START 0x10130
#define CN93_VF_SDP_R_OUT_SLIST_DBELL_START 0x10140
#define CN93_VF_SDP_R_OUT_CONTROL_START 0x10150
#define CN93_VF_SDP_R_OUT_ENABLE_START 0x10160
#define CN93_VF_SDP_R_OUT_PKT_CNT_START 0x10180
#define CN93_VF_SDP_R_OUT_BYTE_CNT_START 0x10190
#define CN93_VF_SDP_R_OUT_CONTROL(ring) \
(CN93_VF_SDP_R_OUT_CONTROL_START + ((ring) * CN93_VF_RING_OFFSET))
#define CN93_VF_SDP_R_OUT_ENABLE(ring) \
(CN93_VF_SDP_R_OUT_ENABLE_START + ((ring) * CN93_VF_RING_OFFSET))
#define CN93_VF_SDP_R_OUT_SLIST_BADDR(ring) \
(CN93_VF_SDP_R_OUT_SLIST_BADDR_START + ((ring) * CN93_VF_RING_OFFSET))
#define CN93_VF_SDP_R_OUT_SLIST_RSIZE(ring) \
(CN93_VF_SDP_R_OUT_SLIST_RSIZE_START + ((ring) * CN93_VF_RING_OFFSET))
#define CN93_VF_SDP_R_OUT_SLIST_DBELL(ring) \
(CN93_VF_SDP_R_OUT_SLIST_DBELL_START + ((ring) * CN93_VF_RING_OFFSET))
#define CN93_VF_SDP_R_OUT_CNTS(ring) \
(CN93_VF_SDP_R_OUT_CNTS_START + ((ring) * CN93_VF_RING_OFFSET))
#define CN93_VF_SDP_R_OUT_INT_LEVELS(ring) \
(CN93_VF_SDP_R_OUT_INT_LEVELS_START + ((ring) * CN93_VF_RING_OFFSET))
#define CN93_VF_SDP_R_OUT_PKT_CNT(ring) \
(CN93_VF_SDP_R_OUT_PKT_CNT_START + ((ring) * CN93_VF_RING_OFFSET))
#define CN93_VF_SDP_R_OUT_BYTE_CNT(ring) \
(CN93_VF_SDP_R_OUT_BYTE_CNT_START + ((ring) * CN93_VF_RING_OFFSET))
/*------------------ R_OUT Masks ----------------*/
#define CN93_VF_R_OUT_INT_LEVELS_BMODE BIT_ULL(63)
#define CN93_VF_R_OUT_INT_LEVELS_TIMET (32)
#define CN93_VF_R_OUT_CTL_IDLE BIT_ULL(40)
#define CN93_VF_R_OUT_CTL_ES_I BIT_ULL(34)
#define CN93_VF_R_OUT_CTL_NSR_I BIT_ULL(33)
#define CN93_VF_R_OUT_CTL_ROR_I BIT_ULL(32)
#define CN93_VF_R_OUT_CTL_ES_D BIT_ULL(30)
#define CN93_VF_R_OUT_CTL_NSR_D BIT_ULL(29)
#define CN93_VF_R_OUT_CTL_ROR_D BIT_ULL(28)
#define CN93_VF_R_OUT_CTL_ES_P BIT_ULL(26)
#define CN93_VF_R_OUT_CTL_NSR_P BIT_ULL(25)
#define CN93_VF_R_OUT_CTL_ROR_P BIT_ULL(24)
#define CN93_VF_R_OUT_CTL_IMODE BIT_ULL(23)
/* ##################### Mail Box Registers ########################## */
/* SDP PF to VF Mailbox Data Register */
#define CN93_VF_SDP_R_MBOX_PF_VF_DATA_START 0x10210
/* SDP Packet PF to VF Mailbox Interrupt Register */
#define CN93_VF_SDP_R_MBOX_PF_VF_INT_START 0x10220
/* SDP VF to PF Mailbox Data Register */
#define CN93_VF_SDP_R_MBOX_VF_PF_DATA_START 0x10230
#define CN93_VF_SDP_R_MBOX_PF_VF_INT_ENAB BIT_ULL(1)
#define CN93_VF_SDP_R_MBOX_PF_VF_INT_STATUS BIT_ULL(0)
#define CN93_VF_SDP_R_MBOX_PF_VF_DATA(ring) \
(CN93_VF_SDP_R_MBOX_PF_VF_DATA_START + ((ring) * CN93_VF_RING_OFFSET))
#define CN93_VF_SDP_R_MBOX_PF_VF_INT(ring) \
(CN93_VF_SDP_R_MBOX_PF_VF_INT_START + ((ring) * CN93_VF_RING_OFFSET))
#define CN93_VF_SDP_R_MBOX_VF_PF_DATA(ring) \
(CN93_VF_SDP_R_MBOX_VF_PF_DATA_START + ((ring) * CN93_VF_RING_OFFSET))
#endif /* _OCTEP_VF_REGS_CN9K_H_ */
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_regs_cnxk.h deleted 100644 → 0
View file @ 5e5401d6
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell Octeon EP (EndPoint) VF Ethernet Driver
*
* Copyright (C) 2020 Marvell.
*
*/
#ifndef _OCTEP_VF_REGS_CNXK_H_
#define _OCTEP_VF_REGS_CNXK_H_
/*############################ RST #########################*/
#define CNXK_VF_CONFIG_XPANSION_BAR 0x38
#define CNXK_VF_CONFIG_PCIE_CAP 0x70
#define CNXK_VF_CONFIG_PCIE_DEVCAP 0x74
#define CNXK_VF_CONFIG_PCIE_DEVCTL 0x78
#define CNXK_VF_CONFIG_PCIE_LINKCAP 0x7C
#define CNXK_VF_CONFIG_PCIE_LINKCTL 0x80
#define CNXK_VF_CONFIG_PCIE_SLOTCAP 0x84
#define CNXK_VF_CONFIG_PCIE_SLOTCTL 0x88
#define CNXK_VF_RING_OFFSET (0x1ULL << 17)
/*###################### RING IN REGISTERS #########################*/
#define CNXK_VF_SDP_R_IN_CONTROL_START 0x10000
#define CNXK_VF_SDP_R_IN_ENABLE_START 0x10010
#define CNXK_VF_SDP_R_IN_INSTR_BADDR_START 0x10020
#define CNXK_VF_SDP_R_IN_INSTR_RSIZE_START 0x10030
#define CNXK_VF_SDP_R_IN_INSTR_DBELL_START 0x10040
#define CNXK_VF_SDP_R_IN_CNTS_START 0x10050
#define CNXK_VF_SDP_R_IN_INT_LEVELS_START 0x10060
#define CNXK_VF_SDP_R_IN_PKT_CNT_START 0x10080
#define CNXK_VF_SDP_R_IN_BYTE_CNT_START 0x10090
#define CNXK_VF_SDP_R_ERR_TYPE_START 0x10400
#define CNXK_VF_SDP_R_ERR_TYPE(ring) \
(CNXK_VF_SDP_R_ERR_TYPE_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_IN_CONTROL(ring) \
(CNXK_VF_SDP_R_IN_CONTROL_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_IN_ENABLE(ring) \
(CNXK_VF_SDP_R_IN_ENABLE_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_IN_INSTR_BADDR(ring) \
(CNXK_VF_SDP_R_IN_INSTR_BADDR_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_IN_INSTR_RSIZE(ring) \
(CNXK_VF_SDP_R_IN_INSTR_RSIZE_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_IN_INSTR_DBELL(ring) \
(CNXK_VF_SDP_R_IN_INSTR_DBELL_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_IN_CNTS(ring) \
(CNXK_VF_SDP_R_IN_CNTS_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_IN_INT_LEVELS(ring) \
(CNXK_VF_SDP_R_IN_INT_LEVELS_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_IN_PKT_CNT(ring) \
(CNXK_VF_SDP_R_IN_PKT_CNT_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_IN_BYTE_CNT(ring) \
(CNXK_VF_SDP_R_IN_BYTE_CNT_START + ((ring) * CNXK_VF_RING_OFFSET))
/*------------------ R_IN Masks ----------------*/
/** Rings per Virtual Function **/
#define CNXK_VF_R_IN_CTL_RPVF_MASK (0xF)
#define CNXK_VF_R_IN_CTL_RPVF_POS (48)
/* Number of instructions to be read in one MAC read request.
* setting to Max value(4)
**/
#define CNXK_VF_R_IN_CTL_IDLE (0x1ULL << 28)
#define CNXK_VF_R_IN_CTL_RDSIZE (0x3ULL << 25)
#define CNXK_VF_R_IN_CTL_IS_64B (0x1ULL << 24)
#define CNXK_VF_R_IN_CTL_D_NSR (0x1ULL << 8)
#define CNXK_VF_R_IN_CTL_D_ESR (0x1ULL << 6)
#define CNXK_VF_R_IN_CTL_D_ROR (0x1ULL << 5)
#define CNXK_VF_R_IN_CTL_NSR (0x1ULL << 3)
#define CNXK_VF_R_IN_CTL_ESR (0x1ULL << 1)
#define CNXK_VF_R_IN_CTL_ROR (0x1ULL << 0)
#define CNXK_VF_R_IN_CTL_MASK (CNXK_VF_R_IN_CTL_RDSIZE | CNXK_VF_R_IN_CTL_IS_64B)
/*###################### RING OUT REGISTERS #########################*/
#define CNXK_VF_SDP_R_OUT_CNTS_START 0x10100
#define CNXK_VF_SDP_R_OUT_INT_LEVELS_START 0x10110
#define CNXK_VF_SDP_R_OUT_SLIST_BADDR_START 0x10120
#define CNXK_VF_SDP_R_OUT_SLIST_RSIZE_START 0x10130
#define CNXK_VF_SDP_R_OUT_SLIST_DBELL_START 0x10140
#define CNXK_VF_SDP_R_OUT_CONTROL_START 0x10150
#define CNXK_VF_SDP_R_OUT_WMARK_START 0x10160
#define CNXK_VF_SDP_R_OUT_ENABLE_START 0x10170
#define CNXK_VF_SDP_R_OUT_PKT_CNT_START 0x10180
#define CNXK_VF_SDP_R_OUT_BYTE_CNT_START 0x10190
#define CNXK_VF_SDP_R_OUT_CONTROL(ring) \
(CNXK_VF_SDP_R_OUT_CONTROL_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_OUT_ENABLE(ring) \
(CNXK_VF_SDP_R_OUT_ENABLE_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_OUT_SLIST_BADDR(ring) \
(CNXK_VF_SDP_R_OUT_SLIST_BADDR_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_OUT_SLIST_RSIZE(ring) \
(CNXK_VF_SDP_R_OUT_SLIST_RSIZE_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_OUT_SLIST_DBELL(ring) \
(CNXK_VF_SDP_R_OUT_SLIST_DBELL_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_OUT_WMARK(ring) \
(CNXK_VF_SDP_R_OUT_WMARK_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_OUT_CNTS(ring) \
(CNXK_VF_SDP_R_OUT_CNTS_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_OUT_INT_LEVELS(ring) \
(CNXK_VF_SDP_R_OUT_INT_LEVELS_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_OUT_PKT_CNT(ring) \
(CNXK_VF_SDP_R_OUT_PKT_CNT_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_OUT_BYTE_CNT(ring) \
(CNXK_VF_SDP_R_OUT_BYTE_CNT_START + ((ring) * CNXK_VF_RING_OFFSET))
/*------------------ R_OUT Masks ----------------*/
#define CNXK_VF_R_OUT_INT_LEVELS_BMODE BIT_ULL(63)
#define CNXK_VF_R_OUT_INT_LEVELS_TIMET (32)
#define CNXK_VF_R_OUT_CTL_IDLE BIT_ULL(40)
#define CNXK_VF_R_OUT_CTL_ES_I BIT_ULL(34)
#define CNXK_VF_R_OUT_CTL_NSR_I BIT_ULL(33)
#define CNXK_VF_R_OUT_CTL_ROR_I BIT_ULL(32)
#define CNXK_VF_R_OUT_CTL_ES_D BIT_ULL(30)
#define CNXK_VF_R_OUT_CTL_NSR_D BIT_ULL(29)
#define CNXK_VF_R_OUT_CTL_ROR_D BIT_ULL(28)
#define CNXK_VF_R_OUT_CTL_ES_P BIT_ULL(26)
#define CNXK_VF_R_OUT_CTL_NSR_P BIT_ULL(25)
#define CNXK_VF_R_OUT_CTL_ROR_P BIT_ULL(24)
#define CNXK_VF_R_OUT_CTL_IMODE BIT_ULL(23)
/* ##################### Mail Box Registers ########################## */
/* SDP PF to VF Mailbox Data Register */
#define CNXK_VF_SDP_R_MBOX_PF_VF_DATA_START 0x10210
/* SDP Packet PF to VF Mailbox Interrupt Register */
#define CNXK_VF_SDP_R_MBOX_PF_VF_INT_START 0x10220
/* SDP VF to PF Mailbox Data Register */
#define CNXK_VF_SDP_R_MBOX_VF_PF_DATA_START 0x10230
#define CNXK_VF_SDP_R_MBOX_PF_VF_INT_ENAB BIT_ULL(1)
#define CNXK_VF_SDP_R_MBOX_PF_VF_INT_STATUS BIT_ULL(0)
#define CNXK_VF_SDP_R_MBOX_PF_VF_DATA(ring) \
(CNXK_VF_SDP_R_MBOX_PF_VF_DATA_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_MBOX_PF_VF_INT(ring) \
(CNXK_VF_SDP_R_MBOX_PF_VF_INT_START + ((ring) * CNXK_VF_RING_OFFSET))
#define CNXK_VF_SDP_R_MBOX_VF_PF_DATA(ring) \
(CNXK_VF_SDP_R_MBOX_VF_PF_DATA_START + ((ring) * CNXK_VF_RING_OFFSET))
#endif /* _OCTEP_VF_REGS_CNXK_H_ */
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.h deleted 100644 → 0
View file @ 5e5401d6
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell Octeon EP (EndPoint) VF Ethernet Driver
*
* Copyright (C) 2020 Marvell.
*
*/
#ifndef _OCTEP_VF_RX_H_
#define _OCTEP_VF_RX_H_
/* struct octep_vf_oq_desc_hw - Octeon Hardware OQ descriptor format.
*
* The descriptor ring is made of descriptors which have 2 64-bit values:
*
* @buffer_ptr: DMA address of the skb->data
* @info_ptr: DMA address of host memory, used to update pkt count by hw.
* This is currently unused to save pci writes.
*/
struct octep_vf_oq_desc_hw {
dma_addr_t buffer_ptr;
u64 info_ptr;
};
static_assert(sizeof(struct octep_vf_oq_desc_hw) == 16);
#define OCTEP_VF_OQ_DESC_SIZE (sizeof(struct octep_vf_oq_desc_hw))
/* Rx offload flags */
#define OCTEP_VF_RX_OFFLOAD_VLAN_STRIP BIT(0)
#define OCTEP_VF_RX_OFFLOAD_IPV4_CKSUM BIT(1)
#define OCTEP_VF_RX_OFFLOAD_UDP_CKSUM BIT(2)
#define OCTEP_VF_RX_OFFLOAD_TCP_CKSUM BIT(3)
#define OCTEP_VF_RX_OFFLOAD_CKSUM (OCTEP_VF_RX_OFFLOAD_IPV4_CKSUM | \
OCTEP_VF_RX_OFFLOAD_UDP_CKSUM | \
OCTEP_VF_RX_OFFLOAD_TCP_CKSUM)
#define OCTEP_VF_RX_IP_CSUM(flags) ((flags) & \
(OCTEP_VF_RX_OFFLOAD_IPV4_CKSUM | \
OCTEP_VF_RX_OFFLOAD_TCP_CKSUM | \
OCTEP_VF_RX_OFFLOAD_UDP_CKSUM))
/* bit 0 is vlan strip */
#define OCTEP_VF_RX_CSUM_IP_VERIFIED BIT(1)
#define OCTEP_VF_RX_CSUM_L4_VERIFIED BIT(2)
#define OCTEP_VF_RX_CSUM_VERIFIED(flags) ((flags) & \
(OCTEP_VF_RX_CSUM_L4_VERIFIED | \
OCTEP_VF_RX_CSUM_IP_VERIFIED))
/* Extended Response Header in packet data received from Hardware.
* Includes metadata like checksum status.
* this is valid only if hardware/firmware published support for this.
* This is at offset 0 of packet data (skb->data).
*/
struct octep_vf_oq_resp_hw_ext {
/* Reserved. */
u64 rsvd:48;
/* rx offload flags */
u16 rx_ol_flags;
};
static_assert(sizeof(struct octep_vf_oq_resp_hw_ext) == 8);
#define OCTEP_VF_OQ_RESP_HW_EXT_SIZE (sizeof(struct octep_vf_oq_resp_hw_ext))
/* Length of Rx packet DMA'ed by Octeon to Host.
* this is in bigendian; so need to be converted to cpu endian.
* Octeon writes this at the beginning of Rx buffer (skb->data).
*/
struct octep_vf_oq_resp_hw {
/* The Length of the packet. */
__be64 length;
};
static_assert(sizeof(struct octep_vf_oq_resp_hw) == 8);
#define OCTEP_VF_OQ_RESP_HW_SIZE (sizeof(struct octep_vf_oq_resp_hw))
/* Pointer to data buffer.
* Driver keeps a pointer to the data buffer that it made available to
* the Octeon device. Since the descriptor ring keeps physical (bus)
* addresses, this field is required for the driver to keep track of
* the virtual address pointers. The fields are operated by
* OS-dependent routines.
*/
struct octep_vf_rx_buffer {
struct page *page;
/* length from rx hardware descriptor after converting to cpu endian */
u64 len;
};
#define OCTEP_VF_OQ_RECVBUF_SIZE (sizeof(struct octep_vf_rx_buffer))
/* Output Queue statistics. Each output queue has four stats fields. */
struct octep_vf_oq_stats {
/* Number of packets received from the Device. */
u64 packets;
/* Number of bytes received from the Device. */
u64 bytes;
/* Number of times failed to allocate buffers. */
u64 alloc_failures;
};
#define OCTEP_VF_OQ_STATS_SIZE (sizeof(struct octep_vf_oq_stats))
/* Hardware interface Rx statistics */
struct octep_vf_iface_rx_stats {
/* Received packets */
u64 pkts;
/* Octets of received packets */
u64 octets;
/* Received PAUSE and Control packets */
u64 pause_pkts;
/* Received PAUSE and Control octets */
u64 pause_octets;
/* Filtered DMAC0 packets */
u64 dmac0_pkts;
/* Filtered DMAC0 octets */
u64 dmac0_octets;
/* Packets dropped due to RX FIFO full */
u64 dropped_pkts_fifo_full;
/* Octets dropped due to RX FIFO full */
u64 dropped_octets_fifo_full;
/* Error packets */
u64 err_pkts;
/* Filtered DMAC1 packets */
u64 dmac1_pkts;
/* Filtered DMAC1 octets */
u64 dmac1_octets;
/* NCSI-bound packets dropped */
u64 ncsi_dropped_pkts;
/* NCSI-bound octets dropped */
u64 ncsi_dropped_octets;
/* Multicast packets received. */
u64 mcast_pkts;
/* Broadcast packets received. */
u64 bcast_pkts;
};
/* The Descriptor Ring Output Queue structure.
* This structure has all the information required to implement a
* Octeon OQ.
*/
struct octep_vf_oq {
u32 q_no;
struct octep_vf_device *octep_vf_dev;
struct net_device *netdev;
struct device *dev;
struct napi_struct *napi;
/* The receive buffer list. This list has the virtual addresses
* of the buffers.
*/
struct octep_vf_rx_buffer *buff_info;
/* Pointer to the mapped packet credit register.
* Host writes number of info/buffer ptrs available to this register
*/
u8 __iomem *pkts_credit_reg;
/* Pointer to the mapped packet sent register.
* Octeon writes the number of packets DMA'ed to host memory
* in this register.
*/
u8 __iomem *pkts_sent_reg;
/* Statistics for this OQ. */
struct octep_vf_oq_stats stats;
/* Packets pending to be processed */
u32 pkts_pending;
u32 last_pkt_count;
/* Index in the ring where the driver should read the next packet */
u32 host_read_idx;
/* Number of descriptors in this ring. */
u32 max_count;
u32 ring_size_mask;
/* The number of descriptors pending refill. */
u32 refill_count;
/* Index in the ring where the driver will refill the
* descriptor's buffer
*/
u32 host_refill_idx;
u32 refill_threshold;
/* The size of each buffer pointed by the buffer pointer. */
u32 buffer_size;
u32 max_single_buffer_size;
/* The 8B aligned descriptor ring starts at this address. */
struct octep_vf_oq_desc_hw *desc_ring;
/* DMA mapped address of the OQ descriptor ring. */
dma_addr_t desc_ring_dma;
};
#define OCTEP_VF_OQ_SIZE (sizeof(struct octep_vf_oq))
#endif /* _OCTEP_VF_RX_H_ */
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