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Commit 648a8e34 authored by Alan Cox's avatar Alan Cox Committed by Dave Airlie
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gma500: now move the Oaktrail save state into its own structure 

Signed-off-by: default avatarAlan Cox <alan@linux.intel.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 933315ac
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Showing with 322 additions and 296 deletions
drivers/gpu/drm/gma500/cdv_intel_display.c
View file @ 648a8e34
......@@ -968,7 +968,7 @@ void cdv_intel_crtc_load_lut(struct drm_crtc *crtc)
gma_power_end(dev);
} else {
for (i = 0; i < 256; i++) {
dev_priv->save_palette_a[i] =
dev_priv->regs.save_palette_a[i] =
((psb_intel_crtc->lut_r[i] +
psb_intel_crtc->lut_adj[i]) << 16) |
((psb_intel_crtc->lut_g[i] +
......@@ -1338,18 +1338,19 @@ static int cdv_intel_crtc_clock_get(struct drm_device *dev,
gma_power_end(dev);
} else {
dpll = (pipe == 0) ?
dev_priv->saveDPLL_A : dev_priv->saveDPLL_B;
dev_priv->regs.saveDPLL_A : dev_priv->regs.saveDPLL_B;
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
fp = (pipe == 0) ?
dev_priv->saveFPA0 :
dev_priv->saveFPB0;
dev_priv->regs.saveFPA0 :
dev_priv->regs.saveFPB0;
else
fp = (pipe == 0) ?
dev_priv->saveFPA1 :
dev_priv->saveFPB1;
dev_priv->regs.saveFPA1 :
dev_priv->regs.saveFPB1;
is_lvds = (pipe == 1) && (dev_priv->saveLVDS & LVDS_PORT_EN);
is_lvds = (pipe == 1) &&
(dev_priv->regs.saveLVDS & LVDS_PORT_EN);
}
clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
......@@ -1419,13 +1420,17 @@ struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
gma_power_end(dev);
} else {
htot = (pipe == 0) ?
dev_priv->saveHTOTAL_A : dev_priv->saveHTOTAL_B;
dev_priv->regs.saveHTOTAL_A :
dev_priv->regs.saveHTOTAL_B;
hsync = (pipe == 0) ?
dev_priv->saveHSYNC_A : dev_priv->saveHSYNC_B;
dev_priv->regs.saveHSYNC_A :
dev_priv->regs.saveHSYNC_B;
vtot = (pipe == 0) ?
dev_priv->saveVTOTAL_A : dev_priv->saveVTOTAL_B;
dev_priv->regs.saveVTOTAL_A :
dev_priv->regs.saveVTOTAL_B;
vsync = (pipe == 0) ?
dev_priv->saveVSYNC_A : dev_priv->saveVSYNC_B;
dev_priv->regs.saveVSYNC_A :
dev_priv->regs.saveVSYNC_B;
}
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
......
drivers/gpu/drm/gma500/cdv_intel_lvds.c
View file @ 648a8e34
......@@ -78,7 +78,7 @@ static u32 cdv_intel_lvds_get_max_backlight(struct drm_device *dev)
gma_power_end(dev);
} else
retval = ((dev_priv->saveBLC_PWM_CTL &
retval = ((dev_priv->regs.saveBLC_PWM_CTL &
BACKLIGHT_MODULATION_FREQ_MASK) >>
BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
......@@ -184,9 +184,9 @@ static void cdv_intel_lvds_set_backlight(struct drm_device *dev, int level)
(level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
gma_power_end(dev);
} else {
blc_pwm_ctl = dev_priv->saveBLC_PWM_CTL &
blc_pwm_ctl = dev_priv->regs.saveBLC_PWM_CTL &
~BACKLIGHT_DUTY_CYCLE_MASK;
dev_priv->saveBLC_PWM_CTL = (blc_pwm_ctl |
dev_priv->regs.saveBLC_PWM_CTL = (blc_pwm_ctl |
(level << BACKLIGHT_DUTY_CYCLE_SHIFT));
}
}
......
drivers/gpu/drm/gma500/oaktrail_device.c
View file @ 648a8e34
This diff is collapsed.
drivers/gpu/drm/gma500/oaktrail_hdmi.c
View file @ 648a8e34
......@@ -766,6 +766,7 @@ void oaktrail_hdmi_save(struct drm_device *dev)
{
struct drm_psb_private *dev_priv = dev->dev_private;
struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
struct psb_state *regs = &dev_priv->regs;
int i;
/* dpll */
......@@ -776,14 +777,14 @@ void oaktrail_hdmi_save(struct drm_device *dev)
hdmi_dev->saveDPLL_CLK_ENABLE = PSB_RVDC32(DPLL_CLK_ENABLE);
/* pipe B */
dev_priv->savePIPEBCONF = PSB_RVDC32(PIPEBCONF);
dev_priv->savePIPEBSRC = PSB_RVDC32(PIPEBSRC);
dev_priv->saveHTOTAL_B = PSB_RVDC32(HTOTAL_B);
dev_priv->saveHBLANK_B = PSB_RVDC32(HBLANK_B);
dev_priv->saveHSYNC_B = PSB_RVDC32(HSYNC_B);
dev_priv->saveVTOTAL_B = PSB_RVDC32(VTOTAL_B);
dev_priv->saveVBLANK_B = PSB_RVDC32(VBLANK_B);
dev_priv->saveVSYNC_B = PSB_RVDC32(VSYNC_B);
regs->savePIPEBCONF = PSB_RVDC32(PIPEBCONF);
regs->savePIPEBSRC = PSB_RVDC32(PIPEBSRC);
regs->saveHTOTAL_B = PSB_RVDC32(HTOTAL_B);
regs->saveHBLANK_B = PSB_RVDC32(HBLANK_B);
regs->saveHSYNC_B = PSB_RVDC32(HSYNC_B);
regs->saveVTOTAL_B = PSB_RVDC32(VTOTAL_B);
regs->saveVBLANK_B = PSB_RVDC32(VBLANK_B);
regs->saveVSYNC_B = PSB_RVDC32(VSYNC_B);
hdmi_dev->savePCH_PIPEBCONF = PSB_RVDC32(PCH_PIPEBCONF);
hdmi_dev->savePCH_PIPEBSRC = PSB_RVDC32(PCH_PIPEBSRC);
......@@ -795,21 +796,21 @@ void oaktrail_hdmi_save(struct drm_device *dev)
hdmi_dev->savePCH_VSYNC_B = PSB_RVDC32(PCH_VSYNC_B);
/* plane */
dev_priv->saveDSPBCNTR = PSB_RVDC32(DSPBCNTR);
dev_priv->saveDSPBSTRIDE = PSB_RVDC32(DSPBSTRIDE);
dev_priv->saveDSPBADDR = PSB_RVDC32(DSPBBASE);
dev_priv->saveDSPBSURF = PSB_RVDC32(DSPBSURF);
dev_priv->saveDSPBLINOFF = PSB_RVDC32(DSPBLINOFF);
dev_priv->saveDSPBTILEOFF = PSB_RVDC32(DSPBTILEOFF);
regs->saveDSPBCNTR = PSB_RVDC32(DSPBCNTR);
regs->saveDSPBSTRIDE = PSB_RVDC32(DSPBSTRIDE);
regs->saveDSPBADDR = PSB_RVDC32(DSPBBASE);
regs->saveDSPBSURF = PSB_RVDC32(DSPBSURF);
regs->saveDSPBLINOFF = PSB_RVDC32(DSPBLINOFF);
regs->saveDSPBTILEOFF = PSB_RVDC32(DSPBTILEOFF);
/* cursor B */
dev_priv->saveDSPBCURSOR_CTRL = PSB_RVDC32(CURBCNTR);
dev_priv->saveDSPBCURSOR_BASE = PSB_RVDC32(CURBBASE);
dev_priv->saveDSPBCURSOR_POS = PSB_RVDC32(CURBPOS);
regs->saveDSPBCURSOR_CTRL = PSB_RVDC32(CURBCNTR);
regs->saveDSPBCURSOR_BASE = PSB_RVDC32(CURBBASE);
regs->saveDSPBCURSOR_POS = PSB_RVDC32(CURBPOS);
/* save palette */
for (i = 0; i < 256; i++)
dev_priv->save_palette_b[i] = PSB_RVDC32(PALETTE_B + (i << 2));
regs->save_palette_b[i] = PSB_RVDC32(PALETTE_B + (i << 2));
}
/* restore HDMI register state */
......@@ -817,6 +818,7 @@ void oaktrail_hdmi_restore(struct drm_device *dev)
{
struct drm_psb_private *dev_priv = dev->dev_private;
struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
struct psb_state *regs = &dev_priv->regs;
int i;
/* dpll */
......@@ -828,13 +830,13 @@ void oaktrail_hdmi_restore(struct drm_device *dev)
DRM_UDELAY(150);
/* pipe */
PSB_WVDC32(dev_priv->savePIPEBSRC, PIPEBSRC);
PSB_WVDC32(dev_priv->saveHTOTAL_B, HTOTAL_B);
PSB_WVDC32(dev_priv->saveHBLANK_B, HBLANK_B);
PSB_WVDC32(dev_priv->saveHSYNC_B, HSYNC_B);
PSB_WVDC32(dev_priv->saveVTOTAL_B, VTOTAL_B);
PSB_WVDC32(dev_priv->saveVBLANK_B, VBLANK_B);
PSB_WVDC32(dev_priv->saveVSYNC_B, VSYNC_B);
PSB_WVDC32(regs->savePIPEBSRC, PIPEBSRC);
PSB_WVDC32(regs->saveHTOTAL_B, HTOTAL_B);
PSB_WVDC32(regs->saveHBLANK_B, HBLANK_B);
PSB_WVDC32(regs->saveHSYNC_B, HSYNC_B);
PSB_WVDC32(regs->saveVTOTAL_B, VTOTAL_B);
PSB_WVDC32(regs->saveVBLANK_B, VBLANK_B);
PSB_WVDC32(regs->saveVSYNC_B, VSYNC_B);
PSB_WVDC32(hdmi_dev->savePCH_PIPEBSRC, PCH_PIPEBSRC);
PSB_WVDC32(hdmi_dev->savePCH_HTOTAL_B, PCH_HTOTAL_B);
......@@ -844,22 +846,22 @@ void oaktrail_hdmi_restore(struct drm_device *dev)
PSB_WVDC32(hdmi_dev->savePCH_VBLANK_B, PCH_VBLANK_B);
PSB_WVDC32(hdmi_dev->savePCH_VSYNC_B, PCH_VSYNC_B);
PSB_WVDC32(dev_priv->savePIPEBCONF, PIPEBCONF);
PSB_WVDC32(regs->savePIPEBCONF, PIPEBCONF);
PSB_WVDC32(hdmi_dev->savePCH_PIPEBCONF, PCH_PIPEBCONF);
/* plane */
PSB_WVDC32(dev_priv->saveDSPBLINOFF, DSPBLINOFF);
PSB_WVDC32(dev_priv->saveDSPBSTRIDE, DSPBSTRIDE);
PSB_WVDC32(dev_priv->saveDSPBTILEOFF, DSPBTILEOFF);
PSB_WVDC32(dev_priv->saveDSPBCNTR, DSPBCNTR);
PSB_WVDC32(dev_priv->saveDSPBSURF, DSPBSURF);
PSB_WVDC32(regs->saveDSPBLINOFF, DSPBLINOFF);
PSB_WVDC32(regs->saveDSPBSTRIDE, DSPBSTRIDE);
PSB_WVDC32(regs->saveDSPBTILEOFF, DSPBTILEOFF);
PSB_WVDC32(regs->saveDSPBCNTR, DSPBCNTR);
PSB_WVDC32(regs->saveDSPBSURF, DSPBSURF);
/* cursor B */
PSB_WVDC32(dev_priv->saveDSPBCURSOR_CTRL, CURBCNTR);
PSB_WVDC32(dev_priv->saveDSPBCURSOR_POS, CURBPOS);
PSB_WVDC32(dev_priv->saveDSPBCURSOR_BASE, CURBBASE);
PSB_WVDC32(regs->saveDSPBCURSOR_CTRL, CURBCNTR);
PSB_WVDC32(regs->saveDSPBCURSOR_POS, CURBPOS);
PSB_WVDC32(regs->saveDSPBCURSOR_BASE, CURBBASE);
/* restore palette */
for (i = 0; i < 256; i++)
PSB_WVDC32(dev_priv->save_palette_b[i], PALETTE_B + (i << 2));
PSB_WVDC32(regs->save_palette_b[i], PALETTE_B + (i << 2));
}
drivers/gpu/drm/gma500/oaktrail_lvds.c
View file @ 648a8e34
......@@ -192,7 +192,7 @@ static u32 oaktrail_lvds_get_max_backlight(struct drm_device *dev)
gma_power_end(dev);
} else
ret = ((dev_priv->saveBLC_PWM_CTL &
ret = ((dev_priv->regs.saveBLC_PWM_CTL &
BACKLIGHT_MODULATION_FREQ_MASK) >>
BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
......
drivers/gpu/drm/gma500/power.c
View file @ 648a8e34
......@@ -132,9 +132,9 @@ static void gma_suspend_pci(struct pci_dev *pdev)
pci_save_state(pdev);
pci_read_config_dword(pdev, 0x5C, &bsm);
dev_priv->saveBSM = bsm;
dev_priv->regs.saveBSM = bsm;
pci_read_config_dword(pdev, 0xFC, &vbt);
dev_priv->saveVBT = vbt;
dev_priv->regs.saveVBT = vbt;
pci_read_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, &dev_priv->msi_addr);
pci_read_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, &dev_priv->msi_data);
......@@ -162,8 +162,8 @@ static bool gma_resume_pci(struct pci_dev *pdev)
pci_set_power_state(pdev, PCI_D0);
pci_restore_state(pdev);
pci_write_config_dword(pdev, 0x5c, dev_priv->saveBSM);
pci_write_config_dword(pdev, 0xFC, dev_priv->saveVBT);
pci_write_config_dword(pdev, 0x5c, dev_priv->regs.saveBSM);
pci_write_config_dword(pdev, 0xFC, dev_priv->regs.saveVBT);
/* restoring MSI address and data in PCIx space */
pci_write_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, dev_priv->msi_addr);
pci_write_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, dev_priv->msi_data);
......
drivers/gpu/drm/gma500/psb_device.c
View file @ 648a8e34
......@@ -177,16 +177,17 @@ static int psb_save_display_registers(struct drm_device *dev)
struct drm_psb_private *dev_priv = dev->dev_private;
struct drm_crtc *crtc;
struct drm_connector *connector;
struct psb_state *regs = &dev_priv->regs;
/* Display arbitration control + watermarks */
dev_priv->saveDSPARB = PSB_RVDC32(DSPARB);
dev_priv->saveDSPFW1 = PSB_RVDC32(DSPFW1);
dev_priv->saveDSPFW2 = PSB_RVDC32(DSPFW2);
dev_priv->saveDSPFW3 = PSB_RVDC32(DSPFW3);
dev_priv->saveDSPFW4 = PSB_RVDC32(DSPFW4);
dev_priv->saveDSPFW5 = PSB_RVDC32(DSPFW5);
dev_priv->saveDSPFW6 = PSB_RVDC32(DSPFW6);
dev_priv->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
regs->saveDSPARB = PSB_RVDC32(DSPARB);
regs->saveDSPFW1 = PSB_RVDC32(DSPFW1);
regs->saveDSPFW2 = PSB_RVDC32(DSPFW2);
regs->saveDSPFW3 = PSB_RVDC32(DSPFW3);
regs->saveDSPFW4 = PSB_RVDC32(DSPFW4);
regs->saveDSPFW5 = PSB_RVDC32(DSPFW5);
regs->saveDSPFW6 = PSB_RVDC32(DSPFW6);
regs->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
/* Save crtc and output state */
mutex_lock(&dev->mode_config.mutex);
......@@ -213,16 +214,17 @@ static int psb_restore_display_registers(struct drm_device *dev)
struct drm_psb_private *dev_priv = dev->dev_private;
struct drm_crtc *crtc;
struct drm_connector *connector;
struct psb_state *regs = &dev_priv->regs;
/* Display arbitration + watermarks */
PSB_WVDC32(dev_priv->saveDSPARB, DSPARB);
PSB_WVDC32(dev_priv->saveDSPFW1, DSPFW1);
PSB_WVDC32(dev_priv->saveDSPFW2, DSPFW2);
PSB_WVDC32(dev_priv->saveDSPFW3, DSPFW3);
PSB_WVDC32(dev_priv->saveDSPFW4, DSPFW4);
PSB_WVDC32(dev_priv->saveDSPFW5, DSPFW5);
PSB_WVDC32(dev_priv->saveDSPFW6, DSPFW6);
PSB_WVDC32(dev_priv->saveCHICKENBIT, DSPCHICKENBIT);
PSB_WVDC32(regs->saveDSPARB, DSPARB);
PSB_WVDC32(regs->saveDSPFW1, DSPFW1);
PSB_WVDC32(regs->saveDSPFW2, DSPFW2);
PSB_WVDC32(regs->saveDSPFW3, DSPFW3);
PSB_WVDC32(regs->saveDSPFW4, DSPFW4);
PSB_WVDC32(regs->saveDSPFW5, DSPFW5);
PSB_WVDC32(regs->saveDSPFW6, DSPFW6);
PSB_WVDC32(regs->saveCHICKENBIT, DSPCHICKENBIT);
/*make sure VGA plane is off. it initializes to on after reset!*/
PSB_WVDC32(0x80000000, VGACNTRL);
......
drivers/gpu/drm/gma500/psb_drv.h
View file @ 648a8e34
......@@ -276,6 +276,123 @@ struct intel_gmbus {
u32 reg0;
};
/*
* Register save state. This is used to hold the context when the
* device is powered off. In the case of Oaktrail this can (but does not
* yet) include screen blank. Operations occuring during the save
* update the register cache instead.
*/
struct psb_state {
uint32_t saveDSPACNTR;
uint32_t saveDSPBCNTR;
uint32_t savePIPEACONF;
uint32_t savePIPEBCONF;
uint32_t savePIPEASRC;
uint32_t savePIPEBSRC;
uint32_t saveFPA0;
uint32_t saveFPA1;
uint32_t saveDPLL_A;
uint32_t saveDPLL_A_MD;
uint32_t saveHTOTAL_A;
uint32_t saveHBLANK_A;
uint32_t saveHSYNC_A;
uint32_t saveVTOTAL_A;
uint32_t saveVBLANK_A;
uint32_t saveVSYNC_A;
uint32_t saveDSPASTRIDE;
uint32_t saveDSPASIZE;
uint32_t saveDSPAPOS;
uint32_t saveDSPABASE;
uint32_t saveDSPASURF;
uint32_t saveDSPASTATUS;
uint32_t saveFPB0;
uint32_t saveFPB1;
uint32_t saveDPLL_B;
uint32_t saveDPLL_B_MD;
uint32_t saveHTOTAL_B;
uint32_t saveHBLANK_B;
uint32_t saveHSYNC_B;
uint32_t saveVTOTAL_B;
uint32_t saveVBLANK_B;
uint32_t saveVSYNC_B;
uint32_t saveDSPBSTRIDE;
uint32_t saveDSPBSIZE;
uint32_t saveDSPBPOS;
uint32_t saveDSPBBASE;
uint32_t saveDSPBSURF;
uint32_t saveDSPBSTATUS;
uint32_t saveVCLK_DIVISOR_VGA0;
uint32_t saveVCLK_DIVISOR_VGA1;
uint32_t saveVCLK_POST_DIV;
uint32_t saveVGACNTRL;
uint32_t saveADPA;
uint32_t saveLVDS;
uint32_t saveDVOA;
uint32_t saveDVOB;
uint32_t saveDVOC;
uint32_t savePP_ON;
uint32_t savePP_OFF;
uint32_t savePP_CONTROL;
uint32_t savePP_CYCLE;
uint32_t savePFIT_CONTROL;
uint32_t savePaletteA[256];
uint32_t savePaletteB[256];
uint32_t saveBLC_PWM_CTL2;
uint32_t saveBLC_PWM_CTL;
uint32_t saveCLOCKGATING;
uint32_t saveDSPARB;
uint32_t saveDSPATILEOFF;
uint32_t saveDSPBTILEOFF;
uint32_t saveDSPAADDR;
uint32_t saveDSPBADDR;
uint32_t savePFIT_AUTO_RATIOS;
uint32_t savePFIT_PGM_RATIOS;
uint32_t savePP_ON_DELAYS;
uint32_t savePP_OFF_DELAYS;
uint32_t savePP_DIVISOR;
uint32_t saveBSM;
uint32_t saveVBT;
uint32_t saveBCLRPAT_A;
uint32_t saveBCLRPAT_B;
uint32_t saveDSPALINOFF;
uint32_t saveDSPBLINOFF;
uint32_t savePERF_MODE;
uint32_t saveDSPFW1;
uint32_t saveDSPFW2;
uint32_t saveDSPFW3;
uint32_t saveDSPFW4;
uint32_t saveDSPFW5;
uint32_t saveDSPFW6;
uint32_t saveCHICKENBIT;
uint32_t saveDSPACURSOR_CTRL;
uint32_t saveDSPBCURSOR_CTRL;
uint32_t saveDSPACURSOR_BASE;
uint32_t saveDSPBCURSOR_BASE;
uint32_t saveDSPACURSOR_POS;
uint32_t saveDSPBCURSOR_POS;
uint32_t save_palette_a[256];
uint32_t save_palette_b[256];
uint32_t saveOV_OVADD;
uint32_t saveOV_OGAMC0;
uint32_t saveOV_OGAMC1;
uint32_t saveOV_OGAMC2;
uint32_t saveOV_OGAMC3;
uint32_t saveOV_OGAMC4;
uint32_t saveOV_OGAMC5;
uint32_t saveOVC_OVADD;
uint32_t saveOVC_OGAMC0;
uint32_t saveOVC_OGAMC1;
uint32_t saveOVC_OGAMC2;
uint32_t saveOVC_OGAMC3;
uint32_t saveOVC_OGAMC4;
uint32_t saveOVC_OGAMC5;
/* DPST register save */
uint32_t saveHISTOGRAM_INT_CONTROL_REG;
uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
uint32_t savePWM_CONTROL_LOGIC;
};
struct psb_ops;
#define PSB_NUM_PIPE 3
......@@ -403,118 +520,11 @@ struct drm_psb_private {
/*
* Register state
*/
uint32_t saveDSPACNTR;
uint32_t saveDSPBCNTR;
uint32_t savePIPEACONF;
uint32_t savePIPEBCONF;
uint32_t savePIPEASRC;
uint32_t savePIPEBSRC;
uint32_t saveFPA0;
uint32_t saveFPA1;
uint32_t saveDPLL_A;
uint32_t saveDPLL_A_MD;
uint32_t saveHTOTAL_A;
uint32_t saveHBLANK_A;
uint32_t saveHSYNC_A;
uint32_t saveVTOTAL_A;
uint32_t saveVBLANK_A;
uint32_t saveVSYNC_A;
uint32_t saveDSPASTRIDE;
uint32_t saveDSPASIZE;
uint32_t saveDSPAPOS;
uint32_t saveDSPABASE;
uint32_t saveDSPASURF;
uint32_t saveDSPASTATUS;
uint32_t saveFPB0;
uint32_t saveFPB1;
uint32_t saveDPLL_B;
uint32_t saveDPLL_B_MD;
uint32_t saveHTOTAL_B;
uint32_t saveHBLANK_B;
uint32_t saveHSYNC_B;
uint32_t saveVTOTAL_B;
uint32_t saveVBLANK_B;
uint32_t saveVSYNC_B;
uint32_t saveDSPBSTRIDE;
uint32_t saveDSPBSIZE;
uint32_t saveDSPBPOS;
uint32_t saveDSPBBASE;
uint32_t saveDSPBSURF;
uint32_t saveDSPBSTATUS;
uint32_t saveVCLK_DIVISOR_VGA0;
uint32_t saveVCLK_DIVISOR_VGA1;
uint32_t saveVCLK_POST_DIV;
uint32_t saveVGACNTRL;
uint32_t saveADPA;
uint32_t saveLVDS;
uint32_t saveDVOA;
uint32_t saveDVOB;
uint32_t saveDVOC;
uint32_t savePP_ON;
uint32_t savePP_OFF;
uint32_t savePP_CONTROL;
uint32_t savePP_CYCLE;
uint32_t savePFIT_CONTROL;
uint32_t savePaletteA[256];
uint32_t savePaletteB[256];
uint32_t saveBLC_PWM_CTL2;
uint32_t saveBLC_PWM_CTL;
uint32_t saveCLOCKGATING;
uint32_t saveDSPARB;
uint32_t saveDSPATILEOFF;
uint32_t saveDSPBTILEOFF;
uint32_t saveDSPAADDR;
uint32_t saveDSPBADDR;
uint32_t savePFIT_AUTO_RATIOS;
uint32_t savePFIT_PGM_RATIOS;
uint32_t savePP_ON_DELAYS;
uint32_t savePP_OFF_DELAYS;
uint32_t savePP_DIVISOR;
uint32_t saveBSM;
uint32_t saveVBT;
uint32_t saveBCLRPAT_A;
uint32_t saveBCLRPAT_B;
uint32_t saveDSPALINOFF;
uint32_t saveDSPBLINOFF;
uint32_t savePERF_MODE;
uint32_t saveDSPFW1;
uint32_t saveDSPFW2;
uint32_t saveDSPFW3;
uint32_t saveDSPFW4;
uint32_t saveDSPFW5;
uint32_t saveDSPFW6;
uint32_t saveCHICKENBIT;
uint32_t saveDSPACURSOR_CTRL;
uint32_t saveDSPBCURSOR_CTRL;
uint32_t saveDSPACURSOR_BASE;
uint32_t saveDSPBCURSOR_BASE;
uint32_t saveDSPACURSOR_POS;
uint32_t saveDSPBCURSOR_POS;
uint32_t save_palette_a[256];
uint32_t save_palette_b[256];
uint32_t saveOV_OVADD;
uint32_t saveOV_OGAMC0;
uint32_t saveOV_OGAMC1;
uint32_t saveOV_OGAMC2;
uint32_t saveOV_OGAMC3;
uint32_t saveOV_OGAMC4;
uint32_t saveOV_OGAMC5;
uint32_t saveOVC_OVADD;
uint32_t saveOVC_OGAMC0;
uint32_t saveOVC_OGAMC1;
uint32_t saveOVC_OGAMC2;
uint32_t saveOVC_OGAMC3;
uint32_t saveOVC_OGAMC4;
uint32_t saveOVC_OGAMC5;
struct psb_state regs;
/* MSI reg save */
uint32_t msi_addr;
uint32_t msi_data;
/* DPST register save */
uint32_t saveHISTOGRAM_INT_CONTROL_REG;
uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
uint32_t savePWM_CONTROL_LOGIC;
/*
* LID-Switch
......
drivers/gpu/drm/gma500/psb_intel_display.c
View file @ 648a8e34
......@@ -845,7 +845,7 @@ void psb_intel_crtc_load_lut(struct drm_crtc *crtc)
gma_power_end(dev);
} else {
for (i = 0; i < 256; i++) {
dev_priv->save_palette_a[i] =
dev_priv->regs.save_palette_a[i] =
((psb_intel_crtc->lut_r[i] +
psb_intel_crtc->lut_adj[i]) << 16) |
((psb_intel_crtc->lut_g[i] +
......@@ -1141,18 +1141,19 @@ static int psb_intel_crtc_clock_get(struct drm_device *dev,
gma_power_end(dev);
} else {
dpll = (pipe == 0) ?
dev_priv->saveDPLL_A : dev_priv->saveDPLL_B;
dev_priv->regs.saveDPLL_A : dev_priv->regs.saveDPLL_B;
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
fp = (pipe == 0) ?
dev_priv->saveFPA0 :
dev_priv->saveFPB0;
dev_priv->regs.saveFPA0 :
dev_priv->regs.saveFPB0;
else
fp = (pipe == 0) ?
dev_priv->saveFPA1 :
dev_priv->saveFPB1;
dev_priv->regs.saveFPA1 :
dev_priv->regs.saveFPB1;
is_lvds = (pipe == 1) && (dev_priv->saveLVDS & LVDS_PORT_EN);
is_lvds = (pipe == 1) && (dev_priv->regs.saveLVDS &
LVDS_PORT_EN);
}
clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
......@@ -1218,13 +1219,17 @@ struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
gma_power_end(dev);
} else {
htot = (pipe == 0) ?
dev_priv->saveHTOTAL_A : dev_priv->saveHTOTAL_B;
dev_priv->regs.saveHTOTAL_A :
dev_priv->regs.saveHTOTAL_B;
hsync = (pipe == 0) ?
dev_priv->saveHSYNC_A : dev_priv->saveHSYNC_B;
dev_priv->regs.saveHSYNC_A :
dev_priv->regs.saveHSYNC_B;
vtot = (pipe == 0) ?
dev_priv->saveVTOTAL_A : dev_priv->saveVTOTAL_B;
dev_priv->regs.saveVTOTAL_A :
dev_priv->regs.saveVTOTAL_B;
vsync = (pipe == 0) ?
dev_priv->saveVSYNC_A : dev_priv->saveVSYNC_B;
dev_priv->regs.saveVSYNC_A :
dev_priv->regs.saveVSYNC_B;
}
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
......
drivers/gpu/drm/gma500/psb_intel_lvds.c
View file @ 648a8e34
......@@ -77,7 +77,7 @@ static u32 psb_intel_lvds_get_max_backlight(struct drm_device *dev)
ret = REG_READ(BLC_PWM_CTL);
gma_power_end(dev);
} else /* Powered off, use the saved value */
ret = dev_priv->saveBLC_PWM_CTL;
ret = dev_priv->regs.saveBLC_PWM_CTL;
/* Top 15bits hold the frequency mask */
ret = (ret & BACKLIGHT_MODULATION_FREQ_MASK) >>
......@@ -86,7 +86,7 @@ static u32 psb_intel_lvds_get_max_backlight(struct drm_device *dev)
ret *= 2; /* Return a 16bit range as needed for setting */
if (ret == 0)
dev_err(dev->dev, "BL bug: Reg %08x save %08X\n",
REG_READ(BLC_PWM_CTL), dev_priv->saveBLC_PWM_CTL);
REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL);
return ret;
}
......@@ -203,13 +203,13 @@ static void psb_intel_lvds_set_backlight(struct drm_device *dev, int level)
REG_WRITE(BLC_PWM_CTL,
(blc_pwm_ctl |
(level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
dev_priv->saveBLC_PWM_CTL = (blc_pwm_ctl |
dev_priv->regs.saveBLC_PWM_CTL = (blc_pwm_ctl |
(level << BACKLIGHT_DUTY_CYCLE_SHIFT));
gma_power_end(dev);
} else {
blc_pwm_ctl = dev_priv->saveBLC_PWM_CTL &
blc_pwm_ctl = dev_priv->regs.saveBLC_PWM_CTL &
~BACKLIGHT_DUTY_CYCLE_MASK;
dev_priv->saveBLC_PWM_CTL = (blc_pwm_ctl |
dev_priv->regs.saveBLC_PWM_CTL = (blc_pwm_ctl |
(level << BACKLIGHT_DUTY_CYCLE_SHIFT));
}
}
......@@ -283,7 +283,7 @@ static void psb_intel_lvds_save(struct drm_connector *connector)
lvds_priv->savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);
/*TODO: move backlight_duty_cycle to psb_intel_lvds_priv*/
dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL &
dev_priv->backlight_duty_cycle = (dev_priv->regs.saveBLC_PWM_CTL &
BACKLIGHT_DUTY_CYCLE_MASK);
/*
......
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