Commit 64936258 authored by Jani Nikula's avatar Jani Nikula Committed by Daniel Vetter

drm/i915: change VLV IOSF sideband accessors to not return error code

We never check the return values, and there's not much we could do on
errors anyway. Just simplify the signatures. No functional changes.
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent ae99258f
...@@ -1137,16 +1137,15 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) ...@@ -1137,16 +1137,15 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
u32 freq_sts, val; u32 freq_sts, val;
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->rps.hw_lock);
vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
&freq_sts);
seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1, &val); val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1);
seq_printf(m, "max GPU freq: %d MHz\n", seq_printf(m, "max GPU freq: %d MHz\n",
vlv_gpu_freq(dev_priv->mem_freq, val)); vlv_gpu_freq(dev_priv->mem_freq, val));
vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val); val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM);
seq_printf(m, "min GPU freq: %d MHz\n", seq_printf(m, "min GPU freq: %d MHz\n",
vlv_gpu_freq(dev_priv->mem_freq, val)); vlv_gpu_freq(dev_priv->mem_freq, val));
......
...@@ -1931,9 +1931,9 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) ...@@ -1931,9 +1931,9 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
/* intel_sideband.c */ /* intel_sideband.c */
int vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val); u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
int vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
int vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val); u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg); u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val); void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
......
...@@ -214,7 +214,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev, ...@@ -214,7 +214,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->rps.hw_lock);
if (IS_VALLEYVIEW(dev_priv->dev)) { if (IS_VALLEYVIEW(dev_priv->dev)) {
u32 freq; u32 freq;
vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &freq); freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff); ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff);
} else { } else {
ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER; ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
......
...@@ -2569,7 +2569,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val) ...@@ -2569,7 +2569,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
do { do {
vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval); pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
if (time_after(jiffies, timeout)) { if (time_after(jiffies, timeout)) {
DRM_DEBUG_DRIVER("timed out waiting for Punit\n"); DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
break; break;
...@@ -2577,7 +2577,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val) ...@@ -2577,7 +2577,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
udelay(10); udelay(10);
} while (pval & 1); } while (pval & 1);
vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval); pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
if ((pval >> 8) != val) if ((pval >> 8) != val)
DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n", DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
val, pval >> 8); val, pval >> 8);
...@@ -2882,7 +2882,7 @@ int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) ...@@ -2882,7 +2882,7 @@ int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
{ {
u32 val, rp0; u32 val, rp0;
vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE, &val); val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
/* Clamp to max */ /* Clamp to max */
...@@ -2895,9 +2895,9 @@ static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) ...@@ -2895,9 +2895,9 @@ static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
{ {
u32 val, rpe; u32 val, rpe;
vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO, &val); val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI, &val); val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
return rpe; return rpe;
...@@ -2905,11 +2905,7 @@ static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) ...@@ -2905,11 +2905,7 @@ static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
{ {
u32 val; return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
return val & 0xff;
} }
static void vlv_rps_timer_work(struct work_struct *work) static void vlv_rps_timer_work(struct work_struct *work)
...@@ -3018,7 +3014,7 @@ static void valleyview_enable_rps(struct drm_device *dev) ...@@ -3018,7 +3014,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
I915_WRITE(GEN6_RC_CONTROL, I915_WRITE(GEN6_RC_CONTROL,
GEN7_RC_CTL_TO_MODE); GEN7_RC_CTL_TO_MODE);
vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val); val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
switch ((val >> 6) & 3) { switch ((val >> 6) & 3) {
case 0: case 0:
case 1: case 1:
......
...@@ -63,46 +63,42 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn, ...@@ -63,46 +63,42 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
return 0; return 0;
} }
int vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val) u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)
{ {
int ret; u32 val = 0;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->dpio_lock);
ret = vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
PUNIT_OPCODE_REG_READ, addr, val); PUNIT_OPCODE_REG_READ, addr, &val);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->dpio_lock);
return ret; return val;
} }
int vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val) void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
{ {
int ret;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->dpio_lock);
ret = vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
PUNIT_OPCODE_REG_WRITE, addr, &val); PUNIT_OPCODE_REG_WRITE, addr, &val);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->dpio_lock);
return ret;
} }
int vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val) u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
{ {
int ret; u32 val = 0;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->dpio_lock);
ret = vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC, vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC,
PUNIT_OPCODE_REG_READ, addr, val); PUNIT_OPCODE_REG_READ, addr, &val);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->dpio_lock);
return ret; return val;
} }
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg) u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg)
......
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