Commit 659a3062 authored by Nirmoy Das's avatar Nirmoy Das Committed by Jani Nikula

drm/i915/selftests: Set always_coherent to false when reading from CPU

Commit 8d4ba9fc ("drm/i915/selftests: Pick correct caching mode.")
was not complete  as for non LLC  sharing platforms cpu read can happen
from LLC which probably doesn't have the latest changes made by GPU.

Cc: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
Fixes: 8d4ba9fc ("drm/i915/selftests: Pick correct caching mode.")
Reviewed-by: default avatarJonathan Cavitt <jonathan.cavitt@intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516151403.2875-1-nirmoy.das@intel.comSigned-off-by: default avatarNirmoy Das <nirmoy.das@intel.com>
(cherry picked from commit 007ed708)
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent d4f36db6
...@@ -196,7 +196,7 @@ static int verify_access(struct drm_i915_private *i915, ...@@ -196,7 +196,7 @@ static int verify_access(struct drm_i915_private *i915,
if (err) if (err)
goto out_file; goto out_file;
mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, true); mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, false);
vaddr = i915_gem_object_pin_map_unlocked(native_obj, mode); vaddr = i915_gem_object_pin_map_unlocked(native_obj, mode);
if (IS_ERR(vaddr)) { if (IS_ERR(vaddr)) {
err = PTR_ERR(vaddr); err = PTR_ERR(vaddr);
......
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