Commit 65cc1a59 authored by Alexandre Belloni's avatar Alexandre Belloni

ARM: at91: pm: Use struct at91_pm_data in pm_suspend.S

The number of register we can safely pass to at91_pm_suspend_in_sram is
limited. Instead, pass the address to the at91_pm_data structure.

The offsets are automatically generated to avoid hardcoding them.
Acked-by: default avatarWenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@free-electrons.com>
parent 9e07c3ce
...@@ -18,3 +18,36 @@ endif ...@@ -18,3 +18,36 @@ endif
ifeq ($(CONFIG_PM_DEBUG),y) ifeq ($(CONFIG_PM_DEBUG),y)
CFLAGS_pm.o += -DDEBUG CFLAGS_pm.o += -DDEBUG
endif endif
# Default sed regexp - multiline due to syntax constraints
define sed-y
"/^->/{s:->#\(.*\):/* \1 */:; \
s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \
s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \
s:->::; p;}"
endef
# Use filechk to avoid rebuilds when a header changes, but the resulting file
# does not
define filechk_offsets
(set -e; \
echo "#ifndef $2"; \
echo "#define $2"; \
echo "/*"; \
echo " * DO NOT MODIFY."; \
echo " *"; \
echo " * This file was generated by Kbuild"; \
echo " */"; \
echo ""; \
sed -ne $(sed-y); \
echo ""; \
echo "#endif" )
endef
arch/arm/mach-at91/pm_data-offsets.s: arch/arm/mach-at91/pm_data-offsets.c
$(call if_changed_dep,cc_s_c)
include/generated/at91_pm_data-offsets.h: arch/arm/mach-at91/pm_data-offsets.s FORCE
$(call filechk,offsets,__PM_DATA_OFFSETS_H__)
arch/arm/mach-at91/pm_suspend.o: include/generated/at91_pm_data-offsets.h
...@@ -37,18 +37,13 @@ extern void at91_pinctrl_gpio_suspend(void); ...@@ -37,18 +37,13 @@ extern void at91_pinctrl_gpio_suspend(void);
extern void at91_pinctrl_gpio_resume(void); extern void at91_pinctrl_gpio_resume(void);
#endif #endif
static struct { static struct at91_pm_data pm_data;
void __iomem *pmc;
void __iomem *ramc[2];
unsigned long uhp_udp_mask;
int memctrl;
} at91_pm_data;
#define at91_ramc_read(id, field) \ #define at91_ramc_read(id, field) \
__raw_readl(at91_pm_data.ramc[id] + field) __raw_readl(pm_data.ramc[id] + field)
#define at91_ramc_write(id, field, value) \ #define at91_ramc_write(id, field, value) \
__raw_writel(value, at91_pm_data.ramc[id] + field) __raw_writel(value, pm_data.ramc[id] + field)
static int at91_pm_valid_state(suspend_state_t state) static int at91_pm_valid_state(suspend_state_t state)
{ {
...@@ -84,10 +79,10 @@ static int at91_pm_verify_clocks(void) ...@@ -84,10 +79,10 @@ static int at91_pm_verify_clocks(void)
unsigned long scsr; unsigned long scsr;
int i; int i;
scsr = readl(at91_pm_data.pmc + AT91_PMC_SCSR); scsr = readl(pm_data.pmc + AT91_PMC_SCSR);
/* USB must not be using PLLB */ /* USB must not be using PLLB */
if ((scsr & at91_pm_data.uhp_udp_mask) != 0) { if ((scsr & pm_data.uhp_udp_mask) != 0) {
pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
return 0; return 0;
} }
...@@ -98,7 +93,7 @@ static int at91_pm_verify_clocks(void) ...@@ -98,7 +93,7 @@ static int at91_pm_verify_clocks(void)
if ((scsr & (AT91_PMC_PCK0 << i)) == 0) if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
continue; continue;
css = readl(at91_pm_data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS; css = readl(pm_data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
if (css != AT91_PMC_CSS_SLOW) { if (css != AT91_PMC_CSS_SLOW) {
pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
return 0; return 0;
...@@ -124,25 +119,18 @@ int at91_suspend_entering_slow_clock(void) ...@@ -124,25 +119,18 @@ int at91_suspend_entering_slow_clock(void)
} }
EXPORT_SYMBOL(at91_suspend_entering_slow_clock); EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0, static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
void __iomem *ramc1, int memctrl); extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
void __iomem *ramc1, int memctrl);
extern u32 at91_pm_suspend_in_sram_sz; extern u32 at91_pm_suspend_in_sram_sz;
static void at91_pm_suspend(suspend_state_t state) static void at91_pm_suspend(suspend_state_t state)
{ {
unsigned int pm_data = at91_pm_data.memctrl; pm_data.mode = (state == PM_SUSPEND_MEM) ? AT91_PM_SLOW_CLOCK : 0;
pm_data |= (state == PM_SUSPEND_MEM) ?
AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
flush_cache_all(); flush_cache_all();
outer_disable(); outer_disable();
at91_suspend_sram_fn(at91_pm_data.pmc, at91_pm_data.ramc[0], at91_suspend_sram_fn(&pm_data);
at91_pm_data.ramc[1], pm_data);
outer_resume(); outer_resume();
} }
...@@ -245,7 +233,7 @@ static void at91rm9200_standby(void) ...@@ -245,7 +233,7 @@ static void at91rm9200_standby(void)
" mcr p15, 0, %0, c7, c0, 4\n\t" " mcr p15, 0, %0, c7, c0, 4\n\t"
" str %5, [%1, %2]" " str %5, [%1, %2]"
: :
: "r" (0), "r" (at91_pm_data.ramc[0]), "r" (AT91_MC_SDRAMC_LPR), : "r" (0), "r" (pm_data.ramc[0]), "r" (AT91_MC_SDRAMC_LPR),
"r" (1), "r" (AT91_MC_SDRAMC_SRR), "r" (1), "r" (AT91_MC_SDRAMC_SRR),
"r" (lpr)); "r" (lpr));
} }
...@@ -260,7 +248,7 @@ static void at91_ddr_standby(void) ...@@ -260,7 +248,7 @@ static void at91_ddr_standby(void)
u32 lpr0, lpr1 = 0; u32 lpr0, lpr1 = 0;
u32 saved_lpr0, saved_lpr1 = 0; u32 saved_lpr0, saved_lpr1 = 0;
if (at91_pm_data.ramc[1]) { if (pm_data.ramc[1]) {
saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
...@@ -272,13 +260,13 @@ static void at91_ddr_standby(void) ...@@ -272,13 +260,13 @@ static void at91_ddr_standby(void)
/* self-refresh mode now */ /* self-refresh mode now */
at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
if (at91_pm_data.ramc[1]) if (pm_data.ramc[1])
at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
cpu_do_idle(); cpu_do_idle();
at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
if (at91_pm_data.ramc[1]) if (pm_data.ramc[1])
at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
} }
...@@ -306,7 +294,7 @@ static void at91sam9_sdram_standby(void) ...@@ -306,7 +294,7 @@ static void at91sam9_sdram_standby(void)
u32 lpr0, lpr1 = 0; u32 lpr0, lpr1 = 0;
u32 saved_lpr0, saved_lpr1 = 0; u32 saved_lpr0, saved_lpr1 = 0;
if (at91_pm_data.ramc[1]) { if (pm_data.ramc[1]) {
saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
...@@ -318,13 +306,13 @@ static void at91sam9_sdram_standby(void) ...@@ -318,13 +306,13 @@ static void at91sam9_sdram_standby(void)
/* self-refresh mode now */ /* self-refresh mode now */
at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
if (at91_pm_data.ramc[1]) if (pm_data.ramc[1])
at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
cpu_do_idle(); cpu_do_idle();
at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
if (at91_pm_data.ramc[1]) if (pm_data.ramc[1])
at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
} }
...@@ -344,8 +332,8 @@ static __init void at91_dt_ramc(void) ...@@ -344,8 +332,8 @@ static __init void at91_dt_ramc(void)
const void *standby = NULL; const void *standby = NULL;
for_each_matching_node_and_match(np, ramc_ids, &of_id) { for_each_matching_node_and_match(np, ramc_ids, &of_id) {
at91_pm_data.ramc[idx] = of_iomap(np, 0); pm_data.ramc[idx] = of_iomap(np, 0);
if (!at91_pm_data.ramc[idx]) if (!pm_data.ramc[idx])
panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx); panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
if (!standby) if (!standby)
...@@ -371,12 +359,12 @@ static void at91rm9200_idle(void) ...@@ -371,12 +359,12 @@ static void at91rm9200_idle(void)
* Disable the processor clock. The processor will be automatically * Disable the processor clock. The processor will be automatically
* re-enabled by an interrupt or by a reset. * re-enabled by an interrupt or by a reset.
*/ */
writel(AT91_PMC_PCK, at91_pm_data.pmc + AT91_PMC_SCDR); writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
} }
static void at91sam9_idle(void) static void at91sam9_idle(void)
{ {
writel(AT91_PMC_PCK, at91_pm_data.pmc + AT91_PMC_SCDR); writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
cpu_do_idle(); cpu_do_idle();
} }
...@@ -445,8 +433,8 @@ static void __init at91_pm_init(void (*pm_idle)(void)) ...@@ -445,8 +433,8 @@ static void __init at91_pm_init(void (*pm_idle)(void))
platform_device_register(&at91_cpuidle_device); platform_device_register(&at91_cpuidle_device);
pmc_np = of_find_matching_node(NULL, atmel_pmc_ids); pmc_np = of_find_matching_node(NULL, atmel_pmc_ids);
at91_pm_data.pmc = of_iomap(pmc_np, 0); pm_data.pmc = of_iomap(pmc_np, 0);
if (!at91_pm_data.pmc) { if (!pm_data.pmc) {
pr_err("AT91: PM not supported, PMC not found\n"); pr_err("AT91: PM not supported, PMC not found\n");
return; return;
} }
...@@ -471,8 +459,8 @@ void __init at91rm9200_pm_init(void) ...@@ -471,8 +459,8 @@ void __init at91rm9200_pm_init(void)
*/ */
at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0); at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP; pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
at91_pm_data.memctrl = AT91_MEMCTRL_MC; pm_data.memctrl = AT91_MEMCTRL_MC;
at91_pm_init(at91rm9200_idle); at91_pm_init(at91rm9200_idle);
} }
...@@ -480,31 +468,31 @@ void __init at91rm9200_pm_init(void) ...@@ -480,31 +468,31 @@ void __init at91rm9200_pm_init(void)
void __init at91sam9260_pm_init(void) void __init at91sam9260_pm_init(void)
{ {
at91_dt_ramc(); at91_dt_ramc();
at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC; pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
at91_pm_init(at91sam9_idle); at91_pm_init(at91sam9_idle);
} }
void __init at91sam9g45_pm_init(void) void __init at91sam9g45_pm_init(void)
{ {
at91_dt_ramc(); at91_dt_ramc();
at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP; pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR; pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
at91_pm_init(at91sam9_idle); at91_pm_init(at91sam9_idle);
} }
void __init at91sam9x5_pm_init(void) void __init at91sam9x5_pm_init(void)
{ {
at91_dt_ramc(); at91_dt_ramc();
at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR; pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
at91_pm_init(at91sam9_idle); at91_pm_init(at91sam9_idle);
} }
void __init sama5_pm_init(void) void __init sama5_pm_init(void)
{ {
at91_dt_ramc(); at91_dt_ramc();
at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR; pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
at91_pm_init(NULL); at91_pm_init(NULL);
} }
...@@ -21,12 +21,16 @@ ...@@ -21,12 +21,16 @@
#define AT91_MEMCTRL_SDRAMC 1 #define AT91_MEMCTRL_SDRAMC 1
#define AT91_MEMCTRL_DDRSDR 2 #define AT91_MEMCTRL_DDRSDR 2
#define AT91_PM_MEMTYPE_MASK 0x0f
#define AT91_PM_MODE_OFFSET 4
#define AT91_PM_MODE_MASK 0x01
#define AT91_PM_MODE(x) (((x) & AT91_PM_MODE_MASK) << AT91_PM_MODE_OFFSET)
#define AT91_PM_SLOW_CLOCK 0x01 #define AT91_PM_SLOW_CLOCK 0x01
#ifndef __ASSEMBLY__
struct at91_pm_data {
void __iomem *pmc;
void __iomem *ramc[2];
unsigned long uhp_udp_mask;
unsigned int memctrl;
unsigned int mode;
};
#endif
#endif #endif
#include <linux/stddef.h>
#include <linux/kbuild.h>
#include "pm.h"
int main(void)
{
DEFINE(PM_DATA_PMC, offsetof(struct at91_pm_data, pmc));
DEFINE(PM_DATA_RAMC0, offsetof(struct at91_pm_data, ramc[0]));
DEFINE(PM_DATA_RAMC1, offsetof(struct at91_pm_data, ramc[1]));
DEFINE(PM_DATA_MEMCTRL, offsetof(struct at91_pm_data, memctrl));
DEFINE(PM_DATA_MODE, offsetof(struct at91_pm_data, mode));
return 0;
}
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
#include <linux/linkage.h> #include <linux/linkage.h>
#include <linux/clk/at91_pmc.h> #include <linux/clk/at91_pmc.h>
#include "pm.h" #include "pm.h"
#include "generated/at91_pm_data-offsets.h"
#define SRAMC_SELF_FRESH_ACTIVE 0x01 #define SRAMC_SELF_FRESH_ACTIVE 0x01
#define SRAMC_SELF_FRESH_EXIT 0x00 #define SRAMC_SELF_FRESH_EXIT 0x00
...@@ -72,13 +73,9 @@ tmp2 .req r5 ...@@ -72,13 +73,9 @@ tmp2 .req r5
.arm .arm
/* /*
* void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *sdramc, * void at91_suspend_sram_fn(struct at91_pm_data*)
* void __iomem *ramc1, int memctrl)
* @input param: * @input param:
* @r0: base address of AT91_PMC * @r0: base address of struct at91_pm_data
* @r1: base address of SDRAM Controller (SDRAM, DDRSDR, or AT91_SYS)
* @r2: base address of second SDRAM Controller or 0 if not present
* @r3: pm information
*/ */
/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */ /* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
.align 3 .align 3
...@@ -90,16 +87,16 @@ ENTRY(at91_pm_suspend_in_sram) ...@@ -90,16 +87,16 @@ ENTRY(at91_pm_suspend_in_sram)
mov tmp1, #0 mov tmp1, #0
mcr p15, 0, tmp1, c7, c10, 4 mcr p15, 0, tmp1, c7, c10, 4
str r0, .pmc_base ldr tmp1, [r0, #PM_DATA_PMC]
str r1, .sramc_base str tmp1, .pmc_base
str r2, .sramc1_base ldr tmp1, [r0, #PM_DATA_RAMC0]
str tmp1, .sramc_base
and r0, r3, #AT91_PM_MEMTYPE_MASK ldr tmp1, [r0, #PM_DATA_RAMC1]
str r0, .memtype str tmp1, .sramc1_base
ldr tmp1, [r0, #PM_DATA_MEMCTRL]
lsr r0, r3, #AT91_PM_MODE_OFFSET str tmp1, .memtype
and r0, r0, #AT91_PM_MODE_MASK ldr tmp1, [r0, #PM_DATA_MODE]
str r0, .pm_mode str tmp1, .pm_mode
/* Active the self-refresh mode */ /* Active the self-refresh mode */
mov r0, #SRAMC_SELF_FRESH_ACTIVE mov r0, #SRAMC_SELF_FRESH_ACTIVE
......
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