Commit 6617be3c authored by Stanislaw Grzeszczak's avatar Stanislaw Grzeszczak Committed by Tony Nguyen

i40e: Add basic support for I710 devices

Intel introduces a new line of 1G ethernet adapters with Device ID 0x0DD2
Signed-off-by: default avatarStanislaw Grzeszczak <stanislaw.a.grzeszczak@intel.com>
Signed-off-by: default avatarMateusz Palczewski <mateusz.palczewski@intel.com>
Tested-by: Gurucharan <gurucharanx.g@intel.com> (A Contingent worker at Intel)
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
parent 03fdb11d
...@@ -27,6 +27,7 @@ i40e_status i40e_set_mac_type(struct i40e_hw *hw) ...@@ -27,6 +27,7 @@ i40e_status i40e_set_mac_type(struct i40e_hw *hw)
case I40E_DEV_ID_QSFP_A: case I40E_DEV_ID_QSFP_A:
case I40E_DEV_ID_QSFP_B: case I40E_DEV_ID_QSFP_B:
case I40E_DEV_ID_QSFP_C: case I40E_DEV_ID_QSFP_C:
case I40E_DEV_ID_1G_BASE_T_BC:
case I40E_DEV_ID_5G_BASE_T_BC: case I40E_DEV_ID_5G_BASE_T_BC:
case I40E_DEV_ID_10G_BASE_T: case I40E_DEV_ID_10G_BASE_T:
case I40E_DEV_ID_10G_BASE_T4: case I40E_DEV_ID_10G_BASE_T4:
...@@ -4974,6 +4975,7 @@ i40e_status i40e_write_phy_register(struct i40e_hw *hw, ...@@ -4974,6 +4975,7 @@ i40e_status i40e_write_phy_register(struct i40e_hw *hw,
status = i40e_write_phy_register_clause22(hw, reg, phy_addr, status = i40e_write_phy_register_clause22(hw, reg, phy_addr,
value); value);
break; break;
case I40E_DEV_ID_1G_BASE_T_BC:
case I40E_DEV_ID_5G_BASE_T_BC: case I40E_DEV_ID_5G_BASE_T_BC:
case I40E_DEV_ID_10G_BASE_T: case I40E_DEV_ID_10G_BASE_T:
case I40E_DEV_ID_10G_BASE_T4: case I40E_DEV_ID_10G_BASE_T4:
...@@ -5012,6 +5014,7 @@ i40e_status i40e_read_phy_register(struct i40e_hw *hw, ...@@ -5012,6 +5014,7 @@ i40e_status i40e_read_phy_register(struct i40e_hw *hw,
status = i40e_read_phy_register_clause22(hw, reg, phy_addr, status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
value); value);
break; break;
case I40E_DEV_ID_1G_BASE_T_BC:
case I40E_DEV_ID_5G_BASE_T_BC: case I40E_DEV_ID_5G_BASE_T_BC:
case I40E_DEV_ID_10G_BASE_T: case I40E_DEV_ID_10G_BASE_T:
case I40E_DEV_ID_10G_BASE_T4: case I40E_DEV_ID_10G_BASE_T4:
......
...@@ -24,8 +24,10 @@ ...@@ -24,8 +24,10 @@
#define I40E_DEV_ID_10G_B 0x104F #define I40E_DEV_ID_10G_B 0x104F
#define I40E_DEV_ID_10G_SFP 0x104E #define I40E_DEV_ID_10G_SFP 0x104E
#define I40E_DEV_ID_5G_BASE_T_BC 0x101F #define I40E_DEV_ID_5G_BASE_T_BC 0x101F
#define I40E_DEV_ID_1G_BASE_T_BC 0x0DD2
#define I40E_IS_X710TL_DEVICE(d) \ #define I40E_IS_X710TL_DEVICE(d) \
(((d) == I40E_DEV_ID_5G_BASE_T_BC) || \ (((d) == I40E_DEV_ID_1G_BASE_T_BC) || \
((d) == I40E_DEV_ID_5G_BASE_T_BC) || \
((d) == I40E_DEV_ID_10G_BASE_T_BC)) ((d) == I40E_DEV_ID_10G_BASE_T_BC))
#define I40E_DEV_ID_KX_X722 0x37CE #define I40E_DEV_ID_KX_X722 0x37CE
#define I40E_DEV_ID_QSFP_X722 0x37CF #define I40E_DEV_ID_QSFP_X722 0x37CF
......
...@@ -66,6 +66,7 @@ static const struct pci_device_id i40e_pci_tbl[] = { ...@@ -66,6 +66,7 @@ static const struct pci_device_id i40e_pci_tbl[] = {
{PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0}, {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
{PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0}, {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
{PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0}, {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
{PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_BC), 0},
{PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0}, {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
{PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0}, {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
{PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_BC), 0}, {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_BC), 0},
......
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