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Commit 66ac69c8 authored by Felix Fietkau's avatar Felix Fietkau Committed by John W. Linville
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ath9k_hw: remove the old tx descriptor API 

Signed-off-by: default avatarFelix Fietkau <nbd@openwrt.org>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 493cf04f
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Showing with 0 additions and 472 deletions
drivers/net/wireless/ath/ath9k/ar9002_mac.c
View file @ 66ac69c8
...@@ -270,35 +270,6 @@ ar9002_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i) ...@@ -270,35 +270,6 @@ ar9002_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i)
| SM(i->rtscts_rate, AR_RTSCTSRate); | SM(i->rtscts_rate, AR_RTSCTSRate);
} }
static void ar9002_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
bool is_firstseg, bool is_lastseg,
const void *ds0, dma_addr_t buf_addr,
unsigned int qcu)
{
struct ar5416_desc *ads = AR5416DESC(ds);
ads->ds_data = buf_addr;
if (is_firstseg) {
ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
} else if (is_lastseg) {
ads->ds_ctl0 = 0;
ads->ds_ctl1 = seglen;
ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
} else {
ads->ds_ctl0 = 0;
ads->ds_ctl1 = seglen | AR_TxMore;
ads->ds_ctl2 = 0;
ads->ds_ctl3 = 0;
}
ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
}
static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds, static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
struct ath_tx_status *ts) struct ath_tx_status *ts)
{ {
...@@ -371,145 +342,6 @@ static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds, ...@@ -371,145 +342,6 @@ static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
return 0; return 0;
} }
static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
u32 pktLen, enum ath9k_pkt_type type,
u32 txPower, u8 keyIx,
enum ath9k_key_type keyType, u32 flags)
{
struct ar5416_desc *ads = AR5416DESC(ds);
if (txPower > 63)
txPower = 63;
ads->ds_ctl0 = (pktLen & AR_FrameLen)
| (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
| SM(txPower, AR_XmitPower)
| (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
| (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
| (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
ads->ds_ctl1 =
(keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
| SM(type, AR_FrameType)
| (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
| (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
| (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
ads->ds_ctl6 = SM(keyType, AR_EncrType);
if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
ads->ds_ctl8 = 0;
ads->ds_ctl9 = 0;
ads->ds_ctl10 = 0;
ads->ds_ctl11 = 0;
}
}
static void ar9002_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
{
struct ar5416_desc *ads = AR5416DESC(ds);
if (val)
ads->ds_ctl0 |= AR_ClrDestMask;
else
ads->ds_ctl0 &= ~AR_ClrDestMask;
}
static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
void *lastds,
u32 durUpdateEn, u32 rtsctsRate,
u32 rtsctsDuration,
struct ath9k_11n_rate_series series[],
u32 nseries, u32 flags)
{
struct ar5416_desc *ads = AR5416DESC(ds);
struct ar5416_desc *last_ads = AR5416DESC(lastds);
u32 ds_ctl0;
if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
ds_ctl0 = ads->ds_ctl0;
if (flags & ATH9K_TXDESC_RTSENA) {
ds_ctl0 &= ~AR_CTSEnable;
ds_ctl0 |= AR_RTSEnable;
} else {
ds_ctl0 &= ~AR_RTSEnable;
ds_ctl0 |= AR_CTSEnable;
}
ads->ds_ctl0 = ds_ctl0;
} else {
ads->ds_ctl0 =
(ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
}
ads->ds_ctl2 = set11nTries(series, 0)
| set11nTries(series, 1)
| set11nTries(series, 2)
| set11nTries(series, 3)
| (durUpdateEn ? AR_DurUpdateEna : 0)
| SM(0, AR_BurstDur);
ads->ds_ctl3 = set11nRate(series, 0)
| set11nRate(series, 1)
| set11nRate(series, 2)
| set11nRate(series, 3);
ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
| set11nPktDurRTSCTS(series, 1);
ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
| set11nPktDurRTSCTS(series, 3);
ads->ds_ctl7 = set11nRateFlags(series, 0)
| set11nRateFlags(series, 1)
| set11nRateFlags(series, 2)
| set11nRateFlags(series, 3)
| SM(rtsctsRate, AR_RTSCTSRate);
last_ads->ds_ctl2 = ads->ds_ctl2;
last_ads->ds_ctl3 = ads->ds_ctl3;
}
static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
u32 aggrLen)
{
struct ar5416_desc *ads = AR5416DESC(ds);
ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
ads->ds_ctl6 &= ~AR_AggrLen;
ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
}
static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
u32 numDelims)
{
struct ar5416_desc *ads = AR5416DESC(ds);
unsigned int ctl6;
ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
ctl6 = ads->ds_ctl6;
ctl6 &= ~AR_PadDelim;
ctl6 |= SM(numDelims, AR_PadDelim);
ads->ds_ctl6 = ctl6;
}
static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
{
struct ar5416_desc *ads = AR5416DESC(ds);
ads->ds_ctl1 |= AR_IsAggr;
ads->ds_ctl1 &= ~AR_MoreAggr;
ads->ds_ctl6 &= ~AR_PadDelim;
}
static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
{
struct ar5416_desc *ads = AR5416DESC(ds);
ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
}
void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
u32 size, u32 flags) u32 size, u32 flags)
{ {
...@@ -534,13 +366,5 @@ void ar9002_hw_attach_mac_ops(struct ath_hw *ah) ...@@ -534,13 +366,5 @@ void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
ops->set_desc_link = ar9002_hw_set_desc_link; ops->set_desc_link = ar9002_hw_set_desc_link;
ops->get_isr = ar9002_hw_get_isr; ops->get_isr = ar9002_hw_get_isr;
ops->set_txdesc = ar9002_set_txdesc; ops->set_txdesc = ar9002_set_txdesc;
ops->fill_txdesc = ar9002_hw_fill_txdesc;
ops->proc_txdesc = ar9002_hw_proc_txdesc; ops->proc_txdesc = ar9002_hw_proc_txdesc;
ops->set11n_txdesc = ar9002_hw_set11n_txdesc;
ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario;
ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first;
ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
ops->set_clrdmask = ar9002_hw_set_clrdmask;
} }
drivers/net/wireless/ath/ath9k/ar9003_mac.c
View file @ 66ac69c8
...@@ -311,46 +311,6 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) ...@@ -311,46 +311,6 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
return true; return true;
} }
static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
bool is_firstseg, bool is_lastseg,
const void *ds0, dma_addr_t buf_addr,
unsigned int qcu)
{
struct ar9003_txc *ads = (struct ar9003_txc *) ds;
unsigned int descid = 0;
ads->info = (ATHEROS_VENDOR_ID << AR_DescId_S) |
(1 << AR_TxRxDesc_S) |
(1 << AR_CtrlStat_S) |
(qcu << AR_TxQcuNum_S) | 0x17;
ads->data0 = buf_addr;
ads->data1 = 0;
ads->data2 = 0;
ads->data3 = 0;
ads->ctl3 = (seglen << AR_BufLen_S);
ads->ctl3 &= AR_BufLen;
/* Fill in pointer checksum and descriptor id */
ads->ctl10 = (descid << AR_TxDescId_S);
if (is_firstseg) {
ads->ctl12 |= (is_lastseg ? 0 : AR_TxMore);
} else if (is_lastseg) {
ads->ctl11 = 0;
ads->ctl12 = 0;
ads->ctl13 = AR9003TXC_CONST(ds0)->ctl13;
ads->ctl14 = AR9003TXC_CONST(ds0)->ctl14;
} else {
/* XXX Intermediate descriptor in a multi-descriptor frame.*/
ads->ctl11 = 0;
ads->ctl12 = AR_TxMore;
ads->ctl13 = 0;
ads->ctl14 = 0;
}
}
static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds, static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
struct ath_tx_status *ts) struct ath_tx_status *ts)
{ {
...@@ -435,161 +395,6 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds, ...@@ -435,161 +395,6 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
return 0; return 0;
} }
static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
u32 pktlen, enum ath9k_pkt_type type, u32 txpower,
u8 keyIx, enum ath9k_key_type keyType, u32 flags)
{
struct ar9003_txc *ads = (struct ar9003_txc *) ds;
if (txpower > ah->txpower_limit)
txpower = ah->txpower_limit;
if (txpower > 63)
txpower = 63;
ads->ctl11 = (pktlen & AR_FrameLen)
| (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
| SM(txpower, AR_XmitPower)
| (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
| (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
| (flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0);
ads->ctl12 =
(keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
| SM(type, AR_FrameType)
| (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
| (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
| (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
ads->ctl17 = SM(keyType, AR_EncrType) |
(flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0);
ads->ctl18 = 0;
ads->ctl19 = AR_Not_Sounding;
ads->ctl20 = 0;
ads->ctl21 = 0;
ads->ctl22 = 0;
}
static void ar9003_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
{
struct ar9003_txc *ads = (struct ar9003_txc *) ds;
if (val)
ads->ctl11 |= AR_ClrDestMask;
else
ads->ctl11 &= ~AR_ClrDestMask;
}
static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
void *lastds,
u32 durUpdateEn, u32 rtsctsRate,
u32 rtsctsDuration,
struct ath9k_11n_rate_series series[],
u32 nseries, u32 flags)
{
struct ar9003_txc *ads = (struct ar9003_txc *) ds;
struct ar9003_txc *last_ads = (struct ar9003_txc *) lastds;
u_int32_t ctl11;
if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
ctl11 = ads->ctl11;
if (flags & ATH9K_TXDESC_RTSENA) {
ctl11 &= ~AR_CTSEnable;
ctl11 |= AR_RTSEnable;
} else {
ctl11 &= ~AR_RTSEnable;
ctl11 |= AR_CTSEnable;
}
ads->ctl11 = ctl11;
} else {
ads->ctl11 = (ads->ctl11 & ~(AR_RTSEnable | AR_CTSEnable));
}
ads->ctl13 = set11nTries(series, 0)
| set11nTries(series, 1)
| set11nTries(series, 2)
| set11nTries(series, 3)
| (durUpdateEn ? AR_DurUpdateEna : 0)
| SM(0, AR_BurstDur);
ads->ctl14 = set11nRate(series, 0)
| set11nRate(series, 1)
| set11nRate(series, 2)
| set11nRate(series, 3);
ads->ctl15 = set11nPktDurRTSCTS(series, 0)
| set11nPktDurRTSCTS(series, 1);
ads->ctl16 = set11nPktDurRTSCTS(series, 2)
| set11nPktDurRTSCTS(series, 3);
ads->ctl18 = set11nRateFlags(series, 0)
| set11nRateFlags(series, 1)
| set11nRateFlags(series, 2)
| set11nRateFlags(series, 3)
| SM(rtsctsRate, AR_RTSCTSRate);
ads->ctl19 = AR_Not_Sounding;
last_ads->ctl13 = ads->ctl13;
last_ads->ctl14 = ads->ctl14;
}
static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
u32 aggrLen)
{
struct ar9003_txc *ads = (struct ar9003_txc *) ds;
ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
ads->ctl17 &= ~AR_AggrLen;
ads->ctl17 |= SM(aggrLen, AR_AggrLen);
}
static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
u32 numDelims)
{
struct ar9003_txc *ads = (struct ar9003_txc *) ds;
unsigned int ctl17;
ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
/*
* We use a stack variable to manipulate ctl6 to reduce uncached
* read modify, modfiy, write.
*/
ctl17 = ads->ctl17;
ctl17 &= ~AR_PadDelim;
ctl17 |= SM(numDelims, AR_PadDelim);
ads->ctl17 = ctl17;
}
static void ar9003_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
{
struct ar9003_txc *ads = (struct ar9003_txc *) ds;
ads->ctl12 |= AR_IsAggr;
ads->ctl12 &= ~AR_MoreAggr;
ads->ctl17 &= ~AR_PadDelim;
}
static void ar9003_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
{
struct ar9003_txc *ads = (struct ar9003_txc *) ds;
ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr);
}
void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains)
{
struct ar9003_txc *ads = ds;
ads->ctl12 |= SM(chains, AR_PAPRDChainMask);
}
EXPORT_SYMBOL(ar9003_hw_set_paprd_txdesc);
void ar9003_hw_attach_mac_ops(struct ath_hw *hw) void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
{ {
struct ath_hw_ops *ops = ath9k_hw_ops(hw); struct ath_hw_ops *ops = ath9k_hw_ops(hw);
...@@ -598,15 +403,7 @@ void ar9003_hw_attach_mac_ops(struct ath_hw *hw) ...@@ -598,15 +403,7 @@ void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
ops->set_desc_link = ar9003_hw_set_desc_link; ops->set_desc_link = ar9003_hw_set_desc_link;
ops->get_isr = ar9003_hw_get_isr; ops->get_isr = ar9003_hw_get_isr;
ops->set_txdesc = ar9003_set_txdesc; ops->set_txdesc = ar9003_set_txdesc;
ops->fill_txdesc = ar9003_hw_fill_txdesc;
ops->proc_txdesc = ar9003_hw_proc_txdesc; ops->proc_txdesc = ar9003_hw_proc_txdesc;
ops->set11n_txdesc = ar9003_hw_set11n_txdesc;
ops->set11n_ratescenario = ar9003_hw_set11n_ratescenario;
ops->set11n_aggr_first = ar9003_hw_set11n_aggr_first;
ops->set11n_aggr_middle = ar9003_hw_set11n_aggr_middle;
ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last;
ops->clr11n_aggr = ar9003_hw_clr11n_aggr;
ops->set_clrdmask = ar9003_hw_set_clrdmask;
} }
void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size) void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
......
drivers/net/wireless/ath/ath9k/hw-ops.h
View file @ 66ac69c8
...@@ -60,70 +60,12 @@ static inline void ath9k_hw_set_txdesc(struct ath_hw *ah, void *ds, ...@@ -60,70 +60,12 @@ static inline void ath9k_hw_set_txdesc(struct ath_hw *ah, void *ds,
return ath9k_hw_ops(ah)->set_txdesc(ah, ds, i); return ath9k_hw_ops(ah)->set_txdesc(ah, ds, i);
} }
static inline void ath9k_hw_filltxdesc(struct ath_hw *ah, void *ds, u32 seglen,
bool is_firstseg, bool is_lastseg,
const void *ds0, dma_addr_t buf_addr,
unsigned int qcu)
{
ath9k_hw_ops(ah)->fill_txdesc(ah, ds, seglen, is_firstseg, is_lastseg,
ds0, buf_addr, qcu);
}
static inline int ath9k_hw_txprocdesc(struct ath_hw *ah, void *ds, static inline int ath9k_hw_txprocdesc(struct ath_hw *ah, void *ds,
struct ath_tx_status *ts) struct ath_tx_status *ts)
{ {
return ath9k_hw_ops(ah)->proc_txdesc(ah, ds, ts); return ath9k_hw_ops(ah)->proc_txdesc(ah, ds, ts);
} }
static inline void ath9k_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
u32 pktLen, enum ath9k_pkt_type type,
u32 txPower, u32 keyIx,
enum ath9k_key_type keyType,
u32 flags)
{
ath9k_hw_ops(ah)->set11n_txdesc(ah, ds, pktLen, type, txPower, keyIx,
keyType, flags);
}
static inline void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
void *lastds,
u32 durUpdateEn, u32 rtsctsRate,
u32 rtsctsDuration,
struct ath9k_11n_rate_series series[],
u32 nseries, u32 flags)
{
ath9k_hw_ops(ah)->set11n_ratescenario(ah, ds, lastds, durUpdateEn,
rtsctsRate, rtsctsDuration, series,
nseries, flags);
}
static inline void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
u32 aggrLen)
{
ath9k_hw_ops(ah)->set11n_aggr_first(ah, ds, aggrLen);
}
static inline void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
u32 numDelims)
{
ath9k_hw_ops(ah)->set11n_aggr_middle(ah, ds, numDelims);
}
static inline void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
{
ath9k_hw_ops(ah)->set11n_aggr_last(ah, ds);
}
static inline void ath9k_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
{
ath9k_hw_ops(ah)->clr11n_aggr(ah, ds);
}
static inline void ath9k_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
{
ath9k_hw_ops(ah)->set_clrdmask(ah, ds, val);
}
static inline void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah, static inline void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
struct ath_hw_antcomb_conf *antconf) struct ath_hw_antcomb_conf *antconf)
{ {
......
drivers/net/wireless/ath/ath9k/hw.h
View file @ 66ac69c8
...@@ -618,30 +618,8 @@ struct ath_hw_ops { ...@@ -618,30 +618,8 @@ struct ath_hw_ops {
bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked); bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
void (*set_txdesc)(struct ath_hw *ah, void *ds, void (*set_txdesc)(struct ath_hw *ah, void *ds,
struct ath_tx_info *i); struct ath_tx_info *i);
void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
bool is_firstseg, bool is_is_lastseg,
const void *ds0, dma_addr_t buf_addr,
unsigned int qcu);
int (*proc_txdesc)(struct ath_hw *ah, void *ds, int (*proc_txdesc)(struct ath_hw *ah, void *ds,
struct ath_tx_status *ts); struct ath_tx_status *ts);
void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
u32 pktLen, enum ath9k_pkt_type type,
u32 txPower, u8 keyIx,
enum ath9k_key_type keyType,
u32 flags);
void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
void *lastds,
u32 durUpdateEn, u32 rtsctsRate,
u32 rtsctsDuration,
struct ath9k_11n_rate_series series[],
u32 nseries, u32 flags);
void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
u32 aggrLen);
void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
u32 numDelims);
void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
void (*set_clrdmask)(struct ath_hw *ah, void *ds, bool val);
void (*antdiv_comb_conf_get)(struct ath_hw *ah, void (*antdiv_comb_conf_get)(struct ath_hw *ah,
struct ath_hw_antcomb_conf *antconf); struct ath_hw_antcomb_conf *antconf);
void (*antdiv_comb_conf_set)(struct ath_hw *ah, void (*antdiv_comb_conf_set)(struct ath_hw *ah,
......
drivers/net/wireless/ath/ath9k/mac.c
View file @ 66ac69c8
...@@ -62,18 +62,6 @@ void ath9k_hw_txstart(struct ath_hw *ah, u32 q) ...@@ -62,18 +62,6 @@ void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
} }
EXPORT_SYMBOL(ath9k_hw_txstart); EXPORT_SYMBOL(ath9k_hw_txstart);
void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds)
{
struct ar5416_desc *ads = AR5416DESC(ds);
ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
}
EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q) u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
{ {
u32 npend; u32 npend;
......
drivers/net/wireless/ath/ath9k/mac.h
View file @ 66ac69c8
...@@ -712,7 +712,6 @@ enum ath9k_int; ...@@ -712,7 +712,6 @@ enum ath9k_int;
u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q); u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp); void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
void ath9k_hw_txstart(struct ath_hw *ah, u32 q); void ath9k_hw_txstart(struct ath_hw *ah, u32 q);
void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds);
u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q); u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel); bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q); bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q);
......
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