Commit 67b0e142 authored by Jian Shen's avatar Jian Shen Committed by David S. Miller

net: hns3: add support for user-def data of flow director

For DEVICE_VERSION_V3, the hardware supports to match specified
data in the specified offset of packet payload. Each layer can
have one offset, and can't be masked when configure flow director
rule by ethtool command. The layer is selected based on the
flow-type, ether for L2, ip4/ipv6 for L3, and tcp4/tcp6/udp4/udp6
for L4. For example, tcp4/tcp6/udp4/udp6 rules share the same
user-def offset, but each rule can have its own user-def value.

For the user-def field of ethtool -N/U command is 64 bits long.
The bit 0~15 is used for user-def value, and bit 32~47 for user-def
offset in HNS3 driver.
Signed-off-by: default avatarJian Shen <shenjian15@huawei.com>
Signed-off-by: default avatarHuazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent f07203b0
...@@ -243,6 +243,7 @@ enum hclge_opcode_type { ...@@ -243,6 +243,7 @@ enum hclge_opcode_type {
HCLGE_OPC_FD_KEY_CONFIG = 0x1202, HCLGE_OPC_FD_KEY_CONFIG = 0x1202,
HCLGE_OPC_FD_TCAM_OP = 0x1203, HCLGE_OPC_FD_TCAM_OP = 0x1203,
HCLGE_OPC_FD_AD_OP = 0x1204, HCLGE_OPC_FD_AD_OP = 0x1204,
HCLGE_OPC_FD_USER_DEF_OP = 0x1207,
/* MDIO command */ /* MDIO command */
HCLGE_OPC_MDIO_CONFIG = 0x1900, HCLGE_OPC_MDIO_CONFIG = 0x1900,
...@@ -1082,6 +1083,19 @@ struct hclge_fd_ad_config_cmd { ...@@ -1082,6 +1083,19 @@ struct hclge_fd_ad_config_cmd {
u8 rsv2[8]; u8 rsv2[8];
}; };
#define HCLGE_FD_USER_DEF_OFT_S 0
#define HCLGE_FD_USER_DEF_OFT_M GENMASK(14, 0)
#define HCLGE_FD_USER_DEF_EN_B 15
struct hclge_fd_user_def_cfg_cmd {
__le16 ol2_cfg;
__le16 l2_cfg;
__le16 ol3_cfg;
__le16 l3_cfg;
__le16 ol4_cfg;
__le16 l4_cfg;
u8 rsv[12];
};
struct hclge_get_m7_bd_cmd { struct hclge_get_m7_bd_cmd {
__le32 bd_num; __le32 bd_num;
u8 rsv[20]; u8 rsv[20];
......
...@@ -225,6 +225,7 @@ enum HCLGE_DEV_STATE { ...@@ -225,6 +225,7 @@ enum HCLGE_DEV_STATE {
HCLGE_STATE_RST_FAIL, HCLGE_STATE_RST_FAIL,
HCLGE_STATE_FD_TBL_CHANGED, HCLGE_STATE_FD_TBL_CHANGED,
HCLGE_STATE_FD_CLEAR_ALL, HCLGE_STATE_FD_CLEAR_ALL,
HCLGE_STATE_FD_USER_DEF_CHANGED,
HCLGE_STATE_MAX HCLGE_STATE_MAX
}; };
...@@ -538,6 +539,9 @@ enum HCLGE_FD_TUPLE { ...@@ -538,6 +539,9 @@ enum HCLGE_FD_TUPLE {
MAX_TUPLE, MAX_TUPLE,
}; };
#define HCLGE_FD_TUPLE_USER_DEF_TUPLES \
(BIT(INNER_L2_RSV) | BIT(INNER_L3_RSV) | BIT(INNER_L4_RSV))
enum HCLGE_FD_META_DATA { enum HCLGE_FD_META_DATA {
PACKET_TYPE_ID, PACKET_TYPE_ID,
IP_FRAGEMENT, IP_FRAGEMENT,
...@@ -572,6 +576,11 @@ struct key_info { ...@@ -572,6 +576,11 @@ struct key_info {
#define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4) #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4)
#define MAX_META_DATA_LENGTH 32 #define MAX_META_DATA_LENGTH 32
#define HCLGE_FD_MAX_USER_DEF_OFFSET 9000
#define HCLGE_FD_USER_DEF_DATA GENMASK(15, 0)
#define HCLGE_FD_USER_DEF_OFFSET GENMASK(15, 0)
#define HCLGE_FD_USER_DEF_OFFSET_UNMASK GENMASK(15, 0)
/* assigned by firmware, the real filter number for each pf may be less */ /* assigned by firmware, the real filter number for each pf may be less */
#define MAX_FD_FILTER_NUM 4096 #define MAX_FD_FILTER_NUM 4096
#define HCLGE_ARFS_EXPIRE_INTERVAL 5UL #define HCLGE_ARFS_EXPIRE_INTERVAL 5UL
...@@ -601,6 +610,26 @@ enum HCLGE_FD_NODE_STATE { ...@@ -601,6 +610,26 @@ enum HCLGE_FD_NODE_STATE {
HCLGE_FD_DELETED, HCLGE_FD_DELETED,
}; };
enum HCLGE_FD_USER_DEF_LAYER {
HCLGE_FD_USER_DEF_NONE,
HCLGE_FD_USER_DEF_L2,
HCLGE_FD_USER_DEF_L3,
HCLGE_FD_USER_DEF_L4,
};
#define HCLGE_FD_USER_DEF_LAYER_NUM 3
struct hclge_fd_user_def_cfg {
u16 ref_cnt;
u16 offset;
};
struct hclge_fd_user_def_info {
enum HCLGE_FD_USER_DEF_LAYER layer;
u16 data;
u16 data_mask;
u16 offset;
};
struct hclge_fd_key_cfg { struct hclge_fd_key_cfg {
u8 key_sel; u8 key_sel;
u8 inner_sipv6_word_en; u8 inner_sipv6_word_en;
...@@ -617,6 +646,7 @@ struct hclge_fd_cfg { ...@@ -617,6 +646,7 @@ struct hclge_fd_cfg {
u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */ u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */
u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */ u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */
struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM]; struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM];
struct hclge_fd_user_def_cfg user_def_cfg[HCLGE_FD_USER_DEF_LAYER_NUM];
}; };
#define IPV4_INDEX 3 #define IPV4_INDEX 3
...@@ -633,6 +663,9 @@ struct hclge_fd_rule_tuples { ...@@ -633,6 +663,9 @@ struct hclge_fd_rule_tuples {
u16 dst_port; u16 dst_port;
u16 vlan_tag1; u16 vlan_tag1;
u16 ether_proto; u16 ether_proto;
u16 l2_user_def;
u16 l3_user_def;
u32 l4_user_def;
u8 ip_tos; u8 ip_tos;
u8 ip_proto; u8 ip_proto;
}; };
...@@ -651,6 +684,9 @@ struct hclge_fd_rule { ...@@ -651,6 +684,9 @@ struct hclge_fd_rule {
struct { struct {
u16 flow_id; /* only used for arfs */ u16 flow_id; /* only used for arfs */
} arfs; } arfs;
struct {
struct hclge_fd_user_def_info user_def;
} ep;
}; };
u16 queue_id; u16 queue_id;
u16 vf_id; u16 vf_id;
......
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