Commit 689c9568 authored by Krzysztof Halasa's avatar Krzysztof Halasa Committed by Linus Torvalds

Intel FB: whitespace, bracket and other clean-ups

Intel FB: whitespace, bracket and other clean-ups
Signed-off-by: default avatarKrzysztof Halasa <khc@pm.waw.pl>
Cc: "Antonino A. Daplas" <adaplas@pol.net>
Cc: <sylvain.meyer@worldonline.fr>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 53ee1b5b
...@@ -231,8 +231,8 @@ struct intelfb_hwstate { ...@@ -231,8 +231,8 @@ struct intelfb_hwstate {
struct intelfb_heap_data { struct intelfb_heap_data {
u32 physical; u32 physical;
u8 __iomem *virtual; u8 __iomem *virtual;
u32 offset; // in GATT pages u32 offset; /* in GATT pages */
u32 size; // in bytes u32 size; /* in bytes */
}; };
#ifdef CONFIG_FB_INTEL_I2C #ifdef CONFIG_FB_INTEL_I2C
...@@ -270,9 +270,9 @@ struct intelfb_info { ...@@ -270,9 +270,9 @@ struct intelfb_info {
struct intelfb_hwstate save_state; struct intelfb_hwstate save_state;
/* agpgart structs */ /* agpgart structs */
struct agp_memory *gtt_fb_mem; // use all stolen memory or vram struct agp_memory *gtt_fb_mem; /* use all stolen memory or vram */
struct agp_memory *gtt_ring_mem; // ring buffer struct agp_memory *gtt_ring_mem; /* ring buffer */
struct agp_memory *gtt_cursor_mem; // hw cursor struct agp_memory *gtt_cursor_mem; /* hw cursor */
/* use a gart reserved fb mem */ /* use a gart reserved fb mem */
u8 fbmem_gart; u8 fbmem_gart;
...@@ -346,7 +346,7 @@ struct intelfb_info { ...@@ -346,7 +346,7 @@ struct intelfb_info {
/* driver registered */ /* driver registered */
int registered; int registered;
/* index into plls */ /* index into plls */
int pll_index; int pll_index;
......
...@@ -58,7 +58,8 @@ static void intelfb_gpio_setscl(void *data, int state) ...@@ -58,7 +58,8 @@ static void intelfb_gpio_setscl(void *data, int state)
struct intelfb_info *dinfo = chan->dinfo; struct intelfb_info *dinfo = chan->dinfo;
u32 val; u32 val;
OUTREG(chan->reg, (state ? SCL_VAL_OUT : 0) | SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK); OUTREG(chan->reg, (state ? SCL_VAL_OUT : 0) |
SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK);
val = INREG(chan->reg); val = INREG(chan->reg);
} }
...@@ -68,7 +69,8 @@ static void intelfb_gpio_setsda(void *data, int state) ...@@ -68,7 +69,8 @@ static void intelfb_gpio_setsda(void *data, int state)
struct intelfb_info *dinfo = chan->dinfo; struct intelfb_info *dinfo = chan->dinfo;
u32 val; u32 val;
OUTREG(chan->reg, (state ? SDA_VAL_OUT : 0) | SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK); OUTREG(chan->reg, (state ? SDA_VAL_OUT : 0) |
SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK);
val = INREG(chan->reg); val = INREG(chan->reg);
} }
...@@ -97,26 +99,26 @@ static int intelfb_gpio_getsda(void *data) ...@@ -97,26 +99,26 @@ static int intelfb_gpio_getsda(void *data)
} }
static int intelfb_setup_i2c_bus(struct intelfb_info *dinfo, static int intelfb_setup_i2c_bus(struct intelfb_info *dinfo,
struct intelfb_i2c_chan *chan, struct intelfb_i2c_chan *chan,
const u32 reg, const char *name) const u32 reg, const char *name)
{ {
int rc; int rc;
chan->dinfo = dinfo; chan->dinfo = dinfo;
chan->reg = reg; chan->reg = reg;
snprintf(chan->adapter.name, sizeof(chan->adapter.name), snprintf(chan->adapter.name, sizeof(chan->adapter.name),
"intelfb %s", name); "intelfb %s", name);
chan->adapter.owner = THIS_MODULE; chan->adapter.owner = THIS_MODULE;
chan->adapter.id = I2C_HW_B_INTELFB; chan->adapter.id = I2C_HW_B_INTELFB;
chan->adapter.algo_data = &chan->algo; chan->adapter.algo_data = &chan->algo;
chan->adapter.dev.parent = &chan->dinfo->pdev->dev; chan->adapter.dev.parent = &chan->dinfo->pdev->dev;
chan->algo.setsda = intelfb_gpio_setsda; chan->algo.setsda = intelfb_gpio_setsda;
chan->algo.setscl = intelfb_gpio_setscl; chan->algo.setscl = intelfb_gpio_setscl;
chan->algo.getsda = intelfb_gpio_getsda; chan->algo.getsda = intelfb_gpio_getsda;
chan->algo.getscl = intelfb_gpio_getscl; chan->algo.getscl = intelfb_gpio_getscl;
chan->algo.udelay = 40; chan->algo.udelay = 40;
chan->algo.timeout = 20; chan->algo.timeout = 20;
chan->algo.data = chan; chan->algo.data = chan;
i2c_set_adapdata(&chan->adapter, chan); i2c_set_adapdata(&chan->adapter, chan);
...@@ -142,40 +144,44 @@ void intelfb_create_i2c_busses(struct intelfb_info *dinfo) ...@@ -142,40 +144,44 @@ void intelfb_create_i2c_busses(struct intelfb_info *dinfo)
dinfo->output[i].type = INTELFB_OUTPUT_ANALOG; dinfo->output[i].type = INTELFB_OUTPUT_ANALOG;
/* setup the DDC bus for analog output */ /* setup the DDC bus for analog output */
intelfb_setup_i2c_bus(dinfo, &dinfo->output[i].ddc_bus, GPIOA, "CRTDDC_A"); intelfb_setup_i2c_bus(dinfo, &dinfo->output[i].ddc_bus, GPIOA,
"CRTDDC_A");
i++; i++;
/* need to add the output busses for each device /* need to add the output busses for each device
- this function is very incomplete - this function is very incomplete
- i915GM has LVDS and TVOUT for example - i915GM has LVDS and TVOUT for example
*/ */
switch(dinfo->chipset) { switch(dinfo->chipset) {
case INTEL_830M: case INTEL_830M:
case INTEL_845G: case INTEL_845G:
case INTEL_855GM: case INTEL_855GM:
case INTEL_865G: case INTEL_865G:
dinfo->output[i].type = INTELFB_OUTPUT_DVO; dinfo->output[i].type = INTELFB_OUTPUT_DVO;
intelfb_setup_i2c_bus(dinfo, &dinfo->output[i].ddc_bus, GPIOD, "DVODDC_D"); intelfb_setup_i2c_bus(dinfo, &dinfo->output[i].ddc_bus,
intelfb_setup_i2c_bus(dinfo, &dinfo->output[i].i2c_bus, GPIOE, "DVOI2C_E"); GPIOD, "DVODDC_D");
intelfb_setup_i2c_bus(dinfo, &dinfo->output[i].i2c_bus,
GPIOE, "DVOI2C_E");
i++; i++;
break; break;
case INTEL_915G: case INTEL_915G:
case INTEL_915GM: case INTEL_915GM:
/* has some LVDS + tv-out */ /* has some LVDS + tv-out */
case INTEL_945G: case INTEL_945G:
case INTEL_945GM: case INTEL_945GM:
/* SDVO ports have a single control bus - 2 devices */ /* SDVO ports have a single control bus - 2 devices */
dinfo->output[i].type = INTELFB_OUTPUT_SDVO; dinfo->output[i].type = INTELFB_OUTPUT_SDVO;
intelfb_setup_i2c_bus(dinfo, &dinfo->output[i].i2c_bus, GPIOE, "SDVOCTRL_E"); intelfb_setup_i2c_bus(dinfo, &dinfo->output[i].i2c_bus,
GPIOE, "SDVOCTRL_E");
/* TODO: initialize the SDVO */ /* TODO: initialize the SDVO */
// I830SDVOInit(pScrn, i, DVOB); /* I830SDVOInit(pScrn, i, DVOB); */
i++; i++;
/* set up SDVOC */ /* set up SDVOC */
dinfo->output[i].type = INTELFB_OUTPUT_SDVO; dinfo->output[i].type = INTELFB_OUTPUT_SDVO;
dinfo->output[i].i2c_bus = dinfo->output[i - 1].i2c_bus; dinfo->output[i].i2c_bus = dinfo->output[i - 1].i2c_bus;
/* TODO: initialize the SDVO */ /* TODO: initialize the SDVO */
// I830SDVOInit(pScrn, i, DVOC); /* I830SDVOInit(pScrn, i, DVOC); */
i++; i++;
break; break;
} }
......
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...@@ -83,7 +83,7 @@ ...@@ -83,7 +83,7 @@
*/ */
#define RING_MIN_FREE 64 #define RING_MIN_FREE 64
#define IPEHR 0x2088 #define IPEHR 0x2088
#define INSTDONE 0x2090 #define INSTDONE 0x2090
#define PRI_RING_EMPTY 1 #define PRI_RING_EMPTY 1
...@@ -128,9 +128,9 @@ ...@@ -128,9 +128,9 @@
#define GPIOA 0x5010 #define GPIOA 0x5010
#define GPIOB 0x5014 #define GPIOB 0x5014
#define GPIOC 0x5018 // this may be external DDC on i830 #define GPIOC 0x5018 /* this may be external DDC on i830 */
#define GPIOD 0x501C // this is DVO DDC #define GPIOD 0x501C /* this is DVO DDC */
#define GPIOE 0x5020 // this is DVO i2C #define GPIOE 0x5020 /* this is DVO i2C */
#define GPIOF 0x5024 #define GPIOF 0x5024
/* PLL registers */ /* PLL registers */
...@@ -269,8 +269,8 @@ ...@@ -269,8 +269,8 @@
#define PORT_ENABLE (1 << 31) #define PORT_ENABLE (1 << 31)
#define PORT_PIPE_SELECT_SHIFT 30 #define PORT_PIPE_SELECT_SHIFT 30
#define PORT_TV_FLAGS_MASK 0xFF #define PORT_TV_FLAGS_MASK 0xFF
#define PORT_TV_FLAGS 0xC4 // ripped from my BIOS #define PORT_TV_FLAGS 0xC4 /* ripped from my BIOS
// to understand and correct to understand and correct */
#define DVOA_SRCDIM 0x61124 #define DVOA_SRCDIM 0x61124
#define DVOB_SRCDIM 0x61144 #define DVOB_SRCDIM 0x61144
...@@ -369,7 +369,7 @@ ...@@ -369,7 +369,7 @@
#define DISPPLANE_8BPP (0x2<<26) #define DISPPLANE_8BPP (0x2<<26)
#define DISPPLANE_15_16BPP (0x4<<26) #define DISPPLANE_15_16BPP (0x4<<26)
#define DISPPLANE_16BPP (0x5<<26) #define DISPPLANE_16BPP (0x5<<26)
#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
#define DISPPLANE_32BPP (0x7<<26) #define DISPPLANE_32BPP (0x7<<26)
#define DISPPLANE_STEREO_ENABLE (1<<25) #define DISPPLANE_STEREO_ENABLE (1<<25)
#define DISPPLANE_STEREO_DISABLE 0 #define DISPPLANE_STEREO_DISABLE 0
......
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