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Kirill Smelkov
linux
Commits
68f3f702
Commit
68f3f702
authored
Aug 20, 2015
by
Ben Skeggs
Browse files
Options
Browse Files
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Email Patches
Plain Diff
drm/nouveau/core: remove the remainder of the previous style
Signed-off-by:
Ben Skeggs
<
bskeggs@redhat.com
>
parent
7624fc01
Changes
68
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Showing
68 changed files
with
496 additions
and
1856 deletions
+496
-1856
drivers/gpu/drm/nouveau/include/nvif/device.h
drivers/gpu/drm/nouveau/include/nvif/device.h
+5
-1
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+46
-64
drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
+3
-49
drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h
drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h
+2
-35
drivers/gpu/drm/nouveau/include/nvkm/core/object.h
drivers/gpu/drm/nouveau/include/nvkm/core/object.h
+3
-85
drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
+4
-47
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
+1
-3
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
+1
-1
drivers/gpu/drm/nouveau/nvkm/core/engine.c
drivers/gpu/drm/nouveau/nvkm/core/engine.c
+8
-71
drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
+0
-93
drivers/gpu/drm/nouveau/nvkm/core/object.c
drivers/gpu/drm/nouveau/nvkm/core/object.c
+1
-166
drivers/gpu/drm/nouveau/nvkm/core/oproxy.c
drivers/gpu/drm/nouveau/nvkm/core/oproxy.c
+0
-2
drivers/gpu/drm/nouveau/nvkm/core/ramht.c
drivers/gpu/drm/nouveau/nvkm/core/ramht.c
+16
-29
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
+43
-180
drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c
drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c
+3
-3
drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c
drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c
+4
-4
drivers/gpu/drm/nouveau/nvkm/engine/ce/gm204.c
drivers/gpu/drm/nouveau/nvkm/engine/ce/gm204.c
+3
-3
drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c
drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c
drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild
+0
-10
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+55
-186
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
+0
-53
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
+0
-51
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+0
-67
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
+0
-39
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
+0
-51
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
+0
-43
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
+0
-45
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
+0
-67
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+0
-63
drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h
drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h
+0
-10
drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
+4
-4
drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c
+50
-55
drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c
+12
-22
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c
+7
-7
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c
+3
-3
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c
+4
-4
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c
+12
-22
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
+25
-25
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
+17
-17
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
+18
-18
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c
+14
-20
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
+8
-14
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
+2
-2
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c
+7
-7
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c
+6
-6
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
+7
-7
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c
+3
-3
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
+5
-5
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c
+6
-6
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c
+2
-2
drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c
+16
-16
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c
+20
-20
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c
+10
-10
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
+13
-13
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
+13
-13
No files found.
drivers/gpu/drm/nouveau/include/nvif/device.h
View file @
68f3f702
...
...
@@ -48,7 +48,11 @@ u64 nvif_device_time(struct nvif_device *);
#define nvxx_device(a) ({ \
struct nvif_device *_device = (a); \
nv_device(_device->object.priv); \
struct { \
struct nvkm_object object; \
struct nvkm_device *device; \
} *_udevice = _device->object.priv; \
_udevice->device; \
})
#define nvxx_bios(a) nvxx_device(a)->bios
#define nvxx_fb(a) nvxx_device(a)->fb
...
...
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View file @
68f3f702
#ifndef __NVKM_DEVICE_H__
#define __NVKM_DEVICE_H__
#include <core/engine.h>
#include <core/event.h>
#include <core/object.h>
enum
nvkm_devidx
{
NVDEV_SUBDEV_VBIOS
,
/* All subdevs from DEVINIT to DEVINIT_LAST will be created before
* *any* of them are initialised. This subdev category is used
* for any subdevs that the VBIOS init table parsing may call out
* to during POST.
*/
NVDEV_SUBDEV_DEVINIT
,
NVDEV_SUBDEV_IBUS
,
NVDEV_SUBDEV_GPIO
,
NVDEV_SUBDEV_I2C
,
NVDEV_SUBDEV_DEVINIT_LAST
=
NVDEV_SUBDEV_I2C
,
/* This grouping of subdevs are initialised right after they've
* been created, and are allowed to assume any subdevs in the
* list above them exist and have been initialised.
*/
NVDEV_SUBDEV_FUSE
,
NVDEV_SUBDEV_MXM
,
NVDEV_SUBDEV_MC
,
NVDEV_SUBDEV_BUS
,
NVDEV_SUBDEV_TIMER
,
NVDEV_SUBDEV_FB
,
NVDEV_SUBDEV_LTC
,
NVDEV_SUBDEV_INSTMEM
,
NVDEV_SUBDEV_MMU
,
NVDEV_SUBDEV_BAR
,
NVDEV_SUBDEV_PMU
,
NVDEV_SUBDEV_VOLT
,
NVDEV_SUBDEV_THERM
,
NVDEV_SUBDEV_CLK
,
NVDEV_ENGINE_FIRST
,
NVDEV_ENGINE_DMAOBJ
=
NVDEV_ENGINE_FIRST
,
NVDEV_ENGINE_IFB
,
NVDEV_ENGINE_FIFO
,
NVDEV_ENGINE_SW
,
NVDEV_ENGINE_GR
,
NVDEV_ENGINE_MPEG
,
NVDEV_ENGINE_ME
,
NVDEV_ENGINE_VP
,
NVDEV_ENGINE_CIPHER
,
NVDEV_ENGINE_BSP
,
NVDEV_ENGINE_MSPPP
,
NVDEV_ENGINE_CE0
,
NVDEV_ENGINE_CE1
,
NVDEV_ENGINE_CE2
,
NVDEV_ENGINE_VIC
,
NVDEV_ENGINE_MSENC
,
NVDEV_ENGINE_DISP
,
NVDEV_ENGINE_PM
,
NVDEV_ENGINE_MSVLD
,
NVDEV_ENGINE_SEC
,
NVDEV_ENGINE_MSPDEC
,
NVDEV_SUBDEV_NR
,
NVKM_SUBDEV_VBIOS
,
NVKM_SUBDEV_DEVINIT
,
NVKM_SUBDEV_IBUS
,
NVKM_SUBDEV_GPIO
,
NVKM_SUBDEV_I2C
,
NVKM_SUBDEV_FUSE
,
NVKM_SUBDEV_MXM
,
NVKM_SUBDEV_MC
,
NVKM_SUBDEV_BUS
,
NVKM_SUBDEV_TIMER
,
NVKM_SUBDEV_FB
,
NVKM_SUBDEV_LTC
,
NVKM_SUBDEV_INSTMEM
,
NVKM_SUBDEV_MMU
,
NVKM_SUBDEV_BAR
,
NVKM_SUBDEV_PMU
,
NVKM_SUBDEV_VOLT
,
NVKM_SUBDEV_THERM
,
NVKM_SUBDEV_CLK
,
NVKM_ENGINE_DMAOBJ
,
NVKM_ENGINE_IFB
,
NVKM_ENGINE_FIFO
,
NVKM_ENGINE_SW
,
NVKM_ENGINE_GR
,
NVKM_ENGINE_MPEG
,
NVKM_ENGINE_ME
,
NVKM_ENGINE_VP
,
NVKM_ENGINE_CIPHER
,
NVKM_ENGINE_BSP
,
NVKM_ENGINE_MSPPP
,
NVKM_ENGINE_CE0
,
NVKM_ENGINE_CE1
,
NVKM_ENGINE_CE2
,
NVKM_ENGINE_VIC
,
NVKM_ENGINE_MSENC
,
NVKM_ENGINE_DISP
,
NVKM_ENGINE_PM
,
NVKM_ENGINE_MSVLD
,
NVKM_ENGINE_SEC
,
NVKM_ENGINE_MSPDEC
,
NVKM_SUBDEV_NR
,
};
struct
nvkm_device
{
struct
nvkm_engine
engine
;
const
struct
nvkm_device_func
*
func
;
const
struct
nvkm_device_quirk
*
quirk
;
struct
device
*
dev
;
...
...
@@ -85,6 +70,7 @@ struct nvkm_device {
struct
nvkm_event
event
;
u64
disable_mask
;
u32
debug
;
const
struct
nvkm_device_chip
*
chip
;
enum
{
...
...
@@ -103,8 +89,6 @@ struct nvkm_device {
u8
chiprev
;
u32
crystal
;
struct
nvkm_oclass
*
oclass
[
NVDEV_SUBDEV_NR
];
struct
{
struct
notifier_block
nb
;
}
acpi
;
...
...
@@ -227,8 +211,6 @@ int nvkm_device_list(u64 *name, int size);
_temp; \
})
struct
nvkm_device
*
nv_device
(
void
*
obj
);
static
inline
bool
nv_device_match
(
struct
nvkm_device
*
device
,
u16
dev
,
u16
ven
,
u16
sub
)
{
...
...
@@ -285,7 +267,7 @@ extern const struct nvkm_sclass nvkm_udevice_sclass;
/* device logging */
#define nvdev_printk_(d,l,p,f,a...) do { \
struct nvkm_device *_device = (d); \
if (_device->
engine.subdev.debug >= (l))
\
if (_device->
debug >= (l))
\
dev_##p(_device->dev, f, ##a); \
} while(0)
#define nvdev_printk(d,l,p,f,a...) nvdev_printk_((d), NV_DBG_##l, p, f, ##a)
...
...
drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
View file @
68f3f702
#ifndef __NVKM_ENGINE_H__
#define __NVKM_ENGINE_H__
#define nvkm_engine(p) container_of((p), struct nvkm_engine, subdev)
#include <core/subdev.h>
struct
nvkm_device_oclass
;
/*XXX: DEV!ENG */
struct
nvkm_fifo_chan
;
struct
nvkm_fb_tile
;
#define NV_ENGINE_(eng,var) (((var) << 8) | (eng))
#define NV_ENGINE(name,var) NV_ENGINE_(NVDEV_ENGINE_##name, (var))
struct
nvkm_engine
{
struct
nvkm_subdev
subdev
;
const
struct
nvkm_engine_func
*
func
;
struct
nvkm_subdev
subdev
;
spinlock_t
lock
;
int
usecount
;
struct
nvkm_oclass
*
cclass
;
struct
nvkm_oclass
*
sclass
;
struct
list_head
contexts
;
spinlock_t
lock
;
};
struct
nvkm_engine_func
{
...
...
@@ -54,42 +46,4 @@ int nvkm_engine_new_(const struct nvkm_engine_func *, struct nvkm_device *,
struct
nvkm_engine
*
nvkm_engine_ref
(
struct
nvkm_engine
*
);
void
nvkm_engine_unref
(
struct
nvkm_engine
**
);
void
nvkm_engine_tile
(
struct
nvkm_engine
*
,
int
region
);
static
inline
struct
nvkm_engine
*
nv_engine
(
void
*
obj
)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
BUG_ON
(
!
nv_iclass
(
obj
,
NV_ENGINE_CLASS
));
#endif
return
obj
;
}
static
inline
int
nv_engidx
(
struct
nvkm_engine
*
engine
)
{
return
nv_subidx
(
&
engine
->
subdev
);
}
struct
nvkm_engine
*
nvkm_engine
(
void
*
obj
,
int
idx
);
#define nvkm_engine_create(p,e,c,d,i,f,r) \
nvkm_engine_create_((p), (e), (c), (d), (i), (f), \
sizeof(**r),(void **)r)
#define nvkm_engine_destroy(p) \
nvkm_subdev_destroy(&(p)->subdev)
#define nvkm_engine_init_old(p) \
nvkm_subdev_init_old(&(p)->subdev)
#define nvkm_engine_fini_old(p,s) \
nvkm_subdev_fini_old(&(p)->subdev, (s))
int
nvkm_engine_create_
(
struct
nvkm_object
*
,
struct
nvkm_object
*
,
struct
nvkm_oclass
*
,
bool
,
const
char
*
,
const
char
*
,
int
,
void
**
);
#define _nvkm_engine_dtor _nvkm_subdev_dtor
#define _nvkm_engine_init _nvkm_subdev_init
#define _nvkm_engine_fini _nvkm_subdev_fini
#include <core/device.h>
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h
View file @
68f3f702
...
...
@@ -33,41 +33,8 @@ struct nvkm_gpuobj_func {
int
nvkm_gpuobj_new
(
struct
nvkm_device
*
,
u32
size
,
int
align
,
bool
zero
,
struct
nvkm_gpuobj
*
parent
,
struct
nvkm_gpuobj
**
);
void
nvkm_gpuobj_del
(
struct
nvkm_gpuobj
**
);
static
inline
struct
nvkm_gpuobj
*
nv_gpuobj
(
void
*
obj
)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
BUG_ON
(
!
nv_iclass
(
obj
,
NV_GPUOBJ_CLASS
));
#endif
return
obj
;
}
#define nvkm_gpuobj_create(p,e,c,v,g,s,a,f,d) \
nvkm_gpuobj_create_((p), (e), (c), (v), (g), (s), (a), (f), \
sizeof(**d), (void **)d)
#define nvkm_gpuobj_init(p) _nvkm_object_init(&(p)->object)
#define nvkm_gpuobj_fini(p,s) _nvkm_object_fini(&(p)->object, (s))
int
nvkm_gpuobj_create_
(
struct
nvkm_object
*
,
struct
nvkm_object
*
,
struct
nvkm_oclass
*
,
u32
pclass
,
struct
nvkm_object
*
,
u32
size
,
u32
align
,
u32
flags
,
int
length
,
void
**
);
void
nvkm_gpuobj_destroy
(
struct
nvkm_gpuobj
*
);
int
nvkm_gpuobj_wrap
(
struct
nvkm_memory
*
,
struct
nvkm_gpuobj
**
);
int
nvkm_gpuobj_map
(
struct
nvkm_gpuobj
*
,
struct
nvkm_vm
*
,
u32
access
,
struct
nvkm_vma
*
);
void
nvkm_gpuobj_unmap
(
struct
nvkm_vma
*
);
static
inline
void
nvkm_gpuobj_ref
(
struct
nvkm_gpuobj
*
obj
,
struct
nvkm_gpuobj
**
ref
)
{
nvkm_object_ref
(
&
obj
->
object
,
(
struct
nvkm_object
**
)
ref
);
}
void
_nvkm_gpuobj_dtor
(
struct
nvkm_object
*
);
int
_nvkm_gpuobj_init
(
struct
nvkm_object
*
);
int
_nvkm_gpuobj_fini
(
struct
nvkm_object
*
,
bool
);
u32
_nvkm_gpuobj_rd32
(
struct
nvkm_object
*
,
u64
);
void
_nvkm_gpuobj_wr32
(
struct
nvkm_object
*
,
u64
,
u32
);
#endif
drivers/gpu/drm/nouveau/include/nvkm/core/object.h
View file @
68f3f702
...
...
@@ -4,32 +4,18 @@
#include <core/debug.h>
struct
nvkm_event
;
struct
nvkm_gpuobj
;
#define NV_PARENT_CLASS 0x80000000
#define NV_NAMEDB_CLASS 0x40000000
#define NV_CLIENT_CLASS 0x20000000
#define NV_SUBDEV_CLASS 0x10000000
#define NV_ENGINE_CLASS 0x08000000
#define NV_MEMOBJ_CLASS 0x04000000
#define NV_GPUOBJ_CLASS 0x02000000
#define NV_ENGCTX_CLASS 0x01000000
struct
nvkm_oclass
;
struct
nvkm_object
{
const
struct
nvkm_object_func
*
func
;
struct
nvkm_client
*
client
;
struct
nvkm_engine
*
engine
;
u32
oclass
_name
;
u32
oclass
;
u32
handle
;
struct
nvkm_object
*
parent
;
struct
nvkm_oclass
*
oclass
;
u32
pclass
;
atomic_t
refcount
;
atomic_t
usecount
;
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
#define NVKM_OBJECT_MAGIC 0x75ef0bad
struct
list_head
list
;
u32
_magic
;
#endif
};
struct
nvkm_object_func
{
...
...
@@ -71,32 +57,6 @@ int nvkm_object_wr32(struct nvkm_object *, u64 addr, u32 data);
int
nvkm_object_bind
(
struct
nvkm_object
*
,
struct
nvkm_gpuobj
*
,
int
align
,
struct
nvkm_gpuobj
**
);
static
inline
struct
nvkm_object
*
nv_object
(
void
*
obj
)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
if
(
likely
(
obj
))
{
struct
nvkm_object
*
object
=
obj
;
BUG_ON
(
object
->
_magic
!=
NVKM_OBJECT_MAGIC
);
}
#endif
return
obj
;
}
#define nvkm_object_create(p,e,c,s,d) \
nvkm_object_create_((p), (e), (c), (s), sizeof(**d), (void **)d)
int
nvkm_object_create_
(
struct
nvkm_object
*
,
struct
nvkm_object
*
,
struct
nvkm_oclass
*
,
u32
,
int
size
,
void
**
);
void
nvkm_object_destroy
(
struct
nvkm_object
*
);
int
_nvkm_object_init
(
struct
nvkm_object
*
);
int
_nvkm_object_fini
(
struct
nvkm_object
*
,
bool
suspend
);
int
_nvkm_object_ctor
(
struct
nvkm_object
*
,
struct
nvkm_object
*
,
struct
nvkm_oclass
*
,
void
*
,
u32
,
struct
nvkm_object
**
);
extern
struct
nvkm_ofuncs
nvkm_object_ofuncs
;
struct
nvkm_sclass
{
int
minver
;
int
maxver
;
...
...
@@ -107,60 +67,18 @@ struct nvkm_sclass {
};
struct
nvkm_oclass
{
s32
handle
;
struct
nvkm_ofuncs
*
const
ofuncs
;
int
(
*
ctor
)(
const
struct
nvkm_oclass
*
,
void
*
data
,
u32
size
,
struct
nvkm_object
**
);
struct
nvkm_sclass
base
;
const
void
*
priv
;
const
void
*
engn
;
s32
handle
;
u64
object
;
struct
nvkm_client
*
client
;
struct
nvkm_object
*
parent
;
struct
nvkm_engine
*
engine
;
};
#define nv_oclass(o) nv_object(o)->oclass
#define nv_hclass(o) nv_oclass(o)->handle
#define nv_iclass(o,i) (nv_object(o)->pclass & (i))
#define nv_mclass(o) nv_oclass(o)->handle
static
inline
struct
nvkm_object
*
nv_pclass
(
struct
nvkm_object
*
parent
,
u32
oclass
)
{
while
(
parent
&&
!
nv_iclass
(
parent
,
oclass
))
parent
=
parent
->
parent
;
return
parent
;
}
struct
nvkm_ofuncs
{
int
(
*
ctor
)(
struct
nvkm_object
*
,
struct
nvkm_object
*
,
struct
nvkm_oclass
*
,
void
*
data
,
u32
size
,
struct
nvkm_object
**
);
void
(
*
dtor
)(
struct
nvkm_object
*
);
int
(
*
init
)(
struct
nvkm_object
*
);
int
(
*
fini
)(
struct
nvkm_object
*
,
bool
suspend
);
int
(
*
mthd
)(
struct
nvkm_object
*
,
u32
,
void
*
,
u32
);
int
(
*
ntfy
)(
struct
nvkm_object
*
,
u32
,
struct
nvkm_event
**
);
int
(
*
map
)(
struct
nvkm_object
*
,
u64
*
,
u32
*
);
u8
(
*
rd08
)(
struct
nvkm_object
*
,
u64
offset
);
u16
(
*
rd16
)(
struct
nvkm_object
*
,
u64
offset
);
u32
(
*
rd32
)(
struct
nvkm_object
*
,
u64
offset
);
void
(
*
wr08
)(
struct
nvkm_object
*
,
u64
offset
,
u8
data
);
void
(
*
wr16
)(
struct
nvkm_object
*
,
u64
offset
,
u16
data
);
void
(
*
wr32
)(
struct
nvkm_object
*
,
u64
offset
,
u32
data
);
};
static
inline
struct
nvkm_ofuncs
*
nv_ofuncs
(
void
*
obj
)
{
return
nv_oclass
(
obj
)
->
ofuncs
;
}
int
nvkm_object_old
(
struct
nvkm_object
*
,
struct
nvkm_object
*
,
struct
nvkm_oclass
*
,
void
*
,
u32
,
struct
nvkm_object
**
);
void
nvkm_object_ref
(
struct
nvkm_object
*
,
struct
nvkm_object
**
);
int
nvkm_object_inc
(
struct
nvkm_object
*
);
int
nvkm_object_dec
(
struct
nvkm_object
*
,
bool
suspend
);
...
...
drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
View file @
68f3f702
#ifndef __NVKM_SUBDEV_H__
#define __NVKM_SUBDEV_H__
#include <core/object.h>
#define NV_SUBDEV_(sub,var) (((var) << 8) | (sub))
#define NV_SUBDEV(name,var) NV_SUBDEV_(NVDEV_SUBDEV_##name, (var))
#include <core/device.h>
struct
nvkm_subdev
{
struct
nvkm_object
object
;
const
struct
nvkm_subdev_func
*
func
;
struct
nvkm_device
*
device
;
int
index
;
enum
nvkm_devidx
index
;
u32
pmc_enable
;
struct
mutex
mutex
;
u32
debug
;
bool
oneinit
;
void
(
*
intr
)(
struct
nvkm_subdev
*
);
u32
unit
;
bool
oneinit
;
};
struct
nvkm_subdev_func
{
...
...
@@ -29,7 +22,7 @@ struct nvkm_subdev_func {
void
(
*
intr
)(
struct
nvkm_subdev
*
);
};
extern
const
char
*
nvkm_subdev_name
[
64
];
extern
const
char
*
nvkm_subdev_name
[
NVKM_SUBDEV_NR
];
void
nvkm_subdev_ctor
(
const
struct
nvkm_subdev_func
*
,
struct
nvkm_device
*
,
int
index
,
u32
pmc_enable
,
struct
nvkm_subdev
*
);
void
nvkm_subdev_del
(
struct
nvkm_subdev
**
);
...
...
@@ -38,40 +31,6 @@ int nvkm_subdev_init(struct nvkm_subdev *);
int
nvkm_subdev_fini
(
struct
nvkm_subdev
*
,
bool
suspend
);
void
nvkm_subdev_intr
(
struct
nvkm_subdev
*
);
static
inline
struct
nvkm_subdev
*
nv_subdev
(
void
*
obj
)
{
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
BUG_ON
(
!
nv_iclass
(
obj
,
NV_SUBDEV_CLASS
));
#endif
return
obj
;
}
static
inline
int
nv_subidx
(
struct
nvkm_subdev
*
subdev
)
{
return
nv_hclass
(
subdev
)
&
0xff
;
}
struct
nvkm_subdev
*
nvkm_subdev
(
void
*
obj
,
int
idx
);
#define nvkm_subdev_create(p,e,o,v,s,f,d) \
nvkm_subdev_create_((p), (e), (o), (v), (s), (f), \
sizeof(**d),(void **)d)
int
nvkm_subdev_create_
(
struct
nvkm_object
*
,
struct
nvkm_object
*
,
struct
nvkm_oclass
*
,
u32
pclass
,
const
char
*
sname
,
const
char
*
fname
,
int
size
,
void
**
);
void
nvkm_subdev_destroy
(
struct
nvkm_subdev
*
);
int
nvkm_subdev_init_old
(
struct
nvkm_subdev
*
);
int
nvkm_subdev_fini_old
(
struct
nvkm_subdev
*
,
bool
suspend
);
void
nvkm_subdev_reset
(
struct
nvkm_object
*
);
void
_nvkm_subdev_dtor
(
struct
nvkm_object
*
);
int
_nvkm_subdev_init
(
struct
nvkm_object
*
);
int
_nvkm_subdev_fini
(
struct
nvkm_object
*
,
bool
suspend
);
/* subdev logging */
#define nvkm_printk_(s,l,p,f,a...) do { \
struct nvkm_subdev *_subdev = (s); \
...
...
@@ -88,6 +47,4 @@ int _nvkm_subdev_fini(struct nvkm_object *, bool suspend);
#define nvkm_debug(s,f,a...) nvkm_printk((s), DEBUG, info, f, ##a)
#define nvkm_trace(s,f,a...) nvkm_printk((s), TRACE, info, f, ##a)
#define nvkm_spam(s,f,a...) nvkm_printk((s), SPAM, dbg, f, ##a)
#include <core/engine.h>
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
View file @
68f3f702
...
...
@@ -26,11 +26,9 @@ struct nvkm_fifo_chan {
u64
addr
;
u32
size
;
struct
nvkm_fifo_engn
engn
[
NV
DEV
_SUBDEV_NR
];
struct
nvkm_fifo_engn
engn
[
NV
KM
_SUBDEV_NR
];
};
extern
const
struct
nvkm_object_func
nvkm_fifo_chan_func
;
struct
nvkm_fifo
{
const
struct
nvkm_fifo_func
*
func
;
struct
nvkm_engine
engine
;
...
...
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
View file @
68f3f702
...
...
@@ -32,7 +32,7 @@ struct nvkm_vm {
struct
kref
refcount
;
struct
list_head
pgd_list
;
atomic_t
engref
[
NV
DEV
_SUBDEV_NR
];
atomic_t
engref
[
NV
KM
_SUBDEV_NR
];
struct
nvkm_vm_pgt
*
pgt
;
u32
fpde
;
...
...
drivers/gpu/drm/nouveau/nvkm/core/engine.c
View file @
68f3f702
...
...
@@ -67,29 +67,26 @@ nvkm_engine_tile(struct nvkm_engine *engine, int region)
}
static
void
nvkm_engine_intr
(
struct
nvkm_subdev
*
obj
)
nvkm_engine_intr
(
struct
nvkm_subdev
*
subdev
)
{
struct
nvkm_engine
*
engine
=
container_of
(
obj
,
typeof
(
*
engine
),
subdev
);
struct
nvkm_engine
*
engine
=
nvkm_engine
(
subdev
);
if
(
engine
->
func
->
intr
)
engine
->
func
->
intr
(
engine
);
}
static
int
nvkm_engine_fini
(
struct
nvkm_subdev
*
obj
,
bool
suspend
)
nvkm_engine_fini
(
struct
nvkm_subdev
*
subdev
,
bool
suspend
)
{
struct
nvkm_engine
*
engine
=
container_of
(
obj
,
typeof
(
*
engine
),
subdev
);
if
(
engine
->
subdev
.
object
.
oclass
)
return
engine
->
subdev
.
object
.
oclass
->
ofuncs
->
fini
(
&
engine
->
subdev
.
object
,
suspend
);
struct
nvkm_engine
*
engine
=
nvkm_engine
(
subdev
);
if
(
engine
->
func
->
fini
)
return
engine
->
func
->
fini
(
engine
,
suspend
);
return
0
;
}
static
int
nvkm_engine_init
(
struct
nvkm_subdev
*
obj
)
nvkm_engine_init
(
struct
nvkm_subdev
*
subdev
)
{
struct
nvkm_engine
*
engine
=
container_of
(
obj
,
typeof
(
*
engine
),
subdev
);
struct
nvkm_subdev
*
subdev
=
&
engine
->
subdev
;
struct
nvkm_engine
*
engine
=
nvkm_engine
(
subdev
);
struct
nvkm_fb
*
fb
=
subdev
->
device
->
fb
;
int
ret
=
0
,
i
;
s64
time
;
...
...
@@ -99,9 +96,6 @@ nvkm_engine_init(struct nvkm_subdev *obj)
return
ret
;
}
if
(
engine
->
subdev
.
object
.
oclass
)
return
engine
->
subdev
.
object
.
oclass
->
ofuncs
->
init
(
&
engine
->
subdev
.
object
);
if
(
engine
->
func
->
oneinit
&&
!
engine
->
subdev
.
oneinit
)
{
nvkm_trace
(
subdev
,
"one-time init running...
\n
"
);
time
=
ktime_to_us
(
ktime_get
());
...
...
@@ -125,13 +119,9 @@ nvkm_engine_init(struct nvkm_subdev *obj)
}
static
void
*
nvkm_engine_dtor
(
struct
nvkm_subdev
*
obj
)
nvkm_engine_dtor
(
struct
nvkm_subdev
*
subdev
)
{
struct
nvkm_engine
*
engine
=
container_of
(
obj
,
typeof
(
*
engine
),
subdev
);
if
(
engine
->
subdev
.
object
.
oclass
)
{
engine
->
subdev
.
object
.
oclass
->
ofuncs
->
dtor
(
&
engine
->
subdev
.
object
);
return
NULL
;
}
struct
nvkm_engine
*
engine
=
nvkm_engine
(
subdev
);
if
(
engine
->
func
->
dtor
)
return
engine
->
func
->
dtor
(
engine
);
return
engine
;
...
...
@@ -173,56 +163,3 @@ nvkm_engine_new_(const struct nvkm_engine_func *func,
return
nvkm_engine_ctor
(
func
,
device
,
index
,
pmc_enable
,
enable
,
*
pengine
);
}
struct
nvkm_engine
*
nvkm_engine
(
void
*
obj
,
int
idx
)
{
obj
=
nvkm_subdev
(
obj
,
idx
);
if
(
obj
&&
nv_iclass
(
obj
,
NV_ENGINE_CLASS
))
return
nv_engine
(
obj
);
return
NULL
;
}
int
nvkm_engine_create_
(
struct
nvkm_object
*
parent
,
struct
nvkm_object
*
engobj
,
struct
nvkm_oclass
*
oclass
,
bool
enable
,
const
char
*
iname
,
const
char
*
fname
,
int
length
,
void
**
pobject
)
{
struct
nvkm_engine
*
engine
;
int
ret
;
ret
=
nvkm_subdev_create_
(
parent
,
engobj
,
oclass
,
NV_ENGINE_CLASS
,
iname
,
fname
,
length
,
pobject
);
engine
=
*
pobject
;
if
(
ret
)
return
ret
;
if
(
parent
)
{
struct
nvkm_device
*
device
=
nv_device
(
parent
);
int
engidx
=
nv_engidx
(
engine
);
if
(
device
->
disable_mask
&
(
1ULL
<<
engidx
))
{
if
(
!
nvkm_boolopt
(
device
->
cfgopt
,
iname
,
false
))
{
nvkm_debug
(
&
engine
->
subdev
,
"engine disabled by hw/fw
\n
"
);
return
-
ENODEV
;
}
nvkm_warn
(
&
engine
->
subdev
,
"ignoring hw/fw engine disable
\n
"
);
}
if
(
!
nvkm_boolopt
(
device
->
cfgopt
,
iname
,
enable
))
{
if
(
!
enable
)
nvkm_warn
(
&
engine
->
subdev
,
"disabled, %s=1 to enable
\n
"
,
iname
);
return
-
ENODEV
;
}
}
INIT_LIST_HEAD
(
&
engine
->
contexts
);
spin_lock_init
(
&
engine
->
lock
);
engine
->
subdev
.
func
=
&
nvkm_engine_func
;
return
0
;
}
drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
View file @
68f3f702
...
...
@@ -218,99 +218,6 @@ nvkm_gpuobj_new(struct nvkm_device *device, u32 size, int align, bool zero,
return
ret
;
}
void
nvkm_gpuobj_destroy
(
struct
nvkm_gpuobj
*
gpuobj
)
{
if
(
gpuobj
->
node
)
nvkm_mm_free
(
&
gpuobj
->
parent
->
heap
,
&
gpuobj
->
node
);
gpuobj
->
heap
.
block_size
=
1
;
nvkm_mm_fini
(
&
gpuobj
->
heap
);
nvkm_memory_del
(
&
gpuobj
->
memory
);
nvkm_object_destroy
(
&
gpuobj
->
object
);
}
#include <engine/fifo/chan.h>
int
nvkm_gpuobj_create_
(
struct
nvkm_object
*
parent
,
struct
nvkm_object
*
engine
,
struct
nvkm_oclass
*
oclass
,
u32
pclass
,
struct
nvkm_object
*
objgpu
,
u32
size
,
u32
align
,
u32
flags
,
int
length
,
void
**
pobject
)
{
struct
nvkm_device
*
device
=
nv_device
(
parent
);
struct
nvkm_gpuobj
*
pargpu
=
NULL
;
struct
nvkm_gpuobj
*
gpuobj
;
struct
nvkm_object
*
object
=
objgpu
;
const
bool
zero
=
(
flags
&
NVOBJ_FLAG_ZERO_ALLOC
);
int
ret
;
*
pobject
=
NULL
;
while
(
object
&&
object
->
func
!=
&
nvkm_fifo_chan_func
)
object
=
object
->
parent
;
if
(
object
)
{
struct
nvkm_fifo_chan
*
chan
=
nvkm_fifo_chan
(
object
);
pargpu
=
chan
->
inst
;
}
else
if
(
objgpu
)
{
while
((
objgpu
=
nv_pclass
(
objgpu
,
NV_GPUOBJ_CLASS
)))
{
if
(
nv_gpuobj
(
objgpu
)
->
heap
.
block_size
)
break
;
objgpu
=
objgpu
->
parent
;
}
if
(
WARN_ON
(
objgpu
==
NULL
))
return
-
EINVAL
;
pargpu
=
nv_gpuobj
(
objgpu
);
}
ret
=
nvkm_object_create_
(
parent
,
engine
,
oclass
,
pclass
|
NV_GPUOBJ_CLASS
,
length
,
pobject
);
gpuobj
=
*
pobject
;
if
(
ret
)
return
ret
;
ret
=
nvkm_gpuobj_ctor
(
device
,
size
,
align
,
zero
,
pargpu
,
gpuobj
);
if
(
!
(
flags
&
NVOBJ_FLAG_HEAP
))
gpuobj
->
heap
.
block_size
=
0
;
return
ret
;
}
void
_nvkm_gpuobj_dtor
(
struct
nvkm_object
*
object
)
{
nvkm_gpuobj_destroy
(
nv_gpuobj
(
object
));
}
int
_nvkm_gpuobj_init
(
struct
nvkm_object
*
object
)
{
return
nvkm_gpuobj_init
(
nv_gpuobj
(
object
));
}
int
_nvkm_gpuobj_fini
(
struct
nvkm_object
*
object
,
bool
suspend
)
{
return
nvkm_gpuobj_fini
(
nv_gpuobj
(
object
),
suspend
);
}
u32
_nvkm_gpuobj_rd32
(
struct
nvkm_object
*
object
,
u64
addr
)
{
struct
nvkm_gpuobj
*
gpuobj
=
nv_gpuobj
(
object
);
return
nvkm_ro32
(
gpuobj
,
addr
);
}
void
_nvkm_gpuobj_wr32
(
struct
nvkm_object
*
object
,
u64
addr
,
u32
data
)
{
struct
nvkm_gpuobj
*
gpuobj
=
nv_gpuobj
(
object
);
nvkm_wo32
(
gpuobj
,
addr
,
data
);
}
int
nvkm_gpuobj_map
(
struct
nvkm_gpuobj
*
gpuobj
,
struct
nvkm_vm
*
vm
,
u32
access
,
struct
nvkm_vma
*
vma
)
...
...
drivers/gpu/drm/nouveau/nvkm/core/object.c
View file @
68f3f702
...
...
@@ -27,11 +27,6 @@
int
nvkm_object_mthd
(
struct
nvkm_object
*
object
,
u32
mthd
,
void
*
data
,
u32
size
)
{
if
(
object
->
oclass
)
{
if
(
object
->
oclass
->
ofuncs
->
mthd
)
return
object
->
oclass
->
ofuncs
->
mthd
(
object
,
mthd
,
data
,
size
);
return
-
ENODEV
;
}
if
(
likely
(
object
->
func
->
mthd
))
return
object
->
func
->
mthd
(
object
,
mthd
,
data
,
size
);
return
-
ENODEV
;
...
...
@@ -41,11 +36,6 @@ int
nvkm_object_ntfy
(
struct
nvkm_object
*
object
,
u32
mthd
,
struct
nvkm_event
**
pevent
)
{
if
(
object
->
oclass
)
{
if
(
object
->
oclass
->
ofuncs
->
ntfy
)
return
object
->
oclass
->
ofuncs
->
ntfy
(
object
,
mthd
,
pevent
);
return
-
ENODEV
;
}
if
(
likely
(
object
->
func
->
ntfy
))
return
object
->
func
->
ntfy
(
object
,
mthd
,
pevent
);
return
-
ENODEV
;
...
...
@@ -54,11 +44,6 @@ nvkm_object_ntfy(struct nvkm_object *object, u32 mthd,
int
nvkm_object_map
(
struct
nvkm_object
*
object
,
u64
*
addr
,
u32
*
size
)
{
if
(
object
->
oclass
)
{
if
(
object
->
oclass
->
ofuncs
->
map
)
return
object
->
oclass
->
ofuncs
->
map
(
object
,
addr
,
size
);
return
-
ENODEV
;
}
if
(
likely
(
object
->
func
->
map
))
return
object
->
func
->
map
(
object
,
addr
,
size
);
return
-
ENODEV
;
...
...
@@ -67,14 +52,6 @@ nvkm_object_map(struct nvkm_object *object, u64 *addr, u32 *size)
int
nvkm_object_rd08
(
struct
nvkm_object
*
object
,
u64
addr
,
u8
*
data
)
{
if
(
object
->
oclass
)
{
if
(
object
->
oclass
->
ofuncs
->
rd08
)
{
*
data
=
object
->
oclass
->
ofuncs
->
rd08
(
object
,
addr
);
return
0
;
}
*
data
=
0x00
;
return
-
ENODEV
;
}
if
(
likely
(
object
->
func
->
rd08
))
return
object
->
func
->
rd08
(
object
,
addr
,
data
);
return
-
ENODEV
;
...
...
@@ -83,14 +60,6 @@ nvkm_object_rd08(struct nvkm_object *object, u64 addr, u8 *data)
int
nvkm_object_rd16
(
struct
nvkm_object
*
object
,
u64
addr
,
u16
*
data
)
{
if
(
object
->
oclass
)
{
if
(
object
->
oclass
->
ofuncs
->
rd16
)
{
*
data
=
object
->
oclass
->
ofuncs
->
rd16
(
object
,
addr
);
return
0
;
}
*
data
=
0x0000
;
return
-
ENODEV
;
}
if
(
likely
(
object
->
func
->
rd16
))
return
object
->
func
->
rd16
(
object
,
addr
,
data
);
return
-
ENODEV
;
...
...
@@ -99,14 +68,6 @@ nvkm_object_rd16(struct nvkm_object *object, u64 addr, u16 *data)
int
nvkm_object_rd32
(
struct
nvkm_object
*
object
,
u64
addr
,
u32
*
data
)
{
if
(
object
->
oclass
)
{
if
(
object
->
oclass
->
ofuncs
->
rd32
)
{
*
data
=
object
->
oclass
->
ofuncs
->
rd32
(
object
,
addr
);
return
0
;
}
*
data
=
0x00000000
;
return
-
ENODEV
;
}
if
(
likely
(
object
->
func
->
rd32
))
return
object
->
func
->
rd32
(
object
,
addr
,
data
);
return
-
ENODEV
;
...
...
@@ -115,13 +76,6 @@ nvkm_object_rd32(struct nvkm_object *object, u64 addr, u32 *data)
int
nvkm_object_wr08
(
struct
nvkm_object
*
object
,
u64
addr
,
u8
data
)
{
if
(
object
->
oclass
)
{
if
(
object
->
oclass
->
ofuncs
->
wr08
)
{
object
->
oclass
->
ofuncs
->
wr08
(
object
,
addr
,
data
);
return
0
;
}
return
-
ENODEV
;
}
if
(
likely
(
object
->
func
->
wr08
))
return
object
->
func
->
wr08
(
object
,
addr
,
data
);
return
-
ENODEV
;
...
...
@@ -130,13 +84,6 @@ nvkm_object_wr08(struct nvkm_object *object, u64 addr, u8 data)
int
nvkm_object_wr16
(
struct
nvkm_object
*
object
,
u64
addr
,
u16
data
)
{
if
(
object
->
oclass
)
{
if
(
object
->
oclass
->
ofuncs
->
wr16
)
{
object
->
oclass
->
ofuncs
->
wr16
(
object
,
addr
,
data
);
return
0
;
}
return
-
ENODEV
;
}
if
(
likely
(
object
->
func
->
wr16
))
return
object
->
func
->
wr16
(
object
,
addr
,
data
);
return
-
ENODEV
;
...
...
@@ -145,13 +92,6 @@ nvkm_object_wr16(struct nvkm_object *object, u64 addr, u16 data)
int
nvkm_object_wr32
(
struct
nvkm_object
*
object
,
u64
addr
,
u32
data
)
{
if
(
object
->
oclass
)
{
if
(
object
->
oclass
->
ofuncs
->
wr32
)
{
object
->
oclass
->
ofuncs
->
wr32
(
object
,
addr
,
data
);
return
0
;
}
return
-
ENODEV
;
}
if
(
likely
(
object
->
func
->
wr32
))
return
object
->
func
->
wr32
(
object
,
addr
,
data
);
return
-
ENODEV
;
...
...
@@ -161,8 +101,6 @@ int
nvkm_object_bind
(
struct
nvkm_object
*
object
,
struct
nvkm_gpuobj
*
gpuobj
,
int
align
,
struct
nvkm_gpuobj
**
pgpuobj
)
{
if
(
object
->
oclass
)
return
-
ENODEV
;
if
(
object
->
func
->
bind
)
return
object
->
func
->
bind
(
object
,
gpuobj
,
align
,
pgpuobj
);
return
-
ENODEV
;
...
...
@@ -171,8 +109,6 @@ nvkm_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *gpuobj,
int
nvkm_object_fini
(
struct
nvkm_object
*
object
,
bool
suspend
)
{
if
(
object
->
oclass
)
return
object
->
oclass
->
ofuncs
->
fini
(
object
,
suspend
);
if
(
object
->
func
->
fini
)
return
object
->
func
->
fini
(
object
,
suspend
);
return
0
;
...
...
@@ -181,8 +117,6 @@ nvkm_object_fini(struct nvkm_object *object, bool suspend)
int
nvkm_object_init
(
struct
nvkm_object
*
object
)
{
if
(
object
->
oclass
)
return
object
->
oclass
->
ofuncs
->
init
(
object
);
if
(
object
->
func
->
init
)
return
object
->
func
->
init
(
object
);
return
0
;
...
...
@@ -193,11 +127,6 @@ nvkm_object_del(struct nvkm_object **pobject)
{
struct
nvkm_object
*
object
=
*
pobject
;
if
(
object
&&
object
->
oclass
)
{
object
->
oclass
->
ofuncs
->
dtor
(
object
);
return
;
}
if
(
object
&&
!
WARN_ON
(
!
object
->
func
))
{
if
(
object
->
func
->
dtor
)
*
pobject
=
object
->
func
->
dtor
(
object
);
...
...
@@ -214,14 +143,11 @@ nvkm_object_ctor(const struct nvkm_object_func *func,
object
->
func
=
func
;
object
->
client
=
oclass
->
client
;
object
->
engine
=
nvkm_engine_ref
(
oclass
->
engine
);
object
->
oclass
_name
=
oclass
->
base
.
oclass
;
object
->
oclass
=
oclass
->
base
.
oclass
;
object
->
handle
=
oclass
->
handle
;
object
->
parent
=
oclass
->
parent
;
atomic_set
(
&
object
->
refcount
,
1
);
atomic_set
(
&
object
->
usecount
,
0
);
#ifdef NVKM_OBJECT_MAGIC
object
->
_magic
=
NVKM_OBJECT_MAGIC
;
#endif
}
int
...
...
@@ -251,97 +177,6 @@ nvkm_object_new(const struct nvkm_oclass *oclass, void *data, u32 size,
return
nvkm_object_new_
(
func
,
oclass
,
data
,
size
,
pobject
);
}
int
nvkm_object_create_
(
struct
nvkm_object
*
parent
,
struct
nvkm_object
*
engobj
,
struct
nvkm_oclass
*
oclass
,
u32
pclass
,
int
size
,
void
**
pobject
)
{
struct
nvkm_engine
*
engine
=
engobj
?
nv_engine
(
engobj
)
:
NULL
;
struct
nvkm_object
*
object
;
object
=
*
pobject
=
kzalloc
(
size
,
GFP_KERNEL
);
if
(
!
object
)
return
-
ENOMEM
;
nvkm_object_ref
(
parent
,
&
object
->
parent
);
object
->
engine
=
nvkm_engine_ref
(
engine
);
object
->
oclass
=
oclass
;
object
->
pclass
=
pclass
;
atomic_set
(
&
object
->
refcount
,
1
);
atomic_set
(
&
object
->
usecount
,
0
);
#ifdef NVKM_OBJECT_MAGIC
object
->
_magic
=
NVKM_OBJECT_MAGIC
;
#endif
return
0
;
}
int
_nvkm_object_ctor
(
struct
nvkm_object
*
parent
,
struct
nvkm_object
*
engine
,
struct
nvkm_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nvkm_object
**
pobject
)
{
if
(
size
!=
0
)
return
-
ENOSYS
;
return
nvkm_object_create
(
parent
,
engine
,
oclass
,
0
,
pobject
);
}
void
nvkm_object_destroy
(
struct
nvkm_object
*
object
)
{
nvkm_engine_unref
(
&
object
->
engine
);
nvkm_object_ref
(
NULL
,
&
object
->
parent
);
kfree
(
object
);
}
int
_nvkm_object_init
(
struct
nvkm_object
*
object
)
{
return
0
;
}
int
_nvkm_object_fini
(
struct
nvkm_object
*
object
,
bool
suspend
)
{
return
0
;
}
struct
nvkm_ofuncs
nvkm_object_ofuncs
=
{
.
ctor
=
_nvkm_object_ctor
,
.
dtor
=
nvkm_object_destroy
,
.
init
=
_nvkm_object_init
,
.
fini
=
_nvkm_object_fini
,
};
int
nvkm_object_old
(
struct
nvkm_object
*
parent
,
struct
nvkm_object
*
engine
,
struct
nvkm_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nvkm_object
**
pobject
)
{
struct
nvkm_ofuncs
*
ofuncs
=
oclass
->
ofuncs
;
struct
nvkm_object
*
object
=
NULL
;
int
ret
;
ret
=
ofuncs
->
ctor
(
parent
,
engine
,
oclass
,
data
,
size
,
&
object
);
*
pobject
=
object
;
if
(
ret
<
0
)
{
if
(
object
)
{
ofuncs
->
dtor
(
object
);
*
pobject
=
NULL
;
}
return
ret
;
}
if
(
ret
==
0
)
{
if
(
!
nv_iclass
(
object
,
NV_SUBDEV_CLASS
))
atomic_set
(
&
object
->
refcount
,
1
);
}
return
0
;
}
void
nvkm_object_ref
(
struct
nvkm_object
*
obj
,
struct
nvkm_object
**
ref
)
{
...
...
drivers/gpu/drm/nouveau/nvkm/core/oproxy.c
View file @
68f3f702
...
...
@@ -92,8 +92,6 @@ nvkm_oproxy_sclass(struct nvkm_object *object, int index,
{
struct
nvkm_oproxy
*
oproxy
=
nvkm_oproxy
(
object
);
oclass
->
parent
=
oproxy
->
object
;
if
(
oproxy
->
object
->
oclass
)
return
-
ENOSYS
;
if
(
!
oproxy
->
object
->
func
->
sclass
)
return
-
ENODEV
;
return
oproxy
->
object
->
func
->
sclass
(
oproxy
->
object
,
index
,
oclass
);
...
...
drivers/gpu/drm/nouveau/nvkm/core/ramht.c
View file @
68f3f702
...
...
@@ -67,20 +67,7 @@ nvkm_ramht_update(struct nvkm_ramht *ramht, int co, struct nvkm_object *object,
data
->
chid
=
chid
;
data
->
handle
=
handle
;
if
(
!
object
)
{
inst
=
0
;
goto
done
;
}
if
(
nv_iclass
(
object
,
NV_GPUOBJ_CLASS
))
{
struct
nvkm_gpuobj
*
gpuobj
=
nv_gpuobj
(
object
);
if
(
ramht
->
device
->
card_type
>=
NV_50
)
inst
=
gpuobj
->
node
->
offset
;
else
inst
=
gpuobj
->
addr
;
goto
done
;
}
if
(
object
)
{
ret
=
nvkm_object_bind
(
object
,
ramht
->
parent
,
16
,
&
data
->
inst
);
if
(
ret
)
{
if
(
ret
!=
-
ENODEV
)
{
...
...
@@ -97,9 +84,9 @@ nvkm_ramht_update(struct nvkm_ramht *ramht, int co, struct nvkm_object *object,
inst
=
data
->
inst
->
addr
;
}
done:
if
(
addr
<
0
)
context
|=
inst
<<
-
addr
;
else
context
|=
inst
>>
addr
;
}
nvkm_kmap
(
ramht
->
gpuobj
);
nvkm_wo32
(
ramht
->
gpuobj
,
(
co
<<
3
)
+
0
,
handle
);
...
...
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
View file @
68f3f702
...
...
@@ -25,61 +25,55 @@
#include <core/device.h>
#include <core/option.h>
static
struct
lock_class_key
nvkm_subdev_lock_class
[
NV
DEV
_SUBDEV_NR
];
static
struct
lock_class_key
nvkm_subdev_lock_class
[
NV
KM
_SUBDEV_NR
];
const
char
*
nvkm_subdev_name
[
64
]
=
{
[
NV
DEV
_SUBDEV_BAR
]
=
"bar"
,
[
NV
DEV
_SUBDEV_VBIOS
]
=
"bios"
,
[
NV
DEV
_SUBDEV_BUS
]
=
"bus"
,
[
NV
DEV
_SUBDEV_CLK
]
=
"clk"
,
[
NV
DEV
_SUBDEV_DEVINIT
]
=
"devinit"
,
[
NV
DEV
_SUBDEV_FB
]
=
"fb"
,
[
NV
DEV
_SUBDEV_FUSE
]
=
"fuse"
,
[
NV
DEV
_SUBDEV_GPIO
]
=
"gpio"
,
[
NV
DEV
_SUBDEV_I2C
]
=
"i2c"
,
[
NV
DEV
_SUBDEV_IBUS
]
=
"priv"
,
[
NV
DEV
_SUBDEV_INSTMEM
]
=
"imem"
,
[
NV
DEV
_SUBDEV_LTC
]
=
"ltc"
,
[
NV
DEV
_SUBDEV_MC
]
=
"mc"
,
[
NV
DEV
_SUBDEV_MMU
]
=
"mmu"
,
[
NV
DEV
_SUBDEV_MXM
]
=
"mxm"
,
[
NV
DEV
_SUBDEV_PMU
]
=
"pmu"
,
[
NV
DEV
_SUBDEV_THERM
]
=
"therm"
,
[
NV
DEV
_SUBDEV_TIMER
]
=
"tmr"
,
[
NV
DEV
_SUBDEV_VOLT
]
=
"volt"
,
[
NV
DEV
_ENGINE_BSP
]
=
"bsp"
,
[
NV
DEV
_ENGINE_CE0
]
=
"ce0"
,
[
NV
DEV
_ENGINE_CE1
]
=
"ce1"
,
[
NV
DEV
_ENGINE_CE2
]
=
"ce2"
,
[
NV
DEV
_ENGINE_CIPHER
]
=
"cipher"
,
[
NV
DEV
_ENGINE_DISP
]
=
"disp"
,
[
NV
DEV
_ENGINE_DMAOBJ
]
=
"dma"
,
[
NV
DEV
_ENGINE_FIFO
]
=
"fifo"
,
[
NV
DEV
_ENGINE_GR
]
=
"gr"
,
[
NV
DEV
_ENGINE_IFB
]
=
"ifb"
,
[
NV
DEV
_ENGINE_ME
]
=
"me"
,
[
NV
DEV
_ENGINE_MPEG
]
=
"mpeg"
,
[
NV
DEV
_ENGINE_MSENC
]
=
"msenc"
,
[
NV
DEV
_ENGINE_MSPDEC
]
=
"mspdec"
,
[
NV
DEV
_ENGINE_MSPPP
]
=
"msppp"
,
[
NV
DEV
_ENGINE_MSVLD
]
=
"msvld"
,
[
NV
DEV
_ENGINE_PM
]
=
"pm"
,
[
NV
DEV
_ENGINE_SEC
]
=
"sec"
,
[
NV
DEV
_ENGINE_SW
]
=
"sw"
,
[
NV
DEV
_ENGINE_VIC
]
=
"vic"
,
[
NV
DEV
_ENGINE_VP
]
=
"vp"
,
nvkm_subdev_name
[
NVKM_SUBDEV_NR
]
=
{
[
NV
KM
_SUBDEV_BAR
]
=
"bar"
,
[
NV
KM
_SUBDEV_VBIOS
]
=
"bios"
,
[
NV
KM
_SUBDEV_BUS
]
=
"bus"
,
[
NV
KM
_SUBDEV_CLK
]
=
"clk"
,
[
NV
KM
_SUBDEV_DEVINIT
]
=
"devinit"
,
[
NV
KM
_SUBDEV_FB
]
=
"fb"
,
[
NV
KM
_SUBDEV_FUSE
]
=
"fuse"
,
[
NV
KM
_SUBDEV_GPIO
]
=
"gpio"
,
[
NV
KM
_SUBDEV_I2C
]
=
"i2c"
,
[
NV
KM
_SUBDEV_IBUS
]
=
"priv"
,
[
NV
KM
_SUBDEV_INSTMEM
]
=
"imem"
,
[
NV
KM
_SUBDEV_LTC
]
=
"ltc"
,
[
NV
KM
_SUBDEV_MC
]
=
"mc"
,
[
NV
KM
_SUBDEV_MMU
]
=
"mmu"
,
[
NV
KM
_SUBDEV_MXM
]
=
"mxm"
,
[
NV
KM
_SUBDEV_PMU
]
=
"pmu"
,
[
NV
KM
_SUBDEV_THERM
]
=
"therm"
,
[
NV
KM
_SUBDEV_TIMER
]
=
"tmr"
,
[
NV
KM
_SUBDEV_VOLT
]
=
"volt"
,
[
NV
KM
_ENGINE_BSP
]
=
"bsp"
,
[
NV
KM
_ENGINE_CE0
]
=
"ce0"
,
[
NV
KM
_ENGINE_CE1
]
=
"ce1"
,
[
NV
KM
_ENGINE_CE2
]
=
"ce2"
,
[
NV
KM
_ENGINE_CIPHER
]
=
"cipher"
,
[
NV
KM
_ENGINE_DISP
]
=
"disp"
,
[
NV
KM
_ENGINE_DMAOBJ
]
=
"dma"
,
[
NV
KM
_ENGINE_FIFO
]
=
"fifo"
,
[
NV
KM
_ENGINE_GR
]
=
"gr"
,
[
NV
KM
_ENGINE_IFB
]
=
"ifb"
,
[
NV
KM
_ENGINE_ME
]
=
"me"
,
[
NV
KM
_ENGINE_MPEG
]
=
"mpeg"
,
[
NV
KM
_ENGINE_MSENC
]
=
"msenc"
,
[
NV
KM
_ENGINE_MSPDEC
]
=
"mspdec"
,
[
NV
KM
_ENGINE_MSPPP
]
=
"msppp"
,
[
NV
KM
_ENGINE_MSVLD
]
=
"msvld"
,
[
NV
KM
_ENGINE_PM
]
=
"pm"
,
[
NV
KM
_ENGINE_SEC
]
=
"sec"
,
[
NV
KM
_ENGINE_SW
]
=
"sw"
,
[
NV
KM
_ENGINE_VIC
]
=
"vic"
,
[
NV
KM
_ENGINE_VP
]
=
"vp"
,
};
void
nvkm_subdev_intr
(
struct
nvkm_subdev
*
subdev
)
{
if
(
subdev
->
object
.
oclass
)
{
if
(
subdev
->
intr
)
subdev
->
intr
(
subdev
);
return
;
}
if
(
subdev
->
func
->
intr
)
subdev
->
func
->
intr
(
subdev
);
}
...
...
@@ -91,18 +85,10 @@ nvkm_subdev_fini(struct nvkm_subdev *subdev, bool suspend)
const
char
*
action
=
suspend
?
"suspend"
:
"fini"
;
u32
pmc_enable
=
subdev
->
pmc_enable
;
s64
time
;
int
ret
;
nvkm_trace
(
subdev
,
"%s running...
\n
"
,
action
);
time
=
ktime_to_us
(
ktime_get
());
if
(
!
subdev
->
func
)
{
ret
=
subdev
->
object
.
oclass
->
ofuncs
->
fini
(
&
subdev
->
object
,
suspend
);
if
(
ret
)
return
ret
;
goto
done
;
}
if
(
subdev
->
func
->
fini
)
{
int
ret
=
subdev
->
func
->
fini
(
subdev
,
suspend
);
if
(
ret
)
{
...
...
@@ -118,7 +104,6 @@ nvkm_subdev_fini(struct nvkm_subdev *subdev, bool suspend)
nvkm_rd32
(
device
,
0x000200
);
}
done:
time
=
ktime_to_us
(
ktime_get
())
-
time
;
nvkm_trace
(
subdev
,
"%s completed in %lldus
\n
"
,
action
,
time
);
return
0
;
...
...
@@ -132,7 +117,7 @@ nvkm_subdev_preinit(struct nvkm_subdev *subdev)
nvkm_trace
(
subdev
,
"preinit running...
\n
"
);
time
=
ktime_to_us
(
ktime_get
());
if
(
!
subdev
->
object
.
oclass
&&
subdev
->
func
->
preinit
)
{
if
(
subdev
->
func
->
preinit
)
{
int
ret
=
subdev
->
func
->
preinit
(
subdev
);
if
(
ret
)
{
nvkm_error
(
subdev
,
"preinit failed, %d
\n
"
,
ret
);
...
...
@@ -154,13 +139,6 @@ nvkm_subdev_init(struct nvkm_subdev *subdev)
nvkm_trace
(
subdev
,
"init running...
\n
"
);
time
=
ktime_to_us
(
ktime_get
());
if
(
!
subdev
->
func
)
{
ret
=
subdev
->
object
.
oclass
->
ofuncs
->
init
(
&
subdev
->
object
);
if
(
ret
)
return
ret
;
goto
done
;
}
if
(
subdev
->
func
->
oneinit
&&
!
subdev
->
oneinit
)
{
s64
time
;
nvkm_trace
(
subdev
,
"one-time init running...
\n
"
);
...
...
@@ -184,7 +162,6 @@ nvkm_subdev_init(struct nvkm_subdev *subdev)
}
}
done:
time
=
ktime_to_us
(
ktime_get
())
-
time
;
nvkm_trace
(
subdev
,
"init completed in %lldus
\n
"
,
time
);
return
0
;
...
...
@@ -196,11 +173,6 @@ nvkm_subdev_del(struct nvkm_subdev **psubdev)
struct
nvkm_subdev
*
subdev
=
*
psubdev
;
s64
time
;
if
(
subdev
&&
subdev
->
object
.
oclass
)
{
subdev
->
object
.
oclass
->
ofuncs
->
dtor
(
&
subdev
->
object
);
return
;
}
if
(
subdev
&&
!
WARN_ON
(
!
subdev
->
func
))
{
nvkm_trace
(
subdev
,
"destroy running...
\n
"
);
time
=
ktime_to_us
(
ktime_get
());
...
...
@@ -213,18 +185,12 @@ nvkm_subdev_del(struct nvkm_subdev **psubdev)
}
}
static
const
struct
nvkm_object_func
nvkm_subdev_func
=
{
};
void
nvkm_subdev_ctor
(
const
struct
nvkm_subdev_func
*
func
,
struct
nvkm_device
*
device
,
int
index
,
u32
pmc_enable
,
struct
nvkm_subdev
*
subdev
)
{
const
char
*
name
=
nvkm_subdev_name
[
index
];
struct
nvkm_oclass
hack
=
{};
nvkm_object_ctor
(
&
nvkm_subdev_func
,
&
hack
,
&
subdev
->
object
);
subdev
->
func
=
func
;
subdev
->
device
=
device
;
subdev
->
index
=
index
;
...
...
@@ -233,106 +199,3 @@ nvkm_subdev_ctor(const struct nvkm_subdev_func *func,
__mutex_init
(
&
subdev
->
mutex
,
name
,
&
nvkm_subdev_lock_class
[
index
]);
subdev
->
debug
=
nvkm_dbgopt
(
device
->
dbgopt
,
name
);
}
struct
nvkm_subdev
*
nvkm_subdev
(
void
*
obj
,
int
idx
)
{
struct
nvkm_object
*
object
=
nv_object
(
obj
);
while
(
object
&&
!
nv_iclass
(
object
,
NV_SUBDEV_CLASS
))
object
=
object
->
parent
;
if
(
object
==
NULL
||
!
object
->
parent
||
nv_subidx
(
nv_subdev
(
object
))
!=
idx
)
{
struct
nvkm_device
*
device
=
nv_device
(
obj
);
return
nvkm_device_subdev
(
device
,
idx
);
}
return
object
?
nv_subdev
(
object
)
:
NULL
;
}
void
nvkm_subdev_reset
(
struct
nvkm_object
*
obj
)
{
struct
nvkm_subdev
*
subdev
=
container_of
(
obj
,
typeof
(
*
subdev
),
object
);
nvkm_trace
(
subdev
,
"resetting...
\n
"
);
nvkm_object_fini
(
&
subdev
->
object
,
false
);
nvkm_trace
(
subdev
,
"reset
\n
"
);
}
int
nvkm_subdev_init_old
(
struct
nvkm_subdev
*
subdev
)
{
int
ret
=
_nvkm_object_init
(
&
subdev
->
object
);
if
(
ret
)
return
ret
;
nvkm_subdev_reset
(
&
subdev
->
object
);
return
0
;
}
int
_nvkm_subdev_init
(
struct
nvkm_object
*
object
)
{
struct
nvkm_subdev
*
subdev
=
(
void
*
)
object
;
return
nvkm_subdev_init_old
(
subdev
);
}
int
nvkm_subdev_fini_old
(
struct
nvkm_subdev
*
subdev
,
bool
suspend
)
{
struct
nvkm_device
*
device
=
subdev
->
device
;
if
(
subdev
->
unit
)
{
nvkm_mask
(
device
,
0x000200
,
subdev
->
unit
,
0x00000000
);
nvkm_mask
(
device
,
0x000200
,
subdev
->
unit
,
subdev
->
unit
);
}
return
_nvkm_object_fini
(
&
subdev
->
object
,
suspend
);
}
int
_nvkm_subdev_fini
(
struct
nvkm_object
*
object
,
bool
suspend
)
{
struct
nvkm_subdev
*
subdev
=
(
void
*
)
object
;
return
nvkm_subdev_fini_old
(
subdev
,
suspend
);
}
void
nvkm_subdev_destroy
(
struct
nvkm_subdev
*
subdev
)
{
nvkm_object_destroy
(
&
subdev
->
object
);
}
void
_nvkm_subdev_dtor
(
struct
nvkm_object
*
object
)
{
nvkm_subdev_destroy
(
nv_subdev
(
object
));
}
int
nvkm_subdev_create_
(
struct
nvkm_object
*
parent
,
struct
nvkm_object
*
engine
,
struct
nvkm_oclass
*
oclass
,
u32
pclass
,
const
char
*
subname
,
const
char
*
sysname
,
int
size
,
void
**
pobject
)
{
const
int
subidx
=
oclass
->
handle
&
0xff
;
const
char
*
name
=
nvkm_subdev_name
[
subidx
];
struct
nvkm_subdev
*
subdev
;
int
ret
;
ret
=
nvkm_object_create_
(
parent
,
engine
,
oclass
,
pclass
|
NV_SUBDEV_CLASS
,
size
,
pobject
);
subdev
=
*
pobject
;
if
(
ret
)
return
ret
;
__mutex_init
(
&
subdev
->
mutex
,
name
,
&
nvkm_subdev_lock_class
[
subidx
]);
subdev
->
index
=
subidx
;
if
(
parent
)
{
struct
nvkm_device
*
device
=
nv_device
(
parent
);
subdev
->
debug
=
nvkm_dbgopt
(
device
->
dbgopt
,
name
);
subdev
->
device
=
device
;
}
else
{
subdev
->
device
=
nv_device
(
subdev
);
}
return
0
;
}
drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c
View file @
68f3f702
...
...
@@ -30,7 +30,7 @@ static void
gf100_ce_init
(
struct
nvkm_falcon
*
ce
)
{
struct
nvkm_device
*
device
=
ce
->
engine
.
subdev
.
device
;
const
int
index
=
ce
->
engine
.
subdev
.
index
-
NV
DEV
_ENGINE_CE0
;
const
int
index
=
ce
->
engine
.
subdev
.
index
-
NV
KM
_ENGINE_CE0
;
nvkm_wr32
(
device
,
ce
->
addr
+
0x084
,
index
);
}
...
...
@@ -68,11 +68,11 @@ int
gf100_ce_new
(
struct
nvkm_device
*
device
,
int
index
,
struct
nvkm_engine
**
pengine
)
{
if
(
index
==
NV
DEV
_ENGINE_CE0
)
{
if
(
index
==
NV
KM
_ENGINE_CE0
)
{
return
nvkm_falcon_new_
(
&
gf100_ce0
,
device
,
index
,
true
,
0x104000
,
pengine
);
}
else
if
(
index
==
NV
DEV
_ENGINE_CE1
)
{
if
(
index
==
NV
KM
_ENGINE_CE1
)
{
return
nvkm_falcon_new_
(
&
gf100_ce1
,
device
,
index
,
true
,
0x105000
,
pengine
);
}
...
...
drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c
View file @
68f3f702
...
...
@@ -28,7 +28,7 @@
void
gk104_ce_intr
(
struct
nvkm_engine
*
ce
)
{
const
u32
base
=
(
ce
->
subdev
.
index
-
NV
DEV
_ENGINE_CE0
)
*
0x1000
;
const
u32
base
=
(
ce
->
subdev
.
index
-
NV
KM
_ENGINE_CE0
)
*
0x1000
;
struct
nvkm_subdev
*
subdev
=
&
ce
->
subdev
;
struct
nvkm_device
*
device
=
subdev
->
device
;
u32
stat
=
nvkm_rd32
(
device
,
0x104908
+
base
);
...
...
@@ -51,15 +51,15 @@ int
gk104_ce_new
(
struct
nvkm_device
*
device
,
int
index
,
struct
nvkm_engine
**
pengine
)
{
if
(
index
==
NV
DEV
_ENGINE_CE0
)
{
if
(
index
==
NV
KM
_ENGINE_CE0
)
{
return
nvkm_engine_new_
(
&
gk104_ce
,
device
,
index
,
0x00000040
,
true
,
pengine
);
}
else
if
(
index
==
NV
DEV
_ENGINE_CE1
)
{
if
(
index
==
NV
KM
_ENGINE_CE1
)
{
return
nvkm_engine_new_
(
&
gk104_ce
,
device
,
index
,
0x00000080
,
true
,
pengine
);
}
else
if
(
index
==
NV
DEV
_ENGINE_CE2
)
{
if
(
index
==
NV
KM
_ENGINE_CE2
)
{
return
nvkm_engine_new_
(
&
gk104_ce
,
device
,
index
,
0x00200000
,
true
,
pengine
);
}
...
...
drivers/gpu/drm/nouveau/nvkm/engine/ce/gm204.c
View file @
68f3f702
...
...
@@ -38,15 +38,15 @@ int
gm204_ce_new
(
struct
nvkm_device
*
device
,
int
index
,
struct
nvkm_engine
**
pengine
)
{
if
(
index
==
NV
DEV
_ENGINE_CE0
)
{
if
(
index
==
NV
KM
_ENGINE_CE0
)
{
return
nvkm_engine_new_
(
&
gm204_ce
,
device
,
index
,
0x00000040
,
true
,
pengine
);
}
else
if
(
index
==
NV
DEV
_ENGINE_CE1
)
{
if
(
index
==
NV
KM
_ENGINE_CE1
)
{
return
nvkm_engine_new_
(
&
gm204_ce
,
device
,
index
,
0x00000080
,
true
,
pengine
);
}
else
if
(
index
==
NV
DEV
_ENGINE_CE2
)
{
if
(
index
==
NV
KM
_ENGINE_CE2
)
{
return
nvkm_engine_new_
(
&
gm204_ce
,
device
,
index
,
0x00200000
,
true
,
pengine
);
}
...
...
drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c
View file @
68f3f702
...
...
@@ -44,7 +44,7 @@ gt215_ce_intr(struct nvkm_falcon *ce, struct nvkm_fifo_chan *chan)
{
struct
nvkm_subdev
*
subdev
=
&
ce
->
engine
.
subdev
;
struct
nvkm_device
*
device
=
subdev
->
device
;
const
u32
base
=
(
subdev
->
index
-
NV
DEV
_ENGINE_CE0
)
*
0x1000
;
const
u32
base
=
(
subdev
->
index
-
NV
KM
_ENGINE_CE0
)
*
0x1000
;
u32
ssta
=
nvkm_rd32
(
device
,
0x104040
+
base
)
&
0x0000ffff
;
u32
addr
=
nvkm_rd32
(
device
,
0x104040
+
base
)
>>
16
;
u32
mthd
=
(
addr
&
0x07ff
)
<<
2
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c
View file @
68f3f702
...
...
@@ -38,7 +38,7 @@ g84_cipher_oclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
align
,
false
,
parent
,
pgpuobj
);
if
(
ret
==
0
)
{
nvkm_kmap
(
*
pgpuobj
);
nvkm_wo32
(
*
pgpuobj
,
0x00
,
object
->
oclass
_name
);
nvkm_wo32
(
*
pgpuobj
,
0x00
,
object
->
oclass
);
nvkm_wo32
(
*
pgpuobj
,
0x04
,
0x00000000
);
nvkm_wo32
(
*
pgpuobj
,
0x08
,
0x00000000
);
nvkm_wo32
(
*
pgpuobj
,
0x0c
,
0x00000000
);
...
...
drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild
View file @
68f3f702
...
...
@@ -4,13 +4,3 @@ nvkm-y += nvkm/engine/device/ctrl.o
nvkm-y += nvkm/engine/device/pci.o
nvkm-y += nvkm/engine/device/tegra.o
nvkm-y += nvkm/engine/device/user.o
nvkm-y += nvkm/engine/device/nv04.o
nvkm-y += nvkm/engine/device/nv10.o
nvkm-y += nvkm/engine/device/nv20.o
nvkm-y += nvkm/engine/device/nv30.o
nvkm-y += nvkm/engine/device/nv40.o
nvkm-y += nvkm/engine/device/nv50.o
nvkm-y += nvkm/engine/device/gf100.o
nvkm-y += nvkm/engine/device/gk104.o
nvkm-y += nvkm/engine/device/gm100.o
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View file @
68f3f702
...
...
@@ -1975,36 +1975,6 @@ nv12b_chipset = {
.
sw
=
gf100_sw_new
,
};
#include <core/client.h>
struct
nvkm_device
*
nv_device
(
void
*
obj
)
{
struct
nvkm_object
*
device
=
nv_object
(
obj
);
if
(
device
->
engine
==
NULL
)
{
while
(
device
&&
device
->
parent
)
{
if
(
!
nv_iclass
(
device
,
NV_SUBDEV_CLASS
)
&&
device
->
parent
==
&
nvkm_client
(
device
)
->
object
)
{
struct
{
struct
nvkm_object
base
;
struct
nvkm_device
*
device
;
}
*
udevice
=
(
void
*
)
device
;
return
udevice
->
device
;
}
device
=
device
->
parent
;
}
}
else
{
device
=
&
nv_object
(
obj
)
->
engine
->
subdev
.
object
;
if
(
device
&&
device
->
parent
)
device
=
device
->
parent
;
}
#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
BUG_ON
(
!
device
);
#endif
return
(
void
*
)
device
;
}
static
int
nvkm_device_event_ctor
(
struct
nvkm_object
*
object
,
void
*
data
,
u32
size
,
struct
nvkm_notify
*
notify
)
...
...
@@ -2032,7 +2002,7 @@ nvkm_device_subdev(struct nvkm_device *device, int index)
return
NULL
;
switch
(
index
)
{
#define _(n,p,m) case NV
DEV
_SUBDEV_##n: if (p) return (m); break
#define _(n,p,m) case NV
KM
_SUBDEV_##n: if (p) return (m); break
_
(
BAR
,
device
->
bar
,
&
device
->
bar
->
subdev
);
_
(
VBIOS
,
device
->
bios
,
&
device
->
bios
->
subdev
);
_
(
BUS
,
device
->
bus
,
&
device
->
bus
->
subdev
);
...
...
@@ -2069,7 +2039,7 @@ nvkm_device_engine(struct nvkm_device *device, int index)
return
NULL
;
switch
(
index
)
{
#define _(n,p,m) case NV
DEV
_ENGINE_##n: if (p) return (m); break
#define _(n,p,m) case NV
KM
_ENGINE_##n: if (p) return (m); break
_
(
BSP
,
device
->
bsp
,
device
->
bsp
);
_
(
CE0
,
device
->
ce
[
0
]
,
device
->
ce
[
0
]);
_
(
CE1
,
device
->
ce
[
1
]
,
device
->
ce
[
1
]);
...
...
@@ -2112,7 +2082,7 @@ nvkm_device_fini(struct nvkm_device *device, bool suspend)
nvkm_acpi_fini
(
device
);
for
(
i
=
NV
DEV
_SUBDEV_NR
-
1
;
i
>=
0
;
i
--
)
{
for
(
i
=
NV
KM
_SUBDEV_NR
-
1
;
i
>=
0
;
i
--
)
{
if
((
subdev
=
nvkm_device_subdev
(
device
,
i
)))
{
ret
=
nvkm_subdev_fini
(
subdev
,
suspend
);
if
(
ret
&&
suspend
)
...
...
@@ -2135,7 +2105,7 @@ nvkm_device_fini(struct nvkm_device *device, bool suspend)
if
(
rret
)
nvkm_fatal
(
subdev
,
"failed restart, %d
\n
"
,
ret
);
}
}
while
(
++
i
<
NV
DEV
_SUBDEV_NR
);
}
while
(
++
i
<
NV
KM
_SUBDEV_NR
);
nvdev_trace
(
device
,
"%s failed with %d
\n
"
,
action
,
ret
);
return
ret
;
...
...
@@ -2157,7 +2127,7 @@ nvkm_device_preinit(struct nvkm_device *device)
goto
fail
;
}
for
(
i
=
0
;
i
<
NV
DEV
_SUBDEV_NR
;
i
++
)
{
for
(
i
=
0
;
i
<
NV
KM
_SUBDEV_NR
;
i
++
)
{
if
((
subdev
=
nvkm_device_subdev
(
device
,
i
)))
{
ret
=
nvkm_subdev_preinit
(
subdev
);
if
(
ret
)
...
...
@@ -2182,7 +2152,7 @@ int
nvkm_device_init
(
struct
nvkm_device
*
device
)
{
struct
nvkm_subdev
*
subdev
;
int
ret
,
i
=
0
,
c
;
int
ret
,
i
;
s64
time
;
ret
=
nvkm_device_preinit
(
device
);
...
...
@@ -2194,82 +2164,13 @@ nvkm_device_init(struct nvkm_device *device)
nvdev_trace
(
device
,
"init running...
\n
"
);
time
=
ktime_to_us
(
ktime_get
());
for
(
i
=
0
,
c
=
0
;
i
<
NVDEV_SUBDEV_NR
;
i
++
)
{
#define _(s,m) case s: if (device->oclass[s] && !device->m) { \
ret = nvkm_object_old(nv_object(device), NULL, \
device->oclass[s], NULL, (s), \
(struct nvkm_object **)&device->m); \
if (ret == -ENODEV) { \
device->oclass[s] = NULL; \
continue; \
} \
if (ret) \
goto fail; \
} break
switch
(
i
)
{
_
(
NVDEV_SUBDEV_BAR
,
bar
);
_
(
NVDEV_SUBDEV_VBIOS
,
bios
);
_
(
NVDEV_SUBDEV_BUS
,
bus
);
_
(
NVDEV_SUBDEV_CLK
,
clk
);
_
(
NVDEV_SUBDEV_DEVINIT
,
devinit
);
_
(
NVDEV_SUBDEV_FB
,
fb
);
_
(
NVDEV_SUBDEV_FUSE
,
fuse
);
_
(
NVDEV_SUBDEV_GPIO
,
gpio
);
_
(
NVDEV_SUBDEV_I2C
,
i2c
);
_
(
NVDEV_SUBDEV_IBUS
,
ibus
);
_
(
NVDEV_SUBDEV_INSTMEM
,
imem
);
_
(
NVDEV_SUBDEV_LTC
,
ltc
);
_
(
NVDEV_SUBDEV_MC
,
mc
);
_
(
NVDEV_SUBDEV_MMU
,
mmu
);
_
(
NVDEV_SUBDEV_MXM
,
mxm
);
_
(
NVDEV_SUBDEV_PMU
,
pmu
);
_
(
NVDEV_SUBDEV_THERM
,
therm
);
_
(
NVDEV_SUBDEV_TIMER
,
timer
);
_
(
NVDEV_SUBDEV_VOLT
,
volt
);
_
(
NVDEV_ENGINE_BSP
,
bsp
);
_
(
NVDEV_ENGINE_CE0
,
ce
[
0
]);
_
(
NVDEV_ENGINE_CE1
,
ce
[
1
]);
_
(
NVDEV_ENGINE_CE2
,
ce
[
2
]);
_
(
NVDEV_ENGINE_CIPHER
,
cipher
);
_
(
NVDEV_ENGINE_DISP
,
disp
);
_
(
NVDEV_ENGINE_DMAOBJ
,
dma
);
_
(
NVDEV_ENGINE_FIFO
,
fifo
);
_
(
NVDEV_ENGINE_GR
,
gr
);
_
(
NVDEV_ENGINE_IFB
,
ifb
);
_
(
NVDEV_ENGINE_ME
,
me
);
_
(
NVDEV_ENGINE_MPEG
,
mpeg
);
_
(
NVDEV_ENGINE_MSENC
,
msenc
);
_
(
NVDEV_ENGINE_MSPDEC
,
mspdec
);
_
(
NVDEV_ENGINE_MSPPP
,
msppp
);
_
(
NVDEV_ENGINE_MSVLD
,
msvld
);
_
(
NVDEV_ENGINE_PM
,
pm
);
_
(
NVDEV_ENGINE_SEC
,
sec
);
_
(
NVDEV_ENGINE_SW
,
sw
);
_
(
NVDEV_ENGINE_VIC
,
vic
);
_
(
NVDEV_ENGINE_VP
,
vp
);
default:
WARN_ON
(
1
);
continue
;
}
#undef _
/* note: can't init *any* subdevs until devinit has been run
* due to not knowing exactly what the vbios init tables will
* mess with. devinit also can't be run until all of its
* dependencies have been created.
*
* this code delays init of any subdev until all of devinit's
* dependencies have been created, and then initialises each
* subdev in turn as they're created.
*/
while
(
i
>=
NVDEV_SUBDEV_DEVINIT_LAST
&&
c
<=
i
)
{
if
((
subdev
=
nvkm_device_subdev
(
device
,
c
++
)))
{
for
(
i
=
0
;
i
<
NVKM_SUBDEV_NR
;
i
++
)
{
if
((
subdev
=
nvkm_device_subdev
(
device
,
i
)))
{
ret
=
nvkm_subdev_init
(
subdev
);
if
(
ret
)
goto
fail
;
}
}
}
nvkm_acpi_init
(
device
);
...
...
@@ -2336,7 +2237,7 @@ nvkm_device_del(struct nvkm_device **pdevice)
if
(
device
)
{
mutex_lock
(
&
nv_devices_mutex
);
device
->
disable_mask
=
0
;
for
(
i
=
NV
DEV
_SUBDEV_NR
-
1
;
i
>=
0
;
i
--
)
{
for
(
i
=
NV
KM
_SUBDEV_NR
-
1
;
i
>=
0
;
i
--
)
{
struct
nvkm_subdev
*
subdev
=
nvkm_device_subdev
(
device
,
i
);
nvkm_subdev_del
(
&
subdev
);
...
...
@@ -2357,10 +2258,6 @@ nvkm_device_del(struct nvkm_device **pdevice)
}
}
static
const
struct
nvkm_engine_func
nvkm_device_func
=
{
};
int
nvkm_device_ctor
(
const
struct
nvkm_device_func
*
func
,
const
struct
nvkm_device_quirk
*
quirk
,
...
...
@@ -2397,12 +2294,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
device
->
dbgopt
=
dbg
;
device
->
name
=
name
;
list_add_tail
(
&
device
->
head
,
&
nv_devices
);
ret
=
nvkm_engine_ctor
(
&
nvkm_device_func
,
device
,
0
,
0
,
true
,
&
device
->
engine
);
device
->
engine
.
subdev
.
object
.
parent
=
NULL
;
if
(
ret
)
goto
done
;
device
->
debug
=
nvkm_dbgopt
(
device
->
dbgopt
,
"device"
);
ret
=
nvkm_event_init
(
&
nvkm_device_event_func
,
1
,
1
,
&
device
->
event
);
if
(
ret
)
...
...
@@ -2472,23 +2364,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
device
->
card_type
=
NV_04
;
}
switch
(
device
->
card_type
)
{
case
NV_04
:
ret
=
nv04_identify
(
device
);
break
;
case
NV_10
:
case
NV_11
:
ret
=
nv10_identify
(
device
);
break
;
case
NV_20
:
ret
=
nv20_identify
(
device
);
break
;
case
NV_30
:
ret
=
nv30_identify
(
device
);
break
;
case
NV_40
:
ret
=
nv40_identify
(
device
);
break
;
case
NV_50
:
ret
=
nv50_identify
(
device
);
break
;
case
NV_C0
:
ret
=
gf100_identify
(
device
);
break
;
case
NV_E0
:
ret
=
gk104_identify
(
device
);
break
;
case
GM100
:
ret
=
gm100_identify
(
device
);
break
;
default:
ret
=
-
EINVAL
;
break
;
}
switch
(
!
ret
*
device
->
chipset
)
{
switch
(
device
->
chipset
)
{
case
0x004
:
device
->
chip
=
&
nv4_chipset
;
break
;
case
0x005
:
device
->
chip
=
&
nv5_chipset
;
break
;
case
0x010
:
device
->
chip
=
&
nv10_chipset
;
break
;
...
...
@@ -2594,16 +2470,9 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
}
}
/* disable subdevs that aren't required (used by tools) */
for
(
i
=
0
;
i
<
NVDEV_SUBDEV_NR
;
i
++
)
{
if
(
!
(
subdev_mask
&
(
1ULL
<<
i
)))
device
->
oclass
[
i
]
=
NULL
;
}
atomic_set
(
&
device
->
engine
.
subdev
.
object
.
usecount
,
2
);
mutex_init
(
&
device
->
mutex
);
for
(
i
=
0
;
i
<
NV
DEV
_SUBDEV_NR
;
i
++
)
{
for
(
i
=
0
;
i
<
NV
KM
_SUBDEV_NR
;
i
++
)
{
#define _(s,m) case s: \
if (device->chip->m && (subdev_mask & (1ULL << (s)))) { \
ret = device->chip->m(device, (s), &device->m); \
...
...
@@ -2620,46 +2489,46 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
} \
break
switch
(
i
)
{
_
(
NV
DEV
_SUBDEV_BAR
,
bar
);
_
(
NV
DEV
_SUBDEV_VBIOS
,
bios
);
_
(
NV
DEV
_SUBDEV_BUS
,
bus
);
_
(
NV
DEV
_SUBDEV_CLK
,
clk
);
_
(
NV
DEV
_SUBDEV_DEVINIT
,
devinit
);
_
(
NV
DEV
_SUBDEV_FB
,
fb
);
_
(
NV
DEV
_SUBDEV_FUSE
,
fuse
);
_
(
NV
DEV
_SUBDEV_GPIO
,
gpio
);
_
(
NV
DEV
_SUBDEV_I2C
,
i2c
);
_
(
NV
DEV
_SUBDEV_IBUS
,
ibus
);
_
(
NV
DEV
_SUBDEV_INSTMEM
,
imem
);
_
(
NV
DEV
_SUBDEV_LTC
,
ltc
);
_
(
NV
DEV
_SUBDEV_MC
,
mc
);
_
(
NV
DEV
_SUBDEV_MMU
,
mmu
);
_
(
NV
DEV
_SUBDEV_MXM
,
mxm
);
_
(
NV
DEV
_SUBDEV_PMU
,
pmu
);
_
(
NV
DEV
_SUBDEV_THERM
,
therm
);
_
(
NV
DEV
_SUBDEV_TIMER
,
timer
);
_
(
NV
DEV
_SUBDEV_VOLT
,
volt
);
_
(
NV
DEV
_ENGINE_BSP
,
bsp
);
_
(
NV
DEV
_ENGINE_CE0
,
ce
[
0
]);
_
(
NV
DEV
_ENGINE_CE1
,
ce
[
1
]);
_
(
NV
DEV
_ENGINE_CE2
,
ce
[
2
]);
_
(
NV
DEV
_ENGINE_CIPHER
,
cipher
);
_
(
NV
DEV
_ENGINE_DISP
,
disp
);
_
(
NV
DEV
_ENGINE_DMAOBJ
,
dma
);
_
(
NV
DEV
_ENGINE_FIFO
,
fifo
);
_
(
NV
DEV
_ENGINE_GR
,
gr
);
_
(
NV
DEV
_ENGINE_IFB
,
ifb
);
_
(
NV
DEV
_ENGINE_ME
,
me
);
_
(
NV
DEV
_ENGINE_MPEG
,
mpeg
);
_
(
NV
DEV
_ENGINE_MSENC
,
msenc
);
_
(
NV
DEV
_ENGINE_MSPDEC
,
mspdec
);
_
(
NV
DEV
_ENGINE_MSPPP
,
msppp
);
_
(
NV
DEV
_ENGINE_MSVLD
,
msvld
);
_
(
NV
DEV
_ENGINE_PM
,
pm
);
_
(
NV
DEV
_ENGINE_SEC
,
sec
);
_
(
NV
DEV
_ENGINE_SW
,
sw
);
_
(
NV
DEV
_ENGINE_VIC
,
vic
);
_
(
NV
DEV
_ENGINE_VP
,
vp
);
_
(
NV
KM
_SUBDEV_BAR
,
bar
);
_
(
NV
KM
_SUBDEV_VBIOS
,
bios
);
_
(
NV
KM
_SUBDEV_BUS
,
bus
);
_
(
NV
KM
_SUBDEV_CLK
,
clk
);
_
(
NV
KM
_SUBDEV_DEVINIT
,
devinit
);
_
(
NV
KM
_SUBDEV_FB
,
fb
);
_
(
NV
KM
_SUBDEV_FUSE
,
fuse
);
_
(
NV
KM
_SUBDEV_GPIO
,
gpio
);
_
(
NV
KM
_SUBDEV_I2C
,
i2c
);
_
(
NV
KM
_SUBDEV_IBUS
,
ibus
);
_
(
NV
KM
_SUBDEV_INSTMEM
,
imem
);
_
(
NV
KM
_SUBDEV_LTC
,
ltc
);
_
(
NV
KM
_SUBDEV_MC
,
mc
);
_
(
NV
KM
_SUBDEV_MMU
,
mmu
);
_
(
NV
KM
_SUBDEV_MXM
,
mxm
);
_
(
NV
KM
_SUBDEV_PMU
,
pmu
);
_
(
NV
KM
_SUBDEV_THERM
,
therm
);
_
(
NV
KM
_SUBDEV_TIMER
,
timer
);
_
(
NV
KM
_SUBDEV_VOLT
,
volt
);
_
(
NV
KM
_ENGINE_BSP
,
bsp
);
_
(
NV
KM
_ENGINE_CE0
,
ce
[
0
]);
_
(
NV
KM
_ENGINE_CE1
,
ce
[
1
]);
_
(
NV
KM
_ENGINE_CE2
,
ce
[
2
]);
_
(
NV
KM
_ENGINE_CIPHER
,
cipher
);
_
(
NV
KM
_ENGINE_DISP
,
disp
);
_
(
NV
KM
_ENGINE_DMAOBJ
,
dma
);
_
(
NV
KM
_ENGINE_FIFO
,
fifo
);
_
(
NV
KM
_ENGINE_GR
,
gr
);
_
(
NV
KM
_ENGINE_IFB
,
ifb
);
_
(
NV
KM
_ENGINE_ME
,
me
);
_
(
NV
KM
_ENGINE_MPEG
,
mpeg
);
_
(
NV
KM
_ENGINE_MSENC
,
msenc
);
_
(
NV
KM
_ENGINE_MSPDEC
,
mspdec
);
_
(
NV
KM
_ENGINE_MSPPP
,
msppp
);
_
(
NV
KM
_ENGINE_MSVLD
,
msvld
);
_
(
NV
KM
_ENGINE_PM
,
pm
);
_
(
NV
KM
_ENGINE_SEC
,
sec
);
_
(
NV
KM
_ENGINE_SW
,
sw
);
_
(
NV
KM
_ENGINE_VIC
,
vic
);
_
(
NV
KM
_ENGINE_VP
,
vp
);
default:
WARN_ON
(
1
);
continue
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
deleted
100644 → 0
View file @
7624fc01
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
int
gf100_identify
(
struct
nvkm_device
*
device
)
{
switch
(
device
->
chipset
)
{
case
0xc0
:
break
;
case
0xc4
:
break
;
case
0xc3
:
break
;
case
0xce
:
break
;
case
0xcf
:
break
;
case
0xc1
:
break
;
case
0xc8
:
break
;
case
0xd9
:
break
;
case
0xd7
:
break
;
default:
return
-
EINVAL
;
}
return
0
;
}
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
deleted
100644 → 0
View file @
7624fc01
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
int
gk104_identify
(
struct
nvkm_device
*
device
)
{
switch
(
device
->
chipset
)
{
case
0xe4
:
break
;
case
0xe7
:
break
;
case
0xe6
:
break
;
case
0xea
:
break
;
case
0xf0
:
break
;
case
0xf1
:
break
;
case
0x106
:
break
;
case
0x108
:
break
;
default:
return
-
EINVAL
;
}
return
0
;
}
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
deleted
100644 → 0
View file @
7624fc01
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
int
gm100_identify
(
struct
nvkm_device
*
device
)
{
switch
(
device
->
chipset
)
{
case
0x117
:
#if 0
#endif
#if 0
#endif
#if 0
#endif
break
;
case
0x124
:
#if 0
/* looks to be some non-trivial changes */
/* priv ring says no to 0x10eb14 writes */
#endif
#if 0
#endif
#if 0
#endif
break
;
case
0x126
:
#if 0
/* looks to be some non-trivial changes */
/* priv ring says no to 0x10eb14 writes */
#endif
#if 0
#endif
#if 0
#endif
break
;
case
0x12b
:
break
;
default:
return
-
EINVAL
;
}
return
0
;
}
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
deleted
100644 → 0
View file @
7624fc01
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
int
nv04_identify
(
struct
nvkm_device
*
device
)
{
switch
(
device
->
chipset
)
{
case
0x04
:
break
;
case
0x05
:
break
;
default:
return
-
EINVAL
;
}
return
0
;
}
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
deleted
100644 → 0
View file @
7624fc01
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
int
nv10_identify
(
struct
nvkm_device
*
device
)
{
switch
(
device
->
chipset
)
{
case
0x10
:
break
;
case
0x15
:
break
;
case
0x16
:
break
;
case
0x1a
:
break
;
case
0x11
:
break
;
case
0x17
:
break
;
case
0x1f
:
break
;
case
0x18
:
break
;
default:
return
-
EINVAL
;
}
return
0
;
}
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
deleted
100644 → 0
View file @
7624fc01
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
int
nv20_identify
(
struct
nvkm_device
*
device
)
{
switch
(
device
->
chipset
)
{
case
0x20
:
break
;
case
0x25
:
break
;
case
0x28
:
break
;
case
0x2a
:
break
;
default:
return
-
EINVAL
;
}
return
0
;
}
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
deleted
100644 → 0
View file @
7624fc01
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
int
nv30_identify
(
struct
nvkm_device
*
device
)
{
switch
(
device
->
chipset
)
{
case
0x30
:
break
;
case
0x35
:
break
;
case
0x31
:
break
;
case
0x36
:
break
;
case
0x34
:
break
;
default:
return
-
EINVAL
;
}
return
0
;
}
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
deleted
100644 → 0
View file @
7624fc01
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
int
nv40_identify
(
struct
nvkm_device
*
device
)
{
switch
(
device
->
chipset
)
{
case
0x40
:
break
;
case
0x41
:
break
;
case
0x42
:
break
;
case
0x43
:
break
;
case
0x45
:
break
;
case
0x47
:
break
;
case
0x49
:
break
;
case
0x4b
:
break
;
case
0x44
:
break
;
case
0x46
:
break
;
case
0x4a
:
break
;
case
0x4c
:
break
;
case
0x4e
:
break
;
case
0x63
:
break
;
case
0x67
:
break
;
case
0x68
:
break
;
default:
return
-
EINVAL
;
}
return
0
;
}
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
deleted
100644 → 0
View file @
7624fc01
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
int
nv50_identify
(
struct
nvkm_device
*
device
)
{
switch
(
device
->
chipset
)
{
case
0x50
:
break
;
case
0x84
:
break
;
case
0x86
:
break
;
case
0x92
:
break
;
case
0x94
:
break
;
case
0x96
:
break
;
case
0x98
:
break
;
case
0xa0
:
break
;
case
0xaa
:
break
;
case
0xac
:
break
;
case
0xa3
:
break
;
case
0xa5
:
break
;
case
0xa8
:
break
;
case
0xaf
:
break
;
default:
return
-
EINVAL
;
}
return
0
;
}
drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h
View file @
68f3f702
...
...
@@ -46,14 +46,4 @@ int nvkm_device_ctor(const struct nvkm_device_func *,
struct
nvkm_device
*
);
int
nvkm_device_init
(
struct
nvkm_device
*
);
int
nvkm_device_fini
(
struct
nvkm_device
*
,
bool
suspend
);
int
nv04_identify
(
struct
nvkm_device
*
);
int
nv10_identify
(
struct
nvkm_device
*
);
int
nv20_identify
(
struct
nvkm_device
*
);
int
nv30_identify
(
struct
nvkm_device
*
);
int
nv40_identify
(
struct
nvkm_device
*
);
int
nv50_identify
(
struct
nvkm_device
*
);
int
gf100_identify
(
struct
nvkm_device
*
);
int
gk104_identify
(
struct
nvkm_device
*
);
int
gm100_identify
(
struct
nvkm_device
*
);
#endif
drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
View file @
68f3f702
...
...
@@ -261,10 +261,10 @@ nvkm_udevice_child_get(struct nvkm_object *object, int index,
struct
nvkm_udevice
*
udev
=
nvkm_udevice
(
object
);
struct
nvkm_device
*
device
=
udev
->
device
;
struct
nvkm_engine
*
engine
;
u64
mask
=
(
1ULL
<<
NV
DEV
_ENGINE_DMAOBJ
)
|
(
1ULL
<<
NV
DEV
_ENGINE_FIFO
)
|
(
1ULL
<<
NV
DEV
_ENGINE_DISP
)
|
(
1ULL
<<
NV
DEV
_ENGINE_PM
);
u64
mask
=
(
1ULL
<<
NV
KM
_ENGINE_DMAOBJ
)
|
(
1ULL
<<
NV
KM
_ENGINE_FIFO
)
|
(
1ULL
<<
NV
KM
_ENGINE_DISP
)
|
(
1ULL
<<
NV
KM
_ENGINE_PM
);
const
struct
nvkm_device_oclass
*
sclass
=
NULL
;
int
i
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c
View file @
68f3f702
...
...
@@ -90,7 +90,7 @@ nv50_disp_dmac_child_get_(struct nv50_disp_chan *base, int index,
struct
nvkm_device
*
device
=
disp
->
base
.
engine
.
subdev
.
device
;
const
struct
nvkm_device_oclass
*
oclass
=
NULL
;
sclass
->
engine
=
nvkm_device_engine
(
device
,
NV
DEV
_ENGINE_DMAOBJ
);
sclass
->
engine
=
nvkm_device_engine
(
device
,
NV
KM
_ENGINE_DMAOBJ
);
if
(
sclass
->
engine
&&
sclass
->
engine
->
func
->
base
.
sclass
)
{
sclass
->
engine
->
func
->
base
.
sclass
(
sclass
,
index
,
&
oclass
);
if
(
oclass
)
{
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
View file @
68f3f702
...
...
@@ -332,7 +332,7 @@ nvkm_fifo_chan_dtor(struct nvkm_object *object)
return
data
;
}
const
struct
nvkm_object_func
static
const
struct
nvkm_object_func
nvkm_fifo_chan_func
=
{
.
dtor
=
nvkm_fifo_chan_dtor
,
.
init
=
nvkm_fifo_chan_init
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c
View file @
68f3f702
...
...
@@ -48,16 +48,16 @@ static int
g84_fifo_chan_engine
(
struct
nvkm_engine
*
engine
)
{
switch
(
engine
->
subdev
.
index
)
{
case
NV
DEV
_ENGINE_GR
:
return
0
;
case
NV
DEV
_ENGINE_MPEG
:
case
NV
DEV
_ENGINE_MSPPP
:
return
1
;
case
NV
DEV
_ENGINE_CE0
:
return
2
;
case
NV
DEV
_ENGINE_VP
:
case
NV
DEV
_ENGINE_MSPDEC
:
return
3
;
case
NV
DEV
_ENGINE_CIPHER
:
case
NV
DEV
_ENGINE_SEC
:
return
4
;
case
NV
DEV
_ENGINE_BSP
:
case
NV
DEV
_ENGINE_MSVLD
:
return
5
;
case
NV
KM
_ENGINE_GR
:
return
0
;
case
NV
KM
_ENGINE_MPEG
:
case
NV
KM
_ENGINE_MSPPP
:
return
1
;
case
NV
KM
_ENGINE_CE0
:
return
2
;
case
NV
KM
_ENGINE_VP
:
case
NV
KM
_ENGINE_MSPDEC
:
return
3
;
case
NV
KM
_ENGINE_CIPHER
:
case
NV
KM
_ENGINE_SEC
:
return
4
;
case
NV
KM
_ENGINE_BSP
:
case
NV
KM
_ENGINE_MSVLD
:
return
5
;
default:
WARN_ON
(
1
);
return
0
;
...
...
@@ -68,18 +68,18 @@ static int
g84_fifo_chan_engine_addr
(
struct
nvkm_engine
*
engine
)
{
switch
(
engine
->
subdev
.
index
)
{
case
NV
DEV
_ENGINE_DMAOBJ
:
case
NV
DEV
_ENGINE_SW
:
return
-
1
;
case
NV
DEV
_ENGINE_GR
:
return
0x0020
;
case
NV
DEV
_ENGINE_VP
:
case
NV
DEV
_ENGINE_MSPDEC
:
return
0x0040
;
case
NV
DEV
_ENGINE_MPEG
:
case
NV
DEV
_ENGINE_MSPPP
:
return
0x0060
;
case
NV
DEV
_ENGINE_BSP
:
case
NV
DEV
_ENGINE_MSVLD
:
return
0x0080
;
case
NV
DEV
_ENGINE_CIPHER
:
case
NV
DEV
_ENGINE_SEC
:
return
0x00a0
;
case
NV
DEV
_ENGINE_CE0
:
return
0x00c0
;
case
NV
KM
_ENGINE_DMAOBJ
:
case
NV
KM
_ENGINE_SW
:
return
-
1
;
case
NV
KM
_ENGINE_GR
:
return
0x0020
;
case
NV
KM
_ENGINE_VP
:
case
NV
KM
_ENGINE_MSPDEC
:
return
0x0040
;
case
NV
KM
_ENGINE_MPEG
:
case
NV
KM
_ENGINE_MSPPP
:
return
0x0060
;
case
NV
KM
_ENGINE_BSP
:
case
NV
KM
_ENGINE_MSVLD
:
return
0x0080
;
case
NV
KM
_ENGINE_CIPHER
:
case
NV
KM
_ENGINE_SEC
:
return
0x00a0
;
case
NV
KM
_ENGINE_CE0
:
return
0x00c0
;
default:
WARN_ON
(
1
);
return
-
1
;
...
...
@@ -167,11 +167,6 @@ g84_fifo_chan_engine_ctor(struct nvkm_fifo_chan *base,
if
(
g84_fifo_chan_engine_addr
(
engine
)
<
0
)
return
0
;
if
(
nv_iclass
(
object
,
NV_GPUOBJ_CLASS
))
{
chan
->
engn
[
engn
]
=
nv_gpuobj
(
object
);
return
0
;
}
return
nvkm_object_bind
(
object
,
NULL
,
0
,
&
chan
->
engn
[
engn
]);
}
...
...
@@ -184,20 +179,20 @@ g84_fifo_chan_object_ctor(struct nvkm_fifo_chan *base,
u32
context
;
switch
(
object
->
engine
->
subdev
.
index
)
{
case
NV
DEV
_ENGINE_DMAOBJ
:
case
NV
DEV
_ENGINE_SW
:
context
=
0x00000000
;
break
;
case
NV
DEV
_ENGINE_GR
:
context
=
0x00100000
;
break
;
case
NV
DEV
_ENGINE_MPEG
:
case
NV
DEV
_ENGINE_MSPPP
:
context
=
0x00200000
;
break
;
case
NV
DEV
_ENGINE_ME
:
case
NV
DEV
_ENGINE_CE0
:
context
=
0x00300000
;
break
;
case
NV
DEV
_ENGINE_VP
:
case
NV
DEV
_ENGINE_MSPDEC
:
context
=
0x00400000
;
break
;
case
NV
DEV
_ENGINE_CIPHER
:
case
NV
DEV
_ENGINE_SEC
:
case
NV
DEV
_ENGINE_VIC
:
context
=
0x00500000
;
break
;
case
NV
DEV
_ENGINE_BSP
:
case
NV
DEV
_ENGINE_MSVLD
:
context
=
0x00600000
;
break
;
case
NV
KM
_ENGINE_DMAOBJ
:
case
NV
KM
_ENGINE_SW
:
context
=
0x00000000
;
break
;
case
NV
KM
_ENGINE_GR
:
context
=
0x00100000
;
break
;
case
NV
KM
_ENGINE_MPEG
:
case
NV
KM
_ENGINE_MSPPP
:
context
=
0x00200000
;
break
;
case
NV
KM
_ENGINE_ME
:
case
NV
KM
_ENGINE_CE0
:
context
=
0x00300000
;
break
;
case
NV
KM
_ENGINE_VP
:
case
NV
KM
_ENGINE_MSPDEC
:
context
=
0x00400000
;
break
;
case
NV
KM
_ENGINE_CIPHER
:
case
NV
KM
_ENGINE_SEC
:
case
NV
KM
_ENGINE_VIC
:
context
=
0x00500000
;
break
;
case
NV
KM
_ENGINE_BSP
:
case
NV
KM
_ENGINE_MSVLD
:
context
=
0x00600000
;
break
;
default:
WARN_ON
(
1
);
return
-
EINVAL
;
...
...
@@ -243,20 +238,20 @@ g84_fifo_chan_ctor(struct nv50_fifo *fifo, u64 vm, u64 push,
ret
=
nvkm_fifo_chan_ctor
(
&
g84_fifo_chan_func
,
&
fifo
->
base
,
0x10000
,
0x1000
,
false
,
vm
,
push
,
(
1ULL
<<
NV
DEV
_ENGINE_BSP
)
|
(
1ULL
<<
NV
DEV
_ENGINE_CE0
)
|
(
1ULL
<<
NV
DEV
_ENGINE_CIPHER
)
|
(
1ULL
<<
NV
DEV
_ENGINE_DMAOBJ
)
|
(
1ULL
<<
NV
DEV
_ENGINE_GR
)
|
(
1ULL
<<
NV
DEV
_ENGINE_ME
)
|
(
1ULL
<<
NV
DEV
_ENGINE_MPEG
)
|
(
1ULL
<<
NV
DEV
_ENGINE_MSPDEC
)
|
(
1ULL
<<
NV
DEV
_ENGINE_MSPPP
)
|
(
1ULL
<<
NV
DEV
_ENGINE_MSVLD
)
|
(
1ULL
<<
NV
DEV
_ENGINE_SEC
)
|
(
1ULL
<<
NV
DEV
_ENGINE_SW
)
|
(
1ULL
<<
NV
DEV
_ENGINE_VIC
)
|
(
1ULL
<<
NV
DEV
_ENGINE_VP
),
(
1ULL
<<
NV
KM
_ENGINE_BSP
)
|
(
1ULL
<<
NV
KM
_ENGINE_CE0
)
|
(
1ULL
<<
NV
KM
_ENGINE_CIPHER
)
|
(
1ULL
<<
NV
KM
_ENGINE_DMAOBJ
)
|
(
1ULL
<<
NV
KM
_ENGINE_GR
)
|
(
1ULL
<<
NV
KM
_ENGINE_ME
)
|
(
1ULL
<<
NV
KM
_ENGINE_MPEG
)
|
(
1ULL
<<
NV
KM
_ENGINE_MSPDEC
)
|
(
1ULL
<<
NV
KM
_ENGINE_MSPPP
)
|
(
1ULL
<<
NV
KM
_ENGINE_MSVLD
)
|
(
1ULL
<<
NV
KM
_ENGINE_SEC
)
|
(
1ULL
<<
NV
KM
_ENGINE_SW
)
|
(
1ULL
<<
NV
KM
_ENGINE_VIC
)
|
(
1ULL
<<
NV
KM
_ENGINE_VP
),
0
,
0xc00000
,
0x2000
,
oclass
,
&
chan
->
base
);
chan
->
fifo
=
fifo
;
if
(
ret
)
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h
View file @
68f3f702
...
...
@@ -17,7 +17,7 @@ struct gf100_fifo_chan {
struct
{
struct
nvkm_gpuobj
*
inst
;
struct
nvkm_vma
vma
;
}
engn
[
NV
DEV
_SUBDEV_NR
];
}
engn
[
NV
KM
_SUBDEV_NR
];
};
extern
const
struct
nvkm_fifo_chan_oclass
gf100_fifo_gpfifo_oclass
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h
View file @
68f3f702
...
...
@@ -18,7 +18,7 @@ struct gk104_fifo_chan {
struct
{
struct
nvkm_gpuobj
*
inst
;
struct
nvkm_vma
vma
;
}
engn
[
NV
DEV
_SUBDEV_NR
];
}
engn
[
NV
KM
_SUBDEV_NR
];
};
int
gk104_fifo_gpfifo_new
(
struct
nvkm_fifo
*
,
const
struct
nvkm_oclass
*
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h
View file @
68f3f702
...
...
@@ -8,7 +8,7 @@ struct nv04_fifo_chan {
struct
nvkm_fifo_chan
base
;
struct
nv04_fifo
*
fifo
;
u32
ramfc
;
struct
nvkm_gpuobj
*
engn
[
NV
DEV
_SUBDEV_NR
];
struct
nvkm_gpuobj
*
engn
[
NV
KM
_SUBDEV_NR
];
};
extern
const
struct
nvkm_fifo_chan_func
nv04_fifo_dma_func
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c
View file @
68f3f702
...
...
@@ -32,10 +32,10 @@ static int
nv50_fifo_chan_engine_addr
(
struct
nvkm_engine
*
engine
)
{
switch
(
engine
->
subdev
.
index
)
{
case
NV
DEV
_ENGINE_DMAOBJ
:
case
NV
DEV
_ENGINE_SW
:
return
-
1
;
case
NV
DEV
_ENGINE_GR
:
return
0x0000
;
case
NV
DEV
_ENGINE_MPEG
:
return
0x0060
;
case
NV
KM
_ENGINE_DMAOBJ
:
case
NV
KM
_ENGINE_SW
:
return
-
1
;
case
NV
KM
_ENGINE_GR
:
return
0x0000
;
case
NV
KM
_ENGINE_MPEG
:
return
0x0060
;
default:
WARN_ON
(
1
);
return
-
1
;
...
...
@@ -130,11 +130,6 @@ nv50_fifo_chan_engine_dtor(struct nvkm_fifo_chan *base,
struct
nvkm_engine
*
engine
)
{
struct
nv50_fifo_chan
*
chan
=
nv50_fifo_chan
(
base
);
if
(
!
chan
->
engn
[
engine
->
subdev
.
index
]
||
chan
->
engn
[
engine
->
subdev
.
index
]
->
object
.
oclass
)
{
chan
->
engn
[
engine
->
subdev
.
index
]
=
NULL
;
return
;
}
nvkm_gpuobj_del
(
&
chan
->
engn
[
engine
->
subdev
.
index
]);
}
...
...
@@ -149,11 +144,6 @@ nv50_fifo_chan_engine_ctor(struct nvkm_fifo_chan *base,
if
(
nv50_fifo_chan_engine_addr
(
engine
)
<
0
)
return
0
;
if
(
nv_iclass
(
object
,
NV_GPUOBJ_CLASS
))
{
chan
->
engn
[
engn
]
=
nv_gpuobj
(
object
);
return
0
;
}
return
nvkm_object_bind
(
object
,
NULL
,
0
,
&
chan
->
engn
[
engn
]);
}
...
...
@@ -173,10 +163,10 @@ nv50_fifo_chan_object_ctor(struct nvkm_fifo_chan *base,
u32
context
;
switch
(
object
->
engine
->
subdev
.
index
)
{
case
NV
DEV
_ENGINE_DMAOBJ
:
case
NV
DEV
_ENGINE_SW
:
context
=
0x00000000
;
break
;
case
NV
DEV
_ENGINE_GR
:
context
=
0x00100000
;
break
;
case
NV
DEV
_ENGINE_MPEG
:
context
=
0x00200000
;
break
;
case
NV
KM
_ENGINE_DMAOBJ
:
case
NV
KM
_ENGINE_SW
:
context
=
0x00000000
;
break
;
case
NV
KM
_ENGINE_GR
:
context
=
0x00100000
;
break
;
case
NV
KM
_ENGINE_MPEG
:
context
=
0x00200000
;
break
;
default:
WARN_ON
(
1
);
return
-
EINVAL
;
...
...
@@ -248,10 +238,10 @@ nv50_fifo_chan_ctor(struct nv50_fifo *fifo, u64 vm, u64 push,
ret
=
nvkm_fifo_chan_ctor
(
&
nv50_fifo_chan_func
,
&
fifo
->
base
,
0x10000
,
0x1000
,
false
,
vm
,
push
,
(
1ULL
<<
NV
DEV
_ENGINE_DMAOBJ
)
|
(
1ULL
<<
NV
DEV
_ENGINE_SW
)
|
(
1ULL
<<
NV
DEV
_ENGINE_GR
)
|
(
1ULL
<<
NV
DEV
_ENGINE_MPEG
),
(
1ULL
<<
NV
KM
_ENGINE_DMAOBJ
)
|
(
1ULL
<<
NV
KM
_ENGINE_SW
)
|
(
1ULL
<<
NV
KM
_ENGINE_GR
)
|
(
1ULL
<<
NV
KM
_ENGINE_MPEG
),
0
,
0xc00000
,
0x2000
,
oclass
,
&
chan
->
base
);
chan
->
fifo
=
fifo
;
if
(
ret
)
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h
View file @
68f3f702
...
...
@@ -15,7 +15,7 @@ struct nv50_fifo_chan {
struct
nvkm_ramht
*
ramht
;
struct
nvkm_vm
*
vm
;
struct
nvkm_gpuobj
*
engn
[
NV
DEV
_SUBDEV_NR
];
struct
nvkm_gpuobj
*
engn
[
NV
KM
_SUBDEV_NR
];
};
int
nv50_fifo_chan_ctor
(
struct
nv50_fifo
*
,
u64
vm
,
u64
push
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c
View file @
68f3f702
...
...
@@ -50,10 +50,10 @@ nv04_fifo_dma_object_ctor(struct nvkm_fifo_chan *base,
int
hash
;
switch
(
object
->
engine
->
subdev
.
index
)
{
case
NV
DEV
_ENGINE_DMAOBJ
:
case
NV
DEV
_ENGINE_SW
:
context
|=
0x00000000
;
break
;
case
NV
DEV
_ENGINE_GR
:
context
|=
0x00010000
;
break
;
case
NV
DEV
_ENGINE_MPEG
:
context
|=
0x00020000
;
break
;
case
NV
KM
_ENGINE_DMAOBJ
:
case
NV
KM
_ENGINE_SW
:
context
|=
0x00000000
;
break
;
case
NV
KM
_ENGINE_GR
:
context
|=
0x00010000
;
break
;
case
NV
KM
_ENGINE_MPEG
:
context
|=
0x00020000
;
break
;
default:
WARN_ON
(
1
);
return
-
EINVAL
;
...
...
@@ -185,9 +185,9 @@ nv04_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
ret
=
nvkm_fifo_chan_ctor
(
&
nv04_fifo_dma_func
,
&
fifo
->
base
,
0x1000
,
0x1000
,
false
,
0
,
args
->
v0
.
pushbuf
,
(
1ULL
<<
NV
DEV
_ENGINE_DMAOBJ
)
|
(
1ULL
<<
NV
DEV
_ENGINE_GR
)
|
(
1ULL
<<
NV
DEV
_ENGINE_SW
),
(
1ULL
<<
NV
KM
_ENGINE_DMAOBJ
)
|
(
1ULL
<<
NV
KM
_ENGINE_GR
)
|
(
1ULL
<<
NV
KM
_ENGINE_SW
),
0
,
0x800000
,
0x10000
,
oclass
,
&
chan
->
base
);
chan
->
fifo
=
fifo
;
if
(
ret
)
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c
View file @
68f3f702
...
...
@@ -61,9 +61,9 @@ nv10_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
ret
=
nvkm_fifo_chan_ctor
(
&
nv04_fifo_dma_func
,
&
fifo
->
base
,
0x1000
,
0x1000
,
false
,
0
,
args
->
v0
.
pushbuf
,
(
1ULL
<<
NV
DEV
_ENGINE_DMAOBJ
)
|
(
1ULL
<<
NV
DEV
_ENGINE_GR
)
|
(
1ULL
<<
NV
DEV
_ENGINE_SW
),
(
1ULL
<<
NV
KM
_ENGINE_DMAOBJ
)
|
(
1ULL
<<
NV
KM
_ENGINE_GR
)
|
(
1ULL
<<
NV
KM
_ENGINE_SW
),
0
,
0x800000
,
0x10000
,
oclass
,
&
chan
->
base
);
chan
->
fifo
=
fifo
;
if
(
ret
)
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c
View file @
68f3f702
...
...
@@ -61,10 +61,10 @@ nv17_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
ret
=
nvkm_fifo_chan_ctor
(
&
nv04_fifo_dma_func
,
&
fifo
->
base
,
0x1000
,
0x1000
,
false
,
0
,
args
->
v0
.
pushbuf
,
(
1ULL
<<
NV
DEV
_ENGINE_DMAOBJ
)
|
(
1ULL
<<
NV
DEV
_ENGINE_GR
)
|
(
1ULL
<<
NV
DEV
_ENGINE_MPEG
)
|
/* NV31- */
(
1ULL
<<
NV
DEV
_ENGINE_SW
),
(
1ULL
<<
NV
KM
_ENGINE_DMAOBJ
)
|
(
1ULL
<<
NV
KM
_ENGINE_GR
)
|
(
1ULL
<<
NV
KM
_ENGINE_MPEG
)
|
/* NV31- */
(
1ULL
<<
NV
KM
_ENGINE_SW
),
0
,
0x800000
,
0x10000
,
oclass
,
&
chan
->
base
);
chan
->
fifo
=
fifo
;
if
(
ret
)
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c
View file @
68f3f702
...
...
@@ -35,14 +35,14 @@ static bool
nv40_fifo_dma_engine
(
struct
nvkm_engine
*
engine
,
u32
*
reg
,
u32
*
ctx
)
{
switch
(
engine
->
subdev
.
index
)
{
case
NV
DEV
_ENGINE_DMAOBJ
:
case
NV
DEV
_ENGINE_SW
:
case
NV
KM
_ENGINE_DMAOBJ
:
case
NV
KM
_ENGINE_SW
:
return
false
;
case
NV
DEV
_ENGINE_GR
:
case
NV
KM
_ENGINE_GR
:
*
reg
=
0x0032e0
;
*
ctx
=
0x38
;
return
true
;
case
NV
DEV
_ENGINE_MPEG
:
case
NV
KM
_ENGINE_MPEG
:
*
reg
=
0x00330c
;
*
ctx
=
0x54
;
return
true
;
...
...
@@ -118,11 +118,6 @@ nv40_fifo_dma_engine_dtor(struct nvkm_fifo_chan *base,
struct
nvkm_engine
*
engine
)
{
struct
nv04_fifo_chan
*
chan
=
nv04_fifo_chan
(
base
);
if
(
!
chan
->
engn
[
engine
->
subdev
.
index
]
||
chan
->
engn
[
engine
->
subdev
.
index
]
->
object
.
oclass
)
{
chan
->
engn
[
engine
->
subdev
.
index
]
=
NULL
;
return
;
}
nvkm_gpuobj_del
(
&
chan
->
engn
[
engine
->
subdev
.
index
]);
}
...
...
@@ -138,11 +133,6 @@ nv40_fifo_dma_engine_ctor(struct nvkm_fifo_chan *base,
if
(
!
nv40_fifo_dma_engine
(
engine
,
&
reg
,
&
ctx
))
return
0
;
if
(
nv_iclass
(
object
,
NV_GPUOBJ_CLASS
))
{
chan
->
engn
[
engn
]
=
nv_gpuobj
(
object
);
return
0
;
}
return
nvkm_object_bind
(
object
,
NULL
,
0
,
&
chan
->
engn
[
engn
]);
}
...
...
@@ -157,10 +147,10 @@ nv40_fifo_dma_object_ctor(struct nvkm_fifo_chan *base,
int
hash
;
switch
(
object
->
engine
->
subdev
.
index
)
{
case
NV
DEV
_ENGINE_DMAOBJ
:
case
NV
DEV
_ENGINE_SW
:
context
|=
0x00000000
;
break
;
case
NV
DEV
_ENGINE_GR
:
context
|=
0x00100000
;
break
;
case
NV
DEV
_ENGINE_MPEG
:
context
|=
0x00200000
;
break
;
case
NV
KM
_ENGINE_DMAOBJ
:
case
NV
KM
_ENGINE_SW
:
context
|=
0x00000000
;
break
;
case
NV
KM
_ENGINE_GR
:
context
|=
0x00100000
;
break
;
case
NV
KM
_ENGINE_MPEG
:
context
|=
0x00200000
;
break
;
default:
WARN_ON
(
1
);
return
-
EINVAL
;
...
...
@@ -216,10 +206,10 @@ nv40_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
ret
=
nvkm_fifo_chan_ctor
(
&
nv40_fifo_dma_func
,
&
fifo
->
base
,
0x1000
,
0x1000
,
false
,
0
,
args
->
v0
.
pushbuf
,
(
1ULL
<<
NV
DEV
_ENGINE_DMAOBJ
)
|
(
1ULL
<<
NV
DEV
_ENGINE_GR
)
|
(
1ULL
<<
NV
DEV
_ENGINE_MPEG
)
|
(
1ULL
<<
NV
DEV
_ENGINE_SW
),
(
1ULL
<<
NV
KM
_ENGINE_DMAOBJ
)
|
(
1ULL
<<
NV
KM
_ENGINE_GR
)
|
(
1ULL
<<
NV
KM
_ENGINE_MPEG
)
|
(
1ULL
<<
NV
KM
_ENGINE_SW
),
0
,
0xc00000
,
0x1000
,
oclass
,
&
chan
->
base
);
chan
->
fifo
=
fifo
;
if
(
ret
)
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
View file @
68f3f702
...
...
@@ -82,12 +82,12 @@ static inline int
gf100_fifo_engidx
(
struct
gf100_fifo
*
fifo
,
u32
engn
)
{
switch
(
engn
)
{
case
NV
DEV
_ENGINE_GR
:
engn
=
0
;
break
;
case
NV
DEV
_ENGINE_MSVLD
:
engn
=
1
;
break
;
case
NV
DEV
_ENGINE_MSPPP
:
engn
=
2
;
break
;
case
NV
DEV
_ENGINE_MSPDEC
:
engn
=
3
;
break
;
case
NV
DEV
_ENGINE_CE0
:
engn
=
4
;
break
;
case
NV
DEV
_ENGINE_CE1
:
engn
=
5
;
break
;
case
NV
KM
_ENGINE_GR
:
engn
=
0
;
break
;
case
NV
KM
_ENGINE_MSVLD
:
engn
=
1
;
break
;
case
NV
KM
_ENGINE_MSPPP
:
engn
=
2
;
break
;
case
NV
KM
_ENGINE_MSPDEC
:
engn
=
3
;
break
;
case
NV
KM
_ENGINE_CE0
:
engn
=
4
;
break
;
case
NV
KM
_ENGINE_CE1
:
engn
=
5
;
break
;
default:
return
-
1
;
}
...
...
@@ -101,12 +101,12 @@ gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn)
struct
nvkm_device
*
device
=
fifo
->
base
.
engine
.
subdev
.
device
;
switch
(
engn
)
{
case
0
:
engn
=
NV
DEV
_ENGINE_GR
;
break
;
case
1
:
engn
=
NV
DEV
_ENGINE_MSVLD
;
break
;
case
2
:
engn
=
NV
DEV
_ENGINE_MSPPP
;
break
;
case
3
:
engn
=
NV
DEV
_ENGINE_MSPDEC
;
break
;
case
4
:
engn
=
NV
DEV
_ENGINE_CE0
;
break
;
case
5
:
engn
=
NV
DEV
_ENGINE_CE1
;
break
;
case
0
:
engn
=
NV
KM
_ENGINE_GR
;
break
;
case
1
:
engn
=
NV
KM
_ENGINE_MSVLD
;
break
;
case
2
:
engn
=
NV
KM
_ENGINE_MSPPP
;
break
;
case
3
:
engn
=
NV
KM
_ENGINE_MSPDEC
;
break
;
case
4
:
engn
=
NV
KM
_ENGINE_CE0
;
break
;
case
5
:
engn
=
NV
KM
_ENGINE_CE1
;
break
;
default:
return
NULL
;
}
...
...
@@ -229,17 +229,17 @@ gf100_fifo_intr_sched(struct gf100_fifo *fifo)
static
const
struct
nvkm_enum
gf100_fifo_fault_engine
[]
=
{
{
0x00
,
"PGRAPH"
,
NULL
,
NV
DEV
_ENGINE_GR
},
{
0x03
,
"PEEPHOLE"
,
NULL
,
NV
DEV
_ENGINE_IFB
},
{
0x04
,
"BAR1"
,
NULL
,
NV
DEV
_SUBDEV_BAR
},
{
0x05
,
"BAR3"
,
NULL
,
NV
DEV
_SUBDEV_INSTMEM
},
{
0x07
,
"PFIFO"
,
NULL
,
NV
DEV
_ENGINE_FIFO
},
{
0x10
,
"PMSVLD"
,
NULL
,
NV
DEV
_ENGINE_MSVLD
},
{
0x11
,
"PMSPPP"
,
NULL
,
NV
DEV
_ENGINE_MSPPP
},
{
0x00
,
"PGRAPH"
,
NULL
,
NV
KM
_ENGINE_GR
},
{
0x03
,
"PEEPHOLE"
,
NULL
,
NV
KM
_ENGINE_IFB
},
{
0x04
,
"BAR1"
,
NULL
,
NV
KM
_SUBDEV_BAR
},
{
0x05
,
"BAR3"
,
NULL
,
NV
KM
_SUBDEV_INSTMEM
},
{
0x07
,
"PFIFO"
,
NULL
,
NV
KM
_ENGINE_FIFO
},
{
0x10
,
"PMSVLD"
,
NULL
,
NV
KM
_ENGINE_MSVLD
},
{
0x11
,
"PMSPPP"
,
NULL
,
NV
KM
_ENGINE_MSPPP
},
{
0x13
,
"PCOUNTER"
},
{
0x14
,
"PMSPDEC"
,
NULL
,
NV
DEV
_ENGINE_MSPDEC
},
{
0x15
,
"PCE0"
,
NULL
,
NV
DEV
_ENGINE_CE0
},
{
0x16
,
"PCE1"
,
NULL
,
NV
DEV
_ENGINE_CE1
},
{
0x14
,
"PMSPDEC"
,
NULL
,
NV
KM
_ENGINE_MSPDEC
},
{
0x15
,
"PCE0"
,
NULL
,
NV
KM
_ENGINE_CE0
},
{
0x16
,
"PCE1"
,
NULL
,
NV
KM
_ENGINE_CE1
},
{
0x17
,
"PDAEMON"
},
{}
};
...
...
@@ -317,13 +317,13 @@ gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit)
if
(
eu
)
{
switch
(
eu
->
data2
)
{
case
NV
DEV
_SUBDEV_BAR
:
case
NV
KM
_SUBDEV_BAR
:
nvkm_mask
(
device
,
0x001704
,
0x00000000
,
0x00000000
);
break
;
case
NV
DEV
_SUBDEV_INSTMEM
:
case
NV
KM
_SUBDEV_INSTMEM
:
nvkm_mask
(
device
,
0x001714
,
0x00000000
,
0x00000000
);
break
;
case
NV
DEV
_ENGINE_IFB
:
case
NV
KM
_ENGINE_IFB
:
nvkm_mask
(
device
,
0x001718
,
0x00000000
,
0x00000000
);
break
;
default:
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
View file @
68f3f702
...
...
@@ -248,22 +248,22 @@ gk104_fifo_intr_dropped_fault(struct gk104_fifo *fifo)
static
const
struct
nvkm_enum
gk104_fifo_fault_engine
[]
=
{
{
0x00
,
"GR"
,
NULL
,
NV
DEV
_ENGINE_GR
},
{
0x03
,
"IFB"
,
NULL
,
NV
DEV
_ENGINE_IFB
},
{
0x04
,
"BAR1"
,
NULL
,
NV
DEV
_SUBDEV_BAR
},
{
0x05
,
"BAR3"
,
NULL
,
NV
DEV
_SUBDEV_INSTMEM
},
{
0x07
,
"PBDMA0"
,
NULL
,
NV
DEV
_ENGINE_FIFO
},
{
0x08
,
"PBDMA1"
,
NULL
,
NV
DEV
_ENGINE_FIFO
},
{
0x09
,
"PBDMA2"
,
NULL
,
NV
DEV
_ENGINE_FIFO
},
{
0x10
,
"MSVLD"
,
NULL
,
NV
DEV
_ENGINE_MSVLD
},
{
0x11
,
"MSPPP"
,
NULL
,
NV
DEV
_ENGINE_MSPPP
},
{
0x00
,
"GR"
,
NULL
,
NV
KM
_ENGINE_GR
},
{
0x03
,
"IFB"
,
NULL
,
NV
KM
_ENGINE_IFB
},
{
0x04
,
"BAR1"
,
NULL
,
NV
KM
_SUBDEV_BAR
},
{
0x05
,
"BAR3"
,
NULL
,
NV
KM
_SUBDEV_INSTMEM
},
{
0x07
,
"PBDMA0"
,
NULL
,
NV
KM
_ENGINE_FIFO
},
{
0x08
,
"PBDMA1"
,
NULL
,
NV
KM
_ENGINE_FIFO
},
{
0x09
,
"PBDMA2"
,
NULL
,
NV
KM
_ENGINE_FIFO
},
{
0x10
,
"MSVLD"
,
NULL
,
NV
KM
_ENGINE_MSVLD
},
{
0x11
,
"MSPPP"
,
NULL
,
NV
KM
_ENGINE_MSPPP
},
{
0x13
,
"PERF"
},
{
0x14
,
"MSPDEC"
,
NULL
,
NV
DEV
_ENGINE_MSPDEC
},
{
0x15
,
"CE0"
,
NULL
,
NV
DEV
_ENGINE_CE0
},
{
0x16
,
"CE1"
,
NULL
,
NV
DEV
_ENGINE_CE1
},
{
0x14
,
"MSPDEC"
,
NULL
,
NV
KM
_ENGINE_MSPDEC
},
{
0x15
,
"CE0"
,
NULL
,
NV
KM
_ENGINE_CE0
},
{
0x16
,
"CE1"
,
NULL
,
NV
KM
_ENGINE_CE1
},
{
0x17
,
"PMU"
},
{
0x19
,
"MSENC"
,
NULL
,
NV
DEV
_ENGINE_MSENC
},
{
0x1b
,
"CE2"
,
NULL
,
NV
DEV
_ENGINE_CE2
},
{
0x19
,
"MSENC"
,
NULL
,
NV
KM
_ENGINE_MSENC
},
{
0x1b
,
"CE2"
,
NULL
,
NV
KM
_ENGINE_CE2
},
{}
};
...
...
@@ -382,13 +382,13 @@ gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit)
if
(
eu
)
{
switch
(
eu
->
data2
)
{
case
NV
DEV
_SUBDEV_BAR
:
case
NV
KM
_SUBDEV_BAR
:
nvkm_mask
(
device
,
0x001704
,
0x00000000
,
0x00000000
);
break
;
case
NV
DEV
_SUBDEV_INSTMEM
:
case
NV
KM
_SUBDEV_INSTMEM
:
nvkm_mask
(
device
,
0x001714
,
0x00000000
,
0x00000000
);
break
;
case
NV
DEV
_ENGINE_IFB
:
case
NV
KM
_ENGINE_IFB
:
nvkm_mask
(
device
,
0x001718
,
0x00000000
,
0x00000000
);
break
;
default:
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
View file @
68f3f702
...
...
@@ -41,15 +41,15 @@ static inline u64
gk104_fifo_engine_subdev
(
int
engine
)
{
switch
(
engine
)
{
case
0
:
return
(
1ULL
<<
NV
DEV
_ENGINE_GR
)
|
(
1ULL
<<
NV
DEV
_ENGINE_SW
)
|
(
1ULL
<<
NV
DEV
_ENGINE_CE2
);
case
1
:
return
(
1ULL
<<
NV
DEV
_ENGINE_MSPDEC
);
case
2
:
return
(
1ULL
<<
NV
DEV
_ENGINE_MSPPP
);
case
3
:
return
(
1ULL
<<
NV
DEV
_ENGINE_MSVLD
);
case
4
:
return
(
1ULL
<<
NV
DEV
_ENGINE_CE0
);
case
5
:
return
(
1ULL
<<
NV
DEV
_ENGINE_CE1
);
case
6
:
return
(
1ULL
<<
NV
DEV
_ENGINE_MSENC
);
case
0
:
return
(
1ULL
<<
NV
KM
_ENGINE_GR
)
|
(
1ULL
<<
NV
KM
_ENGINE_SW
)
|
(
1ULL
<<
NV
KM
_ENGINE_CE2
);
case
1
:
return
(
1ULL
<<
NV
KM
_ENGINE_MSPDEC
);
case
2
:
return
(
1ULL
<<
NV
KM
_ENGINE_MSPPP
);
case
3
:
return
(
1ULL
<<
NV
KM
_ENGINE_MSVLD
);
case
4
:
return
(
1ULL
<<
NV
KM
_ENGINE_CE0
);
case
5
:
return
(
1ULL
<<
NV
KM
_ENGINE_CE1
);
case
6
:
return
(
1ULL
<<
NV
KM
_ENGINE_MSENC
);
default:
WARN_ON
(
1
);
return
0
;
...
...
@@ -60,15 +60,15 @@ static inline int
gk104_fifo_subdev_engine
(
int
subdev
)
{
switch
(
subdev
)
{
case
NV
DEV
_ENGINE_GR
:
case
NV
DEV
_ENGINE_SW
:
case
NV
DEV
_ENGINE_CE2
:
return
0
;
case
NV
DEV
_ENGINE_MSPDEC
:
return
1
;
case
NV
DEV
_ENGINE_MSPPP
:
return
2
;
case
NV
DEV
_ENGINE_MSVLD
:
return
3
;
case
NV
DEV
_ENGINE_CE0
:
return
4
;
case
NV
DEV
_ENGINE_CE1
:
return
5
;
case
NV
DEV
_ENGINE_MSENC
:
return
6
;
case
NV
KM
_ENGINE_GR
:
case
NV
KM
_ENGINE_SW
:
case
NV
KM
_ENGINE_CE2
:
return
0
;
case
NV
KM
_ENGINE_MSPDEC
:
return
1
;
case
NV
KM
_ENGINE_MSPPP
:
return
2
;
case
NV
KM
_ENGINE_MSVLD
:
return
3
;
case
NV
KM
_ENGINE_CE0
:
return
4
;
case
NV
KM
_ENGINE_CE1
:
return
5
;
case
NV
KM
_ENGINE_MSENC
:
return
6
;
default:
WARN_ON
(
1
);
return
0
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c
View file @
68f3f702
...
...
@@ -35,13 +35,13 @@ static u32
gf100_fifo_gpfifo_engine_addr
(
struct
nvkm_engine
*
engine
)
{
switch
(
engine
->
subdev
.
index
)
{
case
NV
DEV
_ENGINE_SW
:
return
0
;
case
NV
DEV
_ENGINE_GR
:
return
0x0210
;
case
NV
DEV
_ENGINE_CE0
:
return
0x0230
;
case
NV
DEV
_ENGINE_CE1
:
return
0x0240
;
case
NV
DEV
_ENGINE_MSPDEC
:
return
0x0250
;
case
NV
DEV
_ENGINE_MSPPP
:
return
0x0260
;
case
NV
DEV
_ENGINE_MSVLD
:
return
0x0270
;
case
NV
KM
_ENGINE_SW
:
return
0
;
case
NV
KM
_ENGINE_GR
:
return
0x0210
;
case
NV
KM
_ENGINE_CE0
:
return
0x0230
;
case
NV
KM
_ENGINE_CE1
:
return
0x0240
;
case
NV
KM
_ENGINE_MSPDEC
:
return
0x0250
;
case
NV
KM
_ENGINE_MSPPP
:
return
0x0260
;
case
NV
KM
_ENGINE_MSVLD
:
return
0x0270
;
default:
WARN_ON
(
1
);
return
0
;
...
...
@@ -121,12 +121,6 @@ gf100_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base,
if
(
!
gf100_fifo_gpfifo_engine_addr
(
engine
))
return
0
;
if
(
object
->
oclass
)
{
return
nvkm_gpuobj_map
(
nv_gpuobj
(
object
),
chan
->
vm
,
NV_MEM_ACCESS_RW
,
&
chan
->
engn
[
engn
].
vma
);
}
ret
=
nvkm_object_bind
(
object
,
NULL
,
0
,
&
chan
->
engn
[
engn
].
inst
);
if
(
ret
)
return
ret
;
...
...
@@ -225,13 +219,13 @@ gf100_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
ret
=
nvkm_fifo_chan_ctor
(
&
gf100_fifo_gpfifo_func
,
&
fifo
->
base
,
0x1000
,
0x1000
,
true
,
args
->
v0
.
vm
,
0
,
(
1ULL
<<
NV
DEV
_ENGINE_CE0
)
|
(
1ULL
<<
NV
DEV
_ENGINE_CE1
)
|
(
1ULL
<<
NV
DEV
_ENGINE_GR
)
|
(
1ULL
<<
NV
DEV
_ENGINE_MSPDEC
)
|
(
1ULL
<<
NV
DEV
_ENGINE_MSPPP
)
|
(
1ULL
<<
NV
DEV
_ENGINE_MSVLD
)
|
(
1ULL
<<
NV
DEV
_ENGINE_SW
),
(
1ULL
<<
NV
KM
_ENGINE_CE0
)
|
(
1ULL
<<
NV
KM
_ENGINE_CE1
)
|
(
1ULL
<<
NV
KM
_ENGINE_GR
)
|
(
1ULL
<<
NV
KM
_ENGINE_MSPDEC
)
|
(
1ULL
<<
NV
KM
_ENGINE_MSPPP
)
|
(
1ULL
<<
NV
KM
_ENGINE_MSVLD
)
|
(
1ULL
<<
NV
KM
_ENGINE_SW
),
1
,
fifo
->
user
.
bar
.
offset
,
0x1000
,
oclass
,
&
chan
->
base
);
if
(
ret
)
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
View file @
68f3f702
...
...
@@ -57,14 +57,14 @@ static u32
gk104_fifo_gpfifo_engine_addr
(
struct
nvkm_engine
*
engine
)
{
switch
(
engine
->
subdev
.
index
)
{
case
NV
DEV
_ENGINE_SW
:
case
NV
DEV
_ENGINE_CE0
:
case
NV
DEV
_ENGINE_CE1
:
case
NV
DEV
_ENGINE_CE2
:
return
0x0000
;
case
NV
DEV
_ENGINE_GR
:
return
0x0210
;
case
NV
DEV
_ENGINE_MSPDEC
:
return
0x0250
;
case
NV
DEV
_ENGINE_MSPPP
:
return
0x0260
;
case
NV
DEV
_ENGINE_MSVLD
:
return
0x0270
;
case
NV
KM
_ENGINE_SW
:
case
NV
KM
_ENGINE_CE0
:
case
NV
KM
_ENGINE_CE1
:
case
NV
KM
_ENGINE_CE2
:
return
0x0000
;
case
NV
KM
_ENGINE_GR
:
return
0x0210
;
case
NV
KM
_ENGINE_MSPDEC
:
return
0x0250
;
case
NV
KM
_ENGINE_MSPPP
:
return
0x0260
;
case
NV
KM
_ENGINE_MSVLD
:
return
0x0270
;
default:
WARN_ON
(
1
);
return
0
;
...
...
@@ -134,12 +134,6 @@ gk104_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base,
if
(
!
gk104_fifo_gpfifo_engine_addr
(
engine
))
return
0
;
if
(
object
->
oclass
)
{
return
nvkm_gpuobj_map
(
nv_gpuobj
(
object
),
chan
->
vm
,
NV_MEM_ACCESS_RW
,
&
chan
->
engn
[
engn
].
vma
);
}
ret
=
nvkm_object_bind
(
object
,
NULL
,
0
,
&
chan
->
engn
[
engn
].
inst
);
if
(
ret
)
return
ret
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
View file @
68f3f702
...
...
@@ -1047,7 +1047,7 @@ nv04_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
false
,
parent
,
pgpuobj
);
if
(
ret
==
0
)
{
nvkm_kmap
(
*
pgpuobj
);
nvkm_wo32
(
*
pgpuobj
,
0x00
,
object
->
oclass
_name
);
nvkm_wo32
(
*
pgpuobj
,
0x00
,
object
->
oclass
);
nvkm_wo32
(
*
pgpuobj
,
0x04
,
0x00000000
);
nvkm_wo32
(
*
pgpuobj
,
0x08
,
0x00000000
);
#ifdef __BIG_ENDIAN
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
View file @
68f3f702
...
...
@@ -48,7 +48,7 @@ nv40_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
false
,
parent
,
pgpuobj
);
if
(
ret
==
0
)
{
nvkm_kmap
(
*
pgpuobj
);
nvkm_wo32
(
*
pgpuobj
,
0x00
,
object
->
oclass
_name
);
nvkm_wo32
(
*
pgpuobj
,
0x00
,
object
->
oclass
);
nvkm_wo32
(
*
pgpuobj
,
0x04
,
0x00000000
);
nvkm_wo32
(
*
pgpuobj
,
0x08
,
0x00000000
);
#ifdef __BIG_ENDIAN
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
View file @
68f3f702
...
...
@@ -45,7 +45,7 @@ nv50_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
align
,
false
,
parent
,
pgpuobj
);
if
(
ret
==
0
)
{
nvkm_kmap
(
*
pgpuobj
);
nvkm_wo32
(
*
pgpuobj
,
0x00
,
object
->
oclass
_name
);
nvkm_wo32
(
*
pgpuobj
,
0x00
,
object
->
oclass
);
nvkm_wo32
(
*
pgpuobj
,
0x04
,
0x00000000
);
nvkm_wo32
(
*
pgpuobj
,
0x08
,
0x00000000
);
nvkm_wo32
(
*
pgpuobj
,
0x0c
,
0x00000000
);
...
...
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
View file @
68f3f702
...
...
@@ -43,7 +43,7 @@ nv31_mpeg_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
false
,
parent
,
pgpuobj
);
if
(
ret
==
0
)
{
nvkm_kmap
(
*
pgpuobj
);
nvkm_wo32
(
*
pgpuobj
,
0x00
,
object
->
oclass
_name
);
nvkm_wo32
(
*
pgpuobj
,
0x00
,
object
->
oclass
);
nvkm_wo32
(
*
pgpuobj
,
0x04
,
0x00000000
);
nvkm_wo32
(
*
pgpuobj
,
0x08
,
0x00000000
);
nvkm_wo32
(
*
pgpuobj
,
0x0c
,
0x00000000
);
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
View file @
68f3f702
...
...
@@ -64,7 +64,7 @@ gf100_bar_ctor_vm(struct gf100_bar *bar, struct gf100_bar_vm *bar_vm,
if
(
ret
)
return
ret
;
atomic_inc
(
&
vm
->
engref
[
NV
DEV
_SUBDEV_BAR
]);
atomic_inc
(
&
vm
->
engref
[
NV
KM
_SUBDEV_BAR
]);
/*
* Bootstrap page table lookup.
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
View file @
68f3f702
...
...
@@ -88,7 +88,7 @@ nv50_bar_oneinit(struct nvkm_bar *base)
if
(
ret
)
return
ret
;
atomic_inc
(
&
vm
->
engref
[
NV
DEV
_SUBDEV_BAR
]);
atomic_inc
(
&
vm
->
engref
[
NV
KM
_SUBDEV_BAR
]);
ret
=
nvkm_vm_boot
(
vm
,
limit
--
-
start
);
if
(
ret
)
...
...
@@ -121,7 +121,7 @@ nv50_bar_oneinit(struct nvkm_bar *base)
if
(
ret
)
return
ret
;
atomic_inc
(
&
vm
->
engref
[
NV
DEV
_SUBDEV_BAR
]);
atomic_inc
(
&
vm
->
engref
[
NV
KM
_SUBDEV_BAR
]);
ret
=
nvkm_vm_ref
(
vm
,
&
bar
->
bar1_vm
,
bar
->
pgd
);
nvkm_vm_ref
(
NULL
,
&
vm
,
NULL
);
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c
View file @
68f3f702
...
...
@@ -35,18 +35,18 @@ g84_devinit_disable(struct nvkm_devinit *init)
u64
disable
=
0ULL
;
if
(
!
(
r001540
&
0x40000000
))
{
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_MPEG
);
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_VP
);
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_BSP
);
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_CIPHER
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_MPEG
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_VP
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_BSP
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_CIPHER
);
}
if
(
!
(
r00154c
&
0x00000004
))
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_DISP
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_DISP
);
if
(
!
(
r00154c
&
0x00000020
))
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_BSP
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_BSP
);
if
(
!
(
r00154c
&
0x00000040
))
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_CIPHER
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_CIPHER
);
return
disable
;
}
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c
View file @
68f3f702
...
...
@@ -35,17 +35,17 @@ g98_devinit_disable(struct nvkm_devinit *init)
u64
disable
=
0ULL
;
if
(
!
(
r001540
&
0x40000000
))
{
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_MSPDEC
);
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_MSVLD
);
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_MSPPP
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_MSPDEC
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_MSVLD
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_MSPPP
);
}
if
(
!
(
r00154c
&
0x00000004
))
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_DISP
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_DISP
);
if
(
!
(
r00154c
&
0x00000020
))
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_MSVLD
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_MSVLD
);
if
(
!
(
r00154c
&
0x00000040
))
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_SEC
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_SEC
);
return
disable
;
}
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
View file @
68f3f702
...
...
@@ -71,21 +71,21 @@ gf100_devinit_disable(struct nvkm_devinit *init)
u64
disable
=
0ULL
;
if
(
r022500
&
0x00000001
)
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_DISP
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_DISP
);
if
(
r022500
&
0x00000002
)
{
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_MSPDEC
);
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_MSPPP
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_MSPDEC
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_MSPPP
);
}
if
(
r022500
&
0x00000004
)
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_MSVLD
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_MSVLD
);
if
(
r022500
&
0x00000008
)
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_MSENC
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_MSENC
);
if
(
r022500
&
0x00000100
)
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_CE0
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_CE0
);
if
(
r022500
&
0x00000200
)
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_CE1
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_CE1
);
return
disable
;
}
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c
View file @
68f3f702
...
...
@@ -35,11 +35,11 @@ gm107_devinit_disable(struct nvkm_devinit *init)
u64
disable
=
0ULL
;
if
(
r021c00
&
0x00000001
)
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_CE0
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_CE0
);
if
(
r021c00
&
0x00000004
)
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_CE2
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_CE2
);
if
(
r021c04
&
0x00000001
)
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_DISP
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_DISP
);
return
disable
;
}
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
View file @
68f3f702
...
...
@@ -71,16 +71,16 @@ gt215_devinit_disable(struct nvkm_devinit *init)
u64
disable
=
0ULL
;
if
(
!
(
r001540
&
0x40000000
))
{
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_MSPDEC
);
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_MSPPP
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_MSPDEC
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_MSPPP
);
}
if
(
!
(
r00154c
&
0x00000004
))
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_DISP
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_DISP
);
if
(
!
(
r00154c
&
0x00000020
))
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_MSVLD
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_MSVLD
);
if
(
!
(
r00154c
&
0x00000200
))
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_CE0
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_CE0
);
return
disable
;
}
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c
View file @
68f3f702
...
...
@@ -35,18 +35,18 @@ mcp89_devinit_disable(struct nvkm_devinit *init)
u64
disable
=
0
;
if
(
!
(
r001540
&
0x40000000
))
{
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_MSPDEC
);
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_MSPPP
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_MSPDEC
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_MSPPP
);
}
if
(
!
(
r00154c
&
0x00000004
))
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_DISP
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_DISP
);
if
(
!
(
r00154c
&
0x00000020
))
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_MSVLD
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_MSVLD
);
if
(
!
(
r00154c
&
0x00000040
))
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_VIC
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_VIC
);
if
(
!
(
r00154c
&
0x00000200
))
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_CE0
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_CE0
);
return
disable
;
}
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c
View file @
68f3f702
...
...
@@ -85,7 +85,7 @@ nv50_devinit_disable(struct nvkm_devinit *init)
u64
disable
=
0ULL
;
if
(
!
(
r001540
&
0x40000000
))
disable
|=
(
1ULL
<<
NV
DEV
_ENGINE_MPEG
);
disable
|=
(
1ULL
<<
NV
KM
_ENGINE_MPEG
);
return
disable
;
}
...
...
@@ -103,7 +103,7 @@ nv50_devinit_preinit(struct nvkm_devinit *base)
*/
if
(
!
init
->
base
.
post
)
{
u64
disable
=
nvkm_devinit_disable
(
&
init
->
base
);
if
(
disable
&
(
1ULL
<<
NV
DEV
_ENGINE_DISP
))
if
(
disable
&
(
1ULL
<<
NV
KM
_ENGINE_DISP
))
init
->
base
.
post
=
true
;
}
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c
View file @
68f3f702
...
...
@@ -25,22 +25,22 @@
static
const
struct
nvkm_mc_intr
g98_mc_intr
[]
=
{
{
0x04000000
,
NV
DEV
_ENGINE_DISP
},
/* DISP first, so pageflip timestamps work */
{
0x00000001
,
NV
DEV
_ENGINE_MSPPP
},
{
0x00000100
,
NV
DEV
_ENGINE_FIFO
},
{
0x00001000
,
NV
DEV
_ENGINE_GR
},
{
0x00004000
,
NV
DEV
_ENGINE_SEC
},
/* NV84:NVA3 */
{
0x00008000
,
NV
DEV
_ENGINE_MSVLD
},
{
0x00020000
,
NV
DEV
_ENGINE_MSPDEC
},
{
0x00040000
,
NV
DEV
_SUBDEV_PMU
},
/* NVA3:NVC0 */
{
0x00080000
,
NV
DEV
_SUBDEV_THERM
},
/* NVA3:NVC0 */
{
0x00100000
,
NV
DEV
_SUBDEV_TIMER
},
{
0x00200000
,
NV
DEV
_SUBDEV_GPIO
},
/* PMGR->GPIO */
{
0x00200000
,
NV
DEV
_SUBDEV_I2C
},
/* PMGR->I2C/AUX */
{
0x00400000
,
NV
DEV
_ENGINE_CE0
},
/* NVA3- */
{
0x10000000
,
NV
DEV
_SUBDEV_BUS
},
{
0x80000000
,
NV
DEV
_ENGINE_SW
},
{
0x0042d101
,
NV
DEV
_SUBDEV_FB
},
{
0x04000000
,
NV
KM
_ENGINE_DISP
},
/* DISP first, so pageflip timestamps work */
{
0x00000001
,
NV
KM
_ENGINE_MSPPP
},
{
0x00000100
,
NV
KM
_ENGINE_FIFO
},
{
0x00001000
,
NV
KM
_ENGINE_GR
},
{
0x00004000
,
NV
KM
_ENGINE_SEC
},
/* NV84:NVA3 */
{
0x00008000
,
NV
KM
_ENGINE_MSVLD
},
{
0x00020000
,
NV
KM
_ENGINE_MSPDEC
},
{
0x00040000
,
NV
KM
_SUBDEV_PMU
},
/* NVA3:NVC0 */
{
0x00080000
,
NV
KM
_SUBDEV_THERM
},
/* NVA3:NVC0 */
{
0x00100000
,
NV
KM
_SUBDEV_TIMER
},
{
0x00200000
,
NV
KM
_SUBDEV_GPIO
},
/* PMGR->GPIO */
{
0x00200000
,
NV
KM
_SUBDEV_I2C
},
/* PMGR->I2C/AUX */
{
0x00400000
,
NV
KM
_ENGINE_CE0
},
/* NVA3- */
{
0x10000000
,
NV
KM
_SUBDEV_BUS
},
{
0x80000000
,
NV
KM
_ENGINE_SW
},
{
0x0042d101
,
NV
KM
_SUBDEV_FB
},
{},
};
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c
View file @
68f3f702
...
...
@@ -25,26 +25,26 @@
const
struct
nvkm_mc_intr
gf100_mc_intr
[]
=
{
{
0x04000000
,
NV
DEV
_ENGINE_DISP
},
/* DISP first, so pageflip timestamps work. */
{
0x00000001
,
NV
DEV
_ENGINE_MSPPP
},
{
0x00000020
,
NV
DEV
_ENGINE_CE0
},
{
0x00000040
,
NV
DEV
_ENGINE_CE1
},
{
0x00000080
,
NV
DEV
_ENGINE_CE2
},
{
0x00000100
,
NV
DEV
_ENGINE_FIFO
},
{
0x00001000
,
NV
DEV
_ENGINE_GR
},
{
0x00002000
,
NV
DEV
_SUBDEV_FB
},
{
0x00008000
,
NV
DEV
_ENGINE_MSVLD
},
{
0x00040000
,
NV
DEV
_SUBDEV_THERM
},
{
0x00020000
,
NV
DEV
_ENGINE_MSPDEC
},
{
0x00100000
,
NV
DEV
_SUBDEV_TIMER
},
{
0x00200000
,
NV
DEV
_SUBDEV_GPIO
},
/* PMGR->GPIO */
{
0x00200000
,
NV
DEV
_SUBDEV_I2C
},
/* PMGR->I2C/AUX */
{
0x01000000
,
NV
DEV
_SUBDEV_PMU
},
{
0x02000000
,
NV
DEV
_SUBDEV_LTC
},
{
0x08000000
,
NV
DEV
_SUBDEV_FB
},
{
0x10000000
,
NV
DEV
_SUBDEV_BUS
},
{
0x40000000
,
NV
DEV
_SUBDEV_IBUS
},
{
0x80000000
,
NV
DEV
_ENGINE_SW
},
{
0x04000000
,
NV
KM
_ENGINE_DISP
},
/* DISP first, so pageflip timestamps work. */
{
0x00000001
,
NV
KM
_ENGINE_MSPPP
},
{
0x00000020
,
NV
KM
_ENGINE_CE0
},
{
0x00000040
,
NV
KM
_ENGINE_CE1
},
{
0x00000080
,
NV
KM
_ENGINE_CE2
},
{
0x00000100
,
NV
KM
_ENGINE_FIFO
},
{
0x00001000
,
NV
KM
_ENGINE_GR
},
{
0x00002000
,
NV
KM
_SUBDEV_FB
},
{
0x00008000
,
NV
KM
_ENGINE_MSVLD
},
{
0x00040000
,
NV
KM
_SUBDEV_THERM
},
{
0x00020000
,
NV
KM
_ENGINE_MSPDEC
},
{
0x00100000
,
NV
KM
_SUBDEV_TIMER
},
{
0x00200000
,
NV
KM
_SUBDEV_GPIO
},
/* PMGR->GPIO */
{
0x00200000
,
NV
KM
_SUBDEV_I2C
},
/* PMGR->I2C/AUX */
{
0x01000000
,
NV
KM
_SUBDEV_PMU
},
{
0x02000000
,
NV
KM
_SUBDEV_LTC
},
{
0x08000000
,
NV
KM
_SUBDEV_FB
},
{
0x10000000
,
NV
KM
_SUBDEV_BUS
},
{
0x40000000
,
NV
KM
_SUBDEV_IBUS
},
{
0x80000000
,
NV
KM
_ENGINE_SW
},
{},
};
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c
View file @
68f3f702
...
...
@@ -25,16 +25,16 @@
const
struct
nvkm_mc_intr
nv04_mc_intr
[]
=
{
{
0x00000001
,
NV
DEV
_ENGINE_MPEG
},
/* NV17- MPEG/ME */
{
0x00000100
,
NV
DEV
_ENGINE_FIFO
},
{
0x00001000
,
NV
DEV
_ENGINE_GR
},
{
0x00010000
,
NV
DEV
_ENGINE_DISP
},
{
0x00020000
,
NV
DEV
_ENGINE_VP
},
/* NV40- */
{
0x00100000
,
NV
DEV
_SUBDEV_TIMER
},
{
0x01000000
,
NV
DEV
_ENGINE_DISP
},
/* NV04- PCRTC0 */
{
0x02000000
,
NV
DEV
_ENGINE_DISP
},
/* NV11- PCRTC1 */
{
0x10000000
,
NV
DEV
_SUBDEV_BUS
},
{
0x80000000
,
NV
DEV
_ENGINE_SW
},
{
0x00000001
,
NV
KM
_ENGINE_MPEG
},
/* NV17- MPEG/ME */
{
0x00000100
,
NV
KM
_ENGINE_FIFO
},
{
0x00001000
,
NV
KM
_ENGINE_GR
},
{
0x00010000
,
NV
KM
_ENGINE_DISP
},
{
0x00020000
,
NV
KM
_ENGINE_VP
},
/* NV40- */
{
0x00100000
,
NV
KM
_SUBDEV_TIMER
},
{
0x01000000
,
NV
KM
_ENGINE_DISP
},
/* NV04- PCRTC0 */
{
0x02000000
,
NV
KM
_ENGINE_DISP
},
/* NV11- PCRTC1 */
{
0x10000000
,
NV
KM
_SUBDEV_BUS
},
{
0x80000000
,
NV
KM
_ENGINE_SW
},
{}
};
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
View file @
68f3f702
...
...
@@ -25,19 +25,19 @@
const
struct
nvkm_mc_intr
nv50_mc_intr
[]
=
{
{
0x04000000
,
NV
DEV
_ENGINE_DISP
},
/* DISP before FIFO, so pageflip-timestamping works! */
{
0x00000001
,
NV
DEV
_ENGINE_MPEG
},
{
0x00000100
,
NV
DEV
_ENGINE_FIFO
},
{
0x00001000
,
NV
DEV
_ENGINE_GR
},
{
0x00004000
,
NV
DEV
_ENGINE_CIPHER
},
/* NV84- */
{
0x00008000
,
NV
DEV
_ENGINE_BSP
},
/* NV84- */
{
0x00020000
,
NV
DEV
_ENGINE_VP
},
/* NV84- */
{
0x00100000
,
NV
DEV
_SUBDEV_TIMER
},
{
0x00200000
,
NV
DEV
_SUBDEV_GPIO
},
/* PMGR->GPIO */
{
0x00200000
,
NV
DEV
_SUBDEV_I2C
},
/* PMGR->I2C/AUX */
{
0x10000000
,
NV
DEV
_SUBDEV_BUS
},
{
0x80000000
,
NV
DEV
_ENGINE_SW
},
{
0x0002d101
,
NV
DEV
_SUBDEV_FB
},
{
0x04000000
,
NV
KM
_ENGINE_DISP
},
/* DISP before FIFO, so pageflip-timestamping works! */
{
0x00000001
,
NV
KM
_ENGINE_MPEG
},
{
0x00000100
,
NV
KM
_ENGINE_FIFO
},
{
0x00001000
,
NV
KM
_ENGINE_GR
},
{
0x00004000
,
NV
KM
_ENGINE_CIPHER
},
/* NV84- */
{
0x00008000
,
NV
KM
_ENGINE_BSP
},
/* NV84- */
{
0x00020000
,
NV
KM
_ENGINE_VP
},
/* NV84- */
{
0x00100000
,
NV
KM
_SUBDEV_TIMER
},
{
0x00200000
,
NV
KM
_SUBDEV_GPIO
},
/* PMGR->GPIO */
{
0x00200000
,
NV
KM
_SUBDEV_I2C
},
/* PMGR->I2C/AUX */
{
0x10000000
,
NV
KM
_SUBDEV_BUS
},
{
0x80000000
,
NV
KM
_ENGINE_SW
},
{
0x0002d101
,
NV
KM
_SUBDEV_FB
},
{},
};
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c
View file @
68f3f702
...
...
@@ -167,7 +167,7 @@ gf100_vm_flush(struct nvkm_vm *vm)
u32
type
;
type
=
0x00000001
;
/* PAGE_ALL */
if
(
atomic_read
(
&
vm
->
engref
[
NV
DEV
_SUBDEV_BAR
]))
if
(
atomic_read
(
&
vm
->
engref
[
NV
KM
_SUBDEV_BAR
]))
type
|=
0x00000004
;
/* HUB_ONLY */
mutex_lock
(
&
mmu
->
subdev
.
mutex
);
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
View file @
68f3f702
...
...
@@ -161,29 +161,29 @@ nv50_vm_flush(struct nvkm_vm *vm)
int
i
,
vme
;
mutex_lock
(
&
subdev
->
mutex
);
for
(
i
=
0
;
i
<
NV
DEV
_SUBDEV_NR
;
i
++
)
{
for
(
i
=
0
;
i
<
NV
KM
_SUBDEV_NR
;
i
++
)
{
if
(
!
atomic_read
(
&
vm
->
engref
[
i
]))
continue
;
/* unfortunate hw bug workaround... */
if
(
i
==
NV
DEV
_ENGINE_GR
&&
device
->
gr
)
{
if
(
i
==
NV
KM
_ENGINE_GR
&&
device
->
gr
)
{
int
ret
=
nvkm_gr_tlb_flush
(
device
->
gr
);
if
(
ret
!=
-
ENODEV
)
continue
;
}
switch
(
i
)
{
case
NV
DEV
_ENGINE_GR
:
vme
=
0x00
;
break
;
case
NV
DEV
_ENGINE_VP
:
case
NV
DEV
_ENGINE_MSPDEC
:
vme
=
0x01
;
break
;
case
NV
DEV
_SUBDEV_BAR
:
vme
=
0x06
;
break
;
case
NV
DEV
_ENGINE_MSPPP
:
case
NV
DEV
_ENGINE_MPEG
:
vme
=
0x08
;
break
;
case
NV
DEV
_ENGINE_BSP
:
case
NV
DEV
_ENGINE_MSVLD
:
vme
=
0x09
;
break
;
case
NV
DEV
_ENGINE_CIPHER
:
case
NV
DEV
_ENGINE_SEC
:
vme
=
0x0a
;
break
;
case
NV
DEV
_ENGINE_CE0
:
vme
=
0x0d
;
break
;
case
NV
KM
_ENGINE_GR
:
vme
=
0x00
;
break
;
case
NV
KM
_ENGINE_VP
:
case
NV
KM
_ENGINE_MSPDEC
:
vme
=
0x01
;
break
;
case
NV
KM
_SUBDEV_BAR
:
vme
=
0x06
;
break
;
case
NV
KM
_ENGINE_MSPPP
:
case
NV
KM
_ENGINE_MPEG
:
vme
=
0x08
;
break
;
case
NV
KM
_ENGINE_BSP
:
case
NV
KM
_ENGINE_MSVLD
:
vme
=
0x09
;
break
;
case
NV
KM
_ENGINE_CIPHER
:
case
NV
KM
_ENGINE_SEC
:
vme
=
0x0a
;
break
;
case
NV
KM
_ENGINE_CE0
:
vme
=
0x0d
;
break
;
default:
continue
;
}
...
...
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