[ARM PATCH] 2262/1: Various IXP2000 typo fixes and comment cleanups

Patch from Deepak Saxena

Patch from Lennert Buytenhek

Signed-off-by: Lennert Buytenhek

Signed-off-by: Deepak Saxena
Signed-off-by: Russell King

Documentation/arm/IXP2000

@@ -18,7 +18,7 @@ http://developer.intel.com/design/network/products/npfamily/ixp2xxx.htm
 
 2. Linux Support
 
-Linux currently supports the following features on the IXP2000 NPUS:
+Linux currently supports the following features on the IXP2000 NPUs:
 
 - On-chip serial
 - PCI
@@ -30,10 +30,10 @@ That is about all we can support under Linux ATM b/c the core networking
 components of the chip are accessed via Intel's closed source SDK. 
 Please contact Intel directly on issues with using those. There is
 also a mailing list run by some folks at Princeton University that might
-be of helpful:  https://lists.cs.princeton.edu/mailman/listinfo/ixp2xxx
+be of help:  https://lists.cs.princeton.edu/mailman/listinfo/ixp2xxx
 
 WHATEVER YOU DO, DO NOT POST EMAIL TO THE LINUX-ARM OR LINUX-ARM-KERNEL
-MAILINNG LISTS REGARDING THE INTEL SDK.
+MAILING LISTS REGARDING THE INTEL SDK.
 
 3. Supported Platforms
 
@@ -47,12 +47,12 @@ MAILINNG LISTS REGARDING THE INTEL SDK.
 
 - The IXP2000 platforms ususally have rather complex PCI bus topologies
   with large memory space requirements. In addition, b/c of the way the
-  Intel SDK is designed, devices are enumerated in a vert specific
+  Intel SDK is designed, devices are enumerated in a very specific
   way. B/c of this this, we use "pci=firmware" option in the kernel
   command line so that we do not re-enumerate the bus.
 
 - IXDP2x01 systems have variable clock tick rates that we cannot determine 
-  via HW registers. The "ixdp2x01_clk=XXX" cmd line options allows you
+  via HW registers. The "ixdp2x01_clk=XXX" cmd line options allow you
   to pass the clock rate to the board port.
 
 5. Thanks

arch/arm/mach-ixp2000/ixdp2x00.c

@@ -194,7 +194,7 @@ void __init ixdp2x00_map_io(void)
  * Linux is a common design in telecom systems. The problem is that instead 
  * of all the devices being controlled by a single host, different
  * devices are controlles by different NPUs on the same bus, leading to
- * multiple hosts on the bus.i The exact bus layout looks like:
+ * multiple hosts on the bus. The exact bus layout looks like:
  *
  *                   Bus 0
  *    Master NPU <-------------------+-------------------> Slave NPU
@@ -210,9 +210,9 @@ void __init ixdp2x00_map_io(void)
  *             ... Dev    PMC       Media     Eth0   Eth1 ...
  *
  * The master controlls all but Eth1, which is controlled by the
- * slave. What this measn is that the both the master and the slave
+ * slave. What this means is that the both the master and the slave
  * have to scan the bus, but only one of them can enumerate the bus.
- * In addition, after the bus is scaned, each kernel must remove
+ * In addition, after the bus is scanned, each kernel must remove
  * the device(s) it does not control from the PCI dev list otherwise
  * a driver on each NPU will try to manage it and we will have horrible
  * conflicts. Oh..and the slave NPU needs to see the master NPU

include/asm-arm/arch-ixp2000/dma.h

 /*
- * linux/include/asm-arm/arch-ixdp2400/dma.h
+ * linux/include/asm-arm/arch-ixp2000/dma.h
  *
  * Copyright (C) 2002 Intel Corp.
  *

include/asm-arm/arch-ixp2000/io.h

@@ -24,7 +24,7 @@
 #define ___io(p)		((unsigned long)((p)+IXP2000_PCI_IO_VIRT_BASE))
 
 /*
- * IXP200 does not do proper byte-lane conversion for PCI addresses,
+ * IXP2000 does not do proper byte-lane conversion for PCI addresses,
  * so we need to override standard functions.
  */
 #define alignb(addr)		((addr & ~3) + (3 - (addr & 3)))

include/asm-arm/arch-ixp2000/irqs.h

@@ -46,13 +46,12 @@
 #define	IRQ_IXP2000_PCI   		15 /* PCI INTA or INTB */
 #define	IRQ_IXP2000_THDA0   		16 /* thread 0-31A */
 #define	IRQ_IXP2000_THDA1  		17 /* thread 32-63A */
-#define	IRQ_IXP2000_THDA2		18 /* thread 64-95A */
-#define	IRQ_IXP2000_THDA3 		19 /* thread 96-127A */
-#define	IRQ_IXP2000_THDB0		24 /* thread 0-31 B */
+#define	IRQ_IXP2000_THDA2		18 /* thread 64-95A, IXP2800 only */
+#define	IRQ_IXP2000_THDA3 		19 /* thread 96-127A, IXP2800 only */
+#define	IRQ_IXP2000_THDB0		24 /* thread 0-31B */
 #define	IRQ_IXP2000_THDB1		25 /* thread 32-63B */
-/* only 64 threads supported for IXP2400, rest or for IXP2800*/
-#define	IRQ_IXP2000_THDB2		26 /* thread 64-95B */
-#define	IRQ_IXP2000_THDB3		27 /* thread 96-127B */
+#define	IRQ_IXP2000_THDB2		26 /* thread 64-95B, IXP2800 only */
+#define	IRQ_IXP2000_THDB3		27 /* thread 96-127B, IXP2800 only */
 
 /* define generic GPIOs */
 #define IRQ_IXP2000_GPIO0		32

include/asm-arm/arch-ixp2000/ixdp2x00.h

@@ -53,7 +53,7 @@
 
 /*
  * PCI devfns for on-board devices. We need these to be able to
- * properly translte IRQs and for device removal.
+ * properly translate IRQs and for device removal.
  */
 #define	IXDP2400_SLAVE_ENET_DEVFN	0x18	/* Bus 1 */
 #define	IXDP2400_MASTER_ENET_DEVFN	0x20	/* Bus 1 */

include/asm-arm/arch-ixp2000/ixp2000-regs.h

@@ -115,7 +115,7 @@
 
 /*
  * Mask of valid IRQs in the 32-bit IRQ register. We use
- * this to mark certain IRQs as being in-valid.
+ * this to mark certain IRQs as being invalid.
  */
 #define	IXP2000_VALID_IRQ_MASK	0x0f0fffff
 
@@ -251,7 +251,7 @@
 #define	SLOWPORT_CCR_DIV_30		0x0f
 
 /*
- * PCR values.  PCR configure the mode of the interfac3
+ * PCR values.  PCR configure the mode of the interface.
  */
 #define	SLOWPORT_MODE_FLASH		0x00
 #define	SLOWPORT_MODE_LUCENT		0x01
@@ -260,7 +260,7 @@
 #define	SLOWPORT_MODE_MOTOROLA_UP	0x04
 
 /*
- * ADC values.  Defines data and address bus widths
+ * ADC values.  Defines data and address bus widths.
  */
 #define	SLOWPORT_ADDR_WIDTH_8		0x00
 #define	SLOWPORT_ADDR_WIDTH_16		0x01
@@ -272,7 +272,7 @@
 #define	SLOWPORT_DATA_WIDTH_32		0x30
 
 /*
- * Masks and shifts for various fields in the WTC and RTC registers
+ * Masks and shifts for various fields in the WTC and RTC registers.
  */
 #define	SLOWPORT_WRTC_MASK_HD		0x0003
 #define	SLOWPORT_WRTC_MASK_SU		0x003c
@@ -284,7 +284,7 @@
 
 
 /*
- * GPIO registers & GPIO interface
+ * GPIO registers & GPIO interface.
  */
 #define IXP2000_GPIO_REG(x)		((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x)))
 #define IXP2000_GPIO_PLR		IXP2000_GPIO_REG(0x00)

include/asm-arm/arch-ixp2000/platform.h

@@ -16,10 +16,10 @@
 #ifndef __ASSEMBLY__
 
 /*
- * The IXP2400 B0 silicon contains an errata that causes writes to 
- * on-chip I/O register to not complete fully. What this means is
+ * The IXP2400 B0 silicon contains an erratum (#66) that causes writes
+ * to on-chip I/O register to not complete fully. What this means is
  * that if you have a write to on-chip I/O followed by a back-to-back
- * read or write, the first write will happend twice. OR...if it's
+ * read or write, the first write will happen twice. OR...if it's
  * not a back-to-back trasaction, the read or write will generate 
  * incorrect data.
  *

include/asm-arm/arch-ixp2000/system.h

 /*
- * linux/include/asm-arm/arch-ixp2400/system.h
+ * linux/include/asm-arm/arch-ixp2000/system.h
  *
  * Copyright (C) 2002 Intel Corp.
  *