Commit 6a4d7a90 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt

Merge commit 'gcl/next' into next

parents edbc29d7 bdad0548
...@@ -235,7 +235,9 @@ image-$(CONFIG_PPC_ADDER875) += cuImage.adder875-uboot \ ...@@ -235,7 +235,9 @@ image-$(CONFIG_PPC_ADDER875) += cuImage.adder875-uboot \
dtbImage.adder875-redboot dtbImage.adder875-redboot
# Board ports in arch/powerpc/platform/52xx/Kconfig # Board ports in arch/powerpc/platform/52xx/Kconfig
image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200 cuImage.lite5200b image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200 lite5200.dtb
image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200b lite5200b.dtb
image-$(CONFIG_PPC_MEDIA5200) += cuImage.media5200 media5200.dtb
# Board ports in arch/powerpc/platform/82xx/Kconfig # Board ports in arch/powerpc/platform/82xx/Kconfig
image-$(CONFIG_MPC8272_ADS) += cuImage.mpc8272ads image-$(CONFIG_MPC8272_ADS) += cuImage.mpc8272ads
......
...@@ -17,6 +17,7 @@ / { ...@@ -17,6 +17,7 @@ / {
compatible = "schindler,cm5200"; compatible = "schindler,cm5200";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
...@@ -66,7 +67,6 @@ timer@600 { // General Purpose Timer ...@@ -66,7 +67,6 @@ timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x600 0x10>; reg = <0x600 0x10>;
interrupts = <1 9 0>; interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,has-wdt; fsl,has-wdt;
}; };
...@@ -74,84 +74,76 @@ timer@610 { // General Purpose Timer ...@@ -74,84 +74,76 @@ timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x610 0x10>; reg = <0x610 0x10>;
interrupts = <1 10 0>; interrupts = <1 10 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@620 { // General Purpose Timer timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x620 0x10>; reg = <0x620 0x10>;
interrupts = <1 11 0>; interrupts = <1 11 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@630 { // General Purpose Timer timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x630 0x10>; reg = <0x630 0x10>;
interrupts = <1 12 0>; interrupts = <1 12 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@640 { // General Purpose Timer timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x640 0x10>; reg = <0x640 0x10>;
interrupts = <1 13 0>; interrupts = <1 13 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@650 { // General Purpose Timer timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x650 0x10>; reg = <0x650 0x10>;
interrupts = <1 14 0>; interrupts = <1 14 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@660 { // General Purpose Timer timer@660 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x660 0x10>; reg = <0x660 0x10>;
interrupts = <1 15 0>; interrupts = <1 15 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@670 { // General Purpose Timer timer@670 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x670 0x10>; reg = <0x670 0x10>;
interrupts = <1 16 0>; interrupts = <1 16 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
rtc@800 { // Real time clock rtc@800 { // Real time clock
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
reg = <0x800 0x100>; reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>; interrupts = <1 5 0 1 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
gpio@b00 { gpio_simple: gpio@b00 {
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
reg = <0xb00 0x40>; reg = <0xb00 0x40>;
interrupts = <1 7 0>; interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>; gpio-controller;
#gpio-cells = <2>;
}; };
gpio@c00 { gpio_wkup: gpio@c00 {
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>; reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>; interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>; gpio-controller;
#gpio-cells = <2>;
}; };
spi@f00 { spi@f00 {
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
reg = <0xf00 0x20>; reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>; interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
usb@1000 { usb@1000 {
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>; reg = <0x1000 0xff>;
interrupts = <2 6 0>; interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
dma-controller@1200 { dma-controller@1200 {
...@@ -161,7 +153,6 @@ dma-controller@1200 { ...@@ -161,7 +153,6 @@ dma-controller@1200 {
3 4 0 3 5 0 3 6 0 3 7 0 3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0 3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>; 3 12 0 3 13 0 3 14 0 3 15 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
xlb@1f00 { xlb@1f00 {
...@@ -170,48 +161,34 @@ xlb@1f00 { ...@@ -170,48 +161,34 @@ xlb@1f00 {
}; };
serial@2000 { // PSC1 serial@2000 { // PSC1
device_type = "serial";
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
reg = <0x2000 0x100>; reg = <0x2000 0x100>;
interrupts = <2 1 0>; interrupts = <2 1 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
serial@2200 { // PSC2 serial@2200 { // PSC2
device_type = "serial"; compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
compatible = "fsl,mpc5200-psc-uart";
port-number = <1>; // Logical port assignment
reg = <0x2200 0x100>; reg = <0x2200 0x100>;
interrupts = <2 2 0>; interrupts = <2 2 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
serial@2400 { // PSC3 serial@2400 { // PSC3
device_type = "serial"; compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
compatible = "fsl,mpc5200-psc-uart";
port-number = <2>; // Logical port assignment
reg = <0x2400 0x100>; reg = <0x2400 0x100>;
interrupts = <2 3 0>; interrupts = <2 3 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
serial@2c00 { // PSC6 serial@2c00 { // PSC6
device_type = "serial";
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <5>; // Logical port assignment
reg = <0x2c00 0x100>; reg = <0x2c00 0x100>;
interrupts = <2 4 0>; interrupts = <2 4 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
ethernet@3000 { ethernet@3000 {
device_type = "network";
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
reg = <0x3000 0x400>; reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>; interrupts = <2 5 0>;
interrupt-parent = <&mpc5200_pic>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
}; };
...@@ -221,10 +198,8 @@ mdio@3000 { ...@@ -221,10 +198,8 @@ mdio@3000 {
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
device_type = "ethernet-phy";
reg = <0>; reg = <0>;
}; };
}; };
...@@ -235,7 +210,6 @@ i2c@3d40 { ...@@ -235,7 +210,6 @@ i2c@3d40 {
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>; reg = <0x3d40 0x40>;
interrupts = <2 16 0>; interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking; fsl5200-clocking;
}; };
...@@ -245,9 +219,8 @@ sram@8000 { ...@@ -245,9 +219,8 @@ sram@8000 {
}; };
}; };
lpb { localbus {
model = "fsl,lpb"; compatible = "fsl,mpc5200b-lpb","simple-bus";
compatible = "fsl,lpb";
#address-cells = <2>; #address-cells = <2>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0 0 0xfc000000 0x2000000>; ranges = <0 0 0xfc000000 0x2000000>;
......
/*
* Digsy MTC board Device Tree Source
*
* Copyright (C) 2009 Semihalf
*
* Based on the CM5200 by M. Balakowicz
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "intercontrol,digsy-mtc";
compatible = "intercontrol,digsy-mtc";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,5200@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <0x4000>; // L1, 16K
i-cache-size = <0x4000>; // L1, 16K
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x02000000>; // 32MB
};
soc5200@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc5200b-immr";
ranges = <0 0xf0000000 0x0000c000>;
reg = <0xf0000000 0x00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
cdm@200 {
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
reg = <0x200 0x38>;
};
mpc5200_pic: interrupt-controller@500 {
// 5200 interrupts are encoded into two levels;
interrupt-controller;
#interrupt-cells = <3>;
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
reg = <0x500 0x80>;
};
timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x600 0x10>;
interrupts = <1 9 0>;
fsl,has-wdt;
};
timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x610 0x10>;
interrupts = <1 10 0>;
};
timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x620 0x10>;
interrupts = <1 11 0>;
};
timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x630 0x10>;
interrupts = <1 12 0>;
};
timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x640 0x10>;
interrupts = <1 13 0>;
};
timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x650 0x10>;
interrupts = <1 14 0>;
};
timer@660 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x660 0x10>;
interrupts = <1 15 0>;
};
timer@670 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x670 0x10>;
interrupts = <1 16 0>;
};
gpio_simple: gpio@b00 {
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
reg = <0xb00 0x40>;
interrupts = <1 7 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpio_wkup: gpio@c00 {
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>;
gpio-controller;
#gpio-cells = <2>;
};
spi@f00 {
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>;
};
usb@1000 {
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>;
interrupts = <2 6 0>;
};
dma-controller@1200 {
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>;
};
xlb@1f00 {
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
reg = <0x1f00 0x100>;
};
serial@2400 { // PSC3
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
reg = <0x2400 0x100>;
interrupts = <2 3 0>;
};
serial@2600 { // PSC4
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
reg = <0x2600 0x100>;
interrupts = <2 11 0>;
};
ethernet@3000 {
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>;
phy-handle = <&phy0>;
};
mdio@3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
phy0: ethernet-phy@0 {
reg = <0>;
};
};
ata@3a00 {
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
reg = <0x3a00 0x100>;
interrupts = <2 7 0>;
};
i2c@3d00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
fsl5200-clocking;
rtc@50 {
compatible = "at,24c08";
reg = <0x50>;
};
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
sram@8000 {
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
reg = <0x8000 0x4000>;
};
};
lpb {
compatible = "fsl,mpc5200b-lpb","simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0xff000000 0x1000000>;
// 16-bit flash device at LocalPlus Bus CS0
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x1000000>;
bank-width = <2>;
device-width = <2>;
#size-cells = <1>;
#address-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x0 0x00200000>;
};
partition@200000 {
label = "root";
reg = <0x00200000 0x00300000>;
};
partition@500000 {
label = "user";
reg = <0x00500000 0x00a00000>;
};
partition@f00000 {
label = "u-boot";
reg = <0x00f00000 0x100000>;
};
};
};
};
...@@ -17,6 +17,7 @@ / { ...@@ -17,6 +17,7 @@ / {
compatible = "fsl,lite5200"; compatible = "fsl,lite5200";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
...@@ -58,96 +59,74 @@ mpc5200_pic: interrupt-controller@500 { ...@@ -58,96 +59,74 @@ mpc5200_pic: interrupt-controller@500 {
// 5200 interrupts are encoded into two levels; // 5200 interrupts are encoded into two levels;
interrupt-controller; interrupt-controller;
#interrupt-cells = <3>; #interrupt-cells = <3>;
device_type = "interrupt-controller";
compatible = "fsl,mpc5200-pic"; compatible = "fsl,mpc5200-pic";
reg = <0x500 0x80>; reg = <0x500 0x80>;
}; };
timer@600 { // General Purpose Timer timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt"; compatible = "fsl,mpc5200-gpt";
cell-index = <0>;
reg = <0x600 0x10>; reg = <0x600 0x10>;
interrupts = <1 9 0>; interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,has-wdt; fsl,has-wdt;
}; };
timer@610 { // General Purpose Timer timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt"; compatible = "fsl,mpc5200-gpt";
cell-index = <1>;
reg = <0x610 0x10>; reg = <0x610 0x10>;
interrupts = <1 10 0>; interrupts = <1 10 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@620 { // General Purpose Timer timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt"; compatible = "fsl,mpc5200-gpt";
cell-index = <2>;
reg = <0x620 0x10>; reg = <0x620 0x10>;
interrupts = <1 11 0>; interrupts = <1 11 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@630 { // General Purpose Timer timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt"; compatible = "fsl,mpc5200-gpt";
cell-index = <3>;
reg = <0x630 0x10>; reg = <0x630 0x10>;
interrupts = <1 12 0>; interrupts = <1 12 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@640 { // General Purpose Timer timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt"; compatible = "fsl,mpc5200-gpt";
cell-index = <4>;
reg = <0x640 0x10>; reg = <0x640 0x10>;
interrupts = <1 13 0>; interrupts = <1 13 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@650 { // General Purpose Timer timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt"; compatible = "fsl,mpc5200-gpt";
cell-index = <5>;
reg = <0x650 0x10>; reg = <0x650 0x10>;
interrupts = <1 14 0>; interrupts = <1 14 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@660 { // General Purpose Timer timer@660 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt"; compatible = "fsl,mpc5200-gpt";
cell-index = <6>;
reg = <0x660 0x10>; reg = <0x660 0x10>;
interrupts = <1 15 0>; interrupts = <1 15 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@670 { // General Purpose Timer timer@670 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt"; compatible = "fsl,mpc5200-gpt";
cell-index = <7>;
reg = <0x670 0x10>; reg = <0x670 0x10>;
interrupts = <1 16 0>; interrupts = <1 16 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
rtc@800 { // Real time clock rtc@800 { // Real time clock
compatible = "fsl,mpc5200-rtc"; compatible = "fsl,mpc5200-rtc";
reg = <0x800 0x100>; reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>; interrupts = <1 5 0 1 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
can@900 { can@900 {
compatible = "fsl,mpc5200-mscan"; compatible = "fsl,mpc5200-mscan";
cell-index = <0>;
interrupts = <2 17 0>; interrupts = <2 17 0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x900 0x80>; reg = <0x900 0x80>;
}; };
can@980 { can@980 {
compatible = "fsl,mpc5200-mscan"; compatible = "fsl,mpc5200-mscan";
cell-index = <1>;
interrupts = <2 18 0>; interrupts = <2 18 0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x980 0x80>; reg = <0x980 0x80>;
}; };
...@@ -155,39 +134,33 @@ gpio@b00 { ...@@ -155,39 +134,33 @@ gpio@b00 {
compatible = "fsl,mpc5200-gpio"; compatible = "fsl,mpc5200-gpio";
reg = <0xb00 0x40>; reg = <0xb00 0x40>;
interrupts = <1 7 0>; interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
gpio@c00 { gpio@c00 {
compatible = "fsl,mpc5200-gpio-wkup"; compatible = "fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>; reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>; interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
spi@f00 { spi@f00 {
compatible = "fsl,mpc5200-spi"; compatible = "fsl,mpc5200-spi";
reg = <0xf00 0x20>; reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>; interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
usb@1000 { usb@1000 {
compatible = "fsl,mpc5200-ohci","ohci-be"; compatible = "fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>; reg = <0x1000 0xff>;
interrupts = <2 6 0>; interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
dma-controller@1200 { dma-controller@1200 {
device_type = "dma-controller";
compatible = "fsl,mpc5200-bestcomm"; compatible = "fsl,mpc5200-bestcomm";
reg = <0x1200 0x80>; reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0 3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0 3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>; 3 12 0 3 13 0 3 14 0 3 15 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
xlb@1f00 { xlb@1f00 {
...@@ -196,13 +169,10 @@ xlb@1f00 { ...@@ -196,13 +169,10 @@ xlb@1f00 {
}; };
serial@2000 { // PSC1 serial@2000 { // PSC1
device_type = "serial";
compatible = "fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
cell-index = <0>; cell-index = <0>;
reg = <0x2000 0x100>; reg = <0x2000 0x100>;
interrupts = <2 1 0>; interrupts = <2 1 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
// PSC2 in ac97 mode example // PSC2 in ac97 mode example
...@@ -211,7 +181,6 @@ serial@2000 { // PSC1 ...@@ -211,7 +181,6 @@ serial@2000 { // PSC1
// cell-index = <1>; // cell-index = <1>;
// reg = <0x2200 0x100>; // reg = <0x2200 0x100>;
// interrupts = <2 2 0>; // interrupts = <2 2 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
// PSC3 in CODEC mode example // PSC3 in CODEC mode example
...@@ -220,27 +189,22 @@ serial@2000 { // PSC1 ...@@ -220,27 +189,22 @@ serial@2000 { // PSC1
// cell-index = <2>; // cell-index = <2>;
// reg = <0x2400 0x100>; // reg = <0x2400 0x100>;
// interrupts = <2 3 0>; // interrupts = <2 3 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
// PSC4 in uart mode example // PSC4 in uart mode example
//serial@2600 { // PSC4 //serial@2600 { // PSC4
// device_type = "serial";
// compatible = "fsl,mpc5200-psc-uart"; // compatible = "fsl,mpc5200-psc-uart";
// cell-index = <3>; // cell-index = <3>;
// reg = <0x2600 0x100>; // reg = <0x2600 0x100>;
// interrupts = <2 11 0>; // interrupts = <2 11 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
// PSC5 in uart mode example // PSC5 in uart mode example
//serial@2800 { // PSC5 //serial@2800 { // PSC5
// device_type = "serial";
// compatible = "fsl,mpc5200-psc-uart"; // compatible = "fsl,mpc5200-psc-uart";
// cell-index = <4>; // cell-index = <4>;
// reg = <0x2800 0x100>; // reg = <0x2800 0x100>;
// interrupts = <2 12 0>; // interrupts = <2 12 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
// PSC6 in spi mode example // PSC6 in spi mode example
...@@ -249,16 +213,13 @@ serial@2000 { // PSC1 ...@@ -249,16 +213,13 @@ serial@2000 { // PSC1
// cell-index = <5>; // cell-index = <5>;
// reg = <0x2c00 0x100>; // reg = <0x2c00 0x100>;
// interrupts = <2 4 0>; // interrupts = <2 4 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
ethernet@3000 { ethernet@3000 {
device_type = "network";
compatible = "fsl,mpc5200-fec"; compatible = "fsl,mpc5200-fec";
reg = <0x3000 0x400>; reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>; interrupts = <2 5 0>;
interrupt-parent = <&mpc5200_pic>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
}; };
...@@ -268,30 +229,24 @@ mdio@3000 { ...@@ -268,30 +229,24 @@ mdio@3000 {
compatible = "fsl,mpc5200-mdio"; compatible = "fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
phy0: ethernet-phy@1 { phy0: ethernet-phy@1 {
device_type = "ethernet-phy";
reg = <1>; reg = <1>;
}; };
}; };
ata@3a00 { ata@3a00 {
device_type = "ata";
compatible = "fsl,mpc5200-ata"; compatible = "fsl,mpc5200-ata";
reg = <0x3a00 0x100>; reg = <0x3a00 0x100>;
interrupts = <2 7 0>; interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
i2c@3d00 { i2c@3d00 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,mpc5200-i2c","fsl-i2c"; compatible = "fsl,mpc5200-i2c","fsl-i2c";
cell-index = <0>;
reg = <0x3d00 0x40>; reg = <0x3d00 0x40>;
interrupts = <2 15 0>; interrupts = <2 15 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking; fsl5200-clocking;
}; };
...@@ -299,14 +254,12 @@ i2c@3d40 { ...@@ -299,14 +254,12 @@ i2c@3d40 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,mpc5200-i2c","fsl-i2c"; compatible = "fsl,mpc5200-i2c","fsl-i2c";
cell-index = <1>;
reg = <0x3d40 0x40>; reg = <0x3d40 0x40>;
interrupts = <2 16 0>; interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking; fsl5200-clocking;
}; };
sram@8000 { sram@8000 {
compatible = "fsl,mpc5200-sram","sram"; compatible = "fsl,mpc5200-sram";
reg = <0x8000 0x4000>; reg = <0x8000 0x4000>;
}; };
}; };
...@@ -325,7 +278,6 @@ pci@f0000d00 { ...@@ -325,7 +278,6 @@ pci@f0000d00 {
0xc000 0 0 4 &mpc5200_pic 0 0 3>; 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 10 0>; interrupts = <2 8 0 2 9 0 2 10 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>; bus-range = <0 0>;
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
......
...@@ -17,6 +17,7 @@ / { ...@@ -17,6 +17,7 @@ / {
compatible = "fsl,lite5200b"; compatible = "fsl,lite5200b";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
...@@ -58,136 +59,112 @@ mpc5200_pic: interrupt-controller@500 { ...@@ -58,136 +59,112 @@ mpc5200_pic: interrupt-controller@500 {
// 5200 interrupts are encoded into two levels; // 5200 interrupts are encoded into two levels;
interrupt-controller; interrupt-controller;
#interrupt-cells = <3>; #interrupt-cells = <3>;
device_type = "interrupt-controller";
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
reg = <0x500 0x80>; reg = <0x500 0x80>;
}; };
timer@600 { // General Purpose Timer timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <0>;
reg = <0x600 0x10>; reg = <0x600 0x10>;
interrupts = <1 9 0>; interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,has-wdt; fsl,has-wdt;
}; };
timer@610 { // General Purpose Timer timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <1>;
reg = <0x610 0x10>; reg = <0x610 0x10>;
interrupts = <1 10 0>; interrupts = <1 10 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@620 { // General Purpose Timer timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <2>;
reg = <0x620 0x10>; reg = <0x620 0x10>;
interrupts = <1 11 0>; interrupts = <1 11 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@630 { // General Purpose Timer timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <3>;
reg = <0x630 0x10>; reg = <0x630 0x10>;
interrupts = <1 12 0>; interrupts = <1 12 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@640 { // General Purpose Timer timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <4>;
reg = <0x640 0x10>; reg = <0x640 0x10>;
interrupts = <1 13 0>; interrupts = <1 13 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@650 { // General Purpose Timer timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <5>;
reg = <0x650 0x10>; reg = <0x650 0x10>;
interrupts = <1 14 0>; interrupts = <1 14 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@660 { // General Purpose Timer timer@660 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <6>;
reg = <0x660 0x10>; reg = <0x660 0x10>;
interrupts = <1 15 0>; interrupts = <1 15 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@670 { // General Purpose Timer timer@670 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <7>;
reg = <0x670 0x10>; reg = <0x670 0x10>;
interrupts = <1 16 0>; interrupts = <1 16 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
rtc@800 { // Real time clock rtc@800 { // Real time clock
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
reg = <0x800 0x100>; reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>; interrupts = <1 5 0 1 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
can@900 { can@900 {
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
cell-index = <0>;
interrupts = <2 17 0>; interrupts = <2 17 0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x900 0x80>; reg = <0x900 0x80>;
}; };
can@980 { can@980 {
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
cell-index = <1>;
interrupts = <2 18 0>; interrupts = <2 18 0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x980 0x80>; reg = <0x980 0x80>;
}; };
gpio@b00 { gpio_simple: gpio@b00 {
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
reg = <0xb00 0x40>; reg = <0xb00 0x40>;
interrupts = <1 7 0>; interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>; gpio-controller;
#gpio-cells = <2>;
}; };
gpio@c00 { gpio_wkup: gpio@c00 {
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>; reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>; interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>; gpio-controller;
#gpio-cells = <2>;
}; };
spi@f00 { spi@f00 {
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
reg = <0xf00 0x20>; reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>; interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
usb@1000 { usb@1000 {
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>; reg = <0x1000 0xff>;
interrupts = <2 6 0>; interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
dma-controller@1200 { dma-controller@1200 {
device_type = "dma-controller";
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
reg = <0x1200 0x80>; reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0 3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0 3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>; 3 12 0 3 13 0 3 14 0 3 15 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
xlb@1f00 { xlb@1f00 {
...@@ -196,13 +173,10 @@ xlb@1f00 { ...@@ -196,13 +173,10 @@ xlb@1f00 {
}; };
serial@2000 { // PSC1 serial@2000 { // PSC1
device_type = "serial";
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
cell-index = <0>; cell-index = <0>;
reg = <0x2000 0x100>; reg = <0x2000 0x100>;
interrupts = <2 1 0>; interrupts = <2 1 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
// PSC2 in ac97 mode example // PSC2 in ac97 mode example
...@@ -211,7 +185,6 @@ serial@2000 { // PSC1 ...@@ -211,7 +185,6 @@ serial@2000 { // PSC1
// cell-index = <1>; // cell-index = <1>;
// reg = <0x2200 0x100>; // reg = <0x2200 0x100>;
// interrupts = <2 2 0>; // interrupts = <2 2 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
// PSC3 in CODEC mode example // PSC3 in CODEC mode example
...@@ -220,27 +193,22 @@ serial@2000 { // PSC1 ...@@ -220,27 +193,22 @@ serial@2000 { // PSC1
// cell-index = <2>; // cell-index = <2>;
// reg = <0x2400 0x100>; // reg = <0x2400 0x100>;
// interrupts = <2 3 0>; // interrupts = <2 3 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
// PSC4 in uart mode example // PSC4 in uart mode example
//serial@2600 { // PSC4 //serial@2600 { // PSC4
// device_type = "serial";
// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
// cell-index = <3>; // cell-index = <3>;
// reg = <0x2600 0x100>; // reg = <0x2600 0x100>;
// interrupts = <2 11 0>; // interrupts = <2 11 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
// PSC5 in uart mode example // PSC5 in uart mode example
//serial@2800 { // PSC5 //serial@2800 { // PSC5
// device_type = "serial";
// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
// cell-index = <4>; // cell-index = <4>;
// reg = <0x2800 0x100>; // reg = <0x2800 0x100>;
// interrupts = <2 12 0>; // interrupts = <2 12 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
// PSC6 in spi mode example // PSC6 in spi mode example
...@@ -249,49 +217,40 @@ serial@2000 { // PSC1 ...@@ -249,49 +217,40 @@ serial@2000 { // PSC1
// cell-index = <5>; // cell-index = <5>;
// reg = <0x2c00 0x100>; // reg = <0x2c00 0x100>;
// interrupts = <2 4 0>; // interrupts = <2 4 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
ethernet@3000 { ethernet@3000 {
device_type = "network";
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
reg = <0x3000 0x400>; reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>; interrupts = <2 5 0>;
interrupt-parent = <&mpc5200_pic>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
}; };
mdio@3000 { mdio@3000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio"; compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
device_type = "ethernet-phy";
reg = <0>; reg = <0>;
}; };
}; };
ata@3a00 { ata@3a00 {
device_type = "ata";
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
reg = <0x3a00 0x100>; reg = <0x3a00 0x100>;
interrupts = <2 7 0>; interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
i2c@3d00 { i2c@3d00 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
cell-index = <0>;
reg = <0x3d00 0x40>; reg = <0x3d00 0x40>;
interrupts = <2 15 0>; interrupts = <2 15 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking; fsl5200-clocking;
}; };
...@@ -299,14 +258,13 @@ i2c@3d40 { ...@@ -299,14 +258,13 @@ i2c@3d40 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
cell-index = <1>;
reg = <0x3d40 0x40>; reg = <0x3d40 0x40>;
interrupts = <2 16 0>; interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking; fsl5200-clocking;
}; };
sram@8000 { sram@8000 {
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram"; compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
reg = <0x8000 0x4000>; reg = <0x8000 0x4000>;
}; };
}; };
...@@ -330,7 +288,6 @@ pci@f0000d00 { ...@@ -330,7 +288,6 @@ pci@f0000d00 {
0xc800 0 0 4 &mpc5200_pic 0 0 3>; 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 10 0>; interrupts = <2 8 0 2 9 0 2 10 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>; bus-range = <0 0>;
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
......
/*
* Freescale Media5200 board Device Tree Source
*
* Copyright 2009 Secret Lab Technologies Ltd.
* Grant Likely <grant.likely@secretlab.ca>
* Steven Cavanagh <scavanagh@secretlab.ca>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "fsl,media5200";
compatible = "fsl,media5200";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
aliases {
console = &console;
ethernet0 = &eth0;
};
chosen {
linux,stdout-path = &console;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,5200@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <0x4000>; // L1, 16K
i-cache-size = <0x4000>; // L1, 16K
timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
bus-frequency = <132000000>; // 132 MHz
clock-frequency = <396000000>; // 396 MHz
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>; // 128MB RAM
};
soc@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc5200b-immr";
ranges = <0 0xf0000000 0x0000c000>;
reg = <0xf0000000 0x00000100>;
bus-frequency = <132000000>;// 132 MHz
system-frequency = <0>; // from bootloader
cdm@200 {
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
reg = <0x200 0x38>;
};
mpc5200_pic: interrupt-controller@500 {
// 5200 interrupts are encoded into two levels;
interrupt-controller;
#interrupt-cells = <3>;
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
reg = <0x500 0x80>;
};
timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x600 0x10>;
interrupts = <1 9 0>;
fsl,has-wdt;
};
timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x610 0x10>;
interrupts = <1 10 0>;
};
timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x620 0x10>;
interrupts = <1 11 0>;
};
timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x630 0x10>;
interrupts = <1 12 0>;
};
timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x640 0x10>;
interrupts = <1 13 0>;
};
timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x650 0x10>;
interrupts = <1 14 0>;
};
timer@660 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x660 0x10>;
interrupts = <1 15 0>;
};
timer@670 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x670 0x10>;
interrupts = <1 16 0>;
};
rtc@800 { // Real time clock
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>;
};
can@900 {
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
interrupts = <2 17 0>;
reg = <0x900 0x80>;
};
can@980 {
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
interrupts = <2 18 0>;
reg = <0x980 0x80>;
};
gpio_simple: gpio@b00 {
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
reg = <0xb00 0x40>;
interrupts = <1 7 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpio_wkup: gpio@c00 {
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>;
gpio-controller;
#gpio-cells = <2>;
};
spi@f00 {
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>;
};
usb@1000 {
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0x100>;
interrupts = <2 6 0>;
};
dma-controller@1200 {
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>;
};
xlb@1f00 {
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
reg = <0x1f00 0x100>;
};
// PSC6 in uart mode
console: serial@2c00 { // PSC6
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
cell-index = <5>;
port-number = <0>; // Logical port assignment
reg = <0x2c00 0x100>;
interrupts = <2 4 0>;
};
eth0: ethernet@3000 {
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>;
phy-handle = <&phy0>;
};
mdio@3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
phy0: ethernet-phy@0 {
reg = <0>;
};
};
ata@3a00 {
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
reg = <0x3a00 0x100>;
interrupts = <2 7 0>;
};
i2c@3d00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
fsl5200-clocking;
};
i2c@3d40 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
fsl5200-clocking;
};
sram@8000 {
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
reg = <0x8000 0x4000>;
};
};
pci@f0000d00 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
reg = <0xf0000d00 0x100>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
0xc000 0 0 2 &media5200_fpga 0 3
0xc000 0 0 3 &media5200_fpga 0 4
0xc000 0 0 4 &media5200_fpga 0 5
0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot
0xc800 0 0 2 &media5200_fpga 0 4
0xc800 0 0 3 &media5200_fpga 0 5
0xc800 0 0 4 &media5200_fpga 0 2
0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI
0xd000 0 0 2 &media5200_fpga 0 5
0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
>;
clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 10 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>;
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
};
localbus {
compatible = "fsl,mpc5200b-lpb","simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = < 0 0 0xfc000000 0x02000000
1 0 0xfe000000 0x02000000
2 0 0xf0010000 0x00010000
3 0 0xf0020000 0x00010000 >;
flash@0,0 {
compatible = "amd,am29lv28ml", "cfi-flash";
reg = <0 0x0 0x2000000>; // 32 MB
bank-width = <4>; // Width in bytes of the flash bank
device-width = <2>; // Two devices on each bank
};
flash@1,0 {
compatible = "amd,am29lv28ml", "cfi-flash";
reg = <1 0 0x2000000>; // 32 MB
bank-width = <4>; // Width in bytes of the flash bank
device-width = <2>; // Two devices on each bank
};
media5200_fpga: fpga@2,0 {
compatible = "fsl,media5200-fpga";
interrupt-controller;
#interrupt-cells = <2>; // 0:bank 1:id; no type field
reg = <2 0 0x10000>;
interrupt-parent = <&mpc5200_pic>;
interrupts = <0 0 3 // IRQ bank 0
1 1 3>; // IRQ bank 1
};
uart@3,0 {
compatible = "ti,tl16c752bpt";
reg = <3 0 0x10000>;
interrupt-parent = <&media5200_fpga>;
interrupts = <0 0 0 1>; // 2 irqs
};
};
};
...@@ -17,6 +17,7 @@ / { ...@@ -17,6 +17,7 @@ / {
compatible = "promess,motionpro"; compatible = "promess,motionpro";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
...@@ -66,7 +67,6 @@ timer@600 { // General Purpose Timer ...@@ -66,7 +67,6 @@ timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x600 0x10>; reg = <0x600 0x10>;
interrupts = <1 9 0>; interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,has-wdt; fsl,has-wdt;
}; };
...@@ -74,35 +74,30 @@ timer@610 { // General Purpose Timer ...@@ -74,35 +74,30 @@ timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x610 0x10>; reg = <0x610 0x10>;
interrupts = <1 10 0>; interrupts = <1 10 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@620 { // General Purpose Timer timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x620 0x10>; reg = <0x620 0x10>;
interrupts = <1 11 0>; interrupts = <1 11 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@630 { // General Purpose Timer timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x630 0x10>; reg = <0x630 0x10>;
interrupts = <1 12 0>; interrupts = <1 12 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@640 { // General Purpose Timer timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x640 0x10>; reg = <0x640 0x10>;
interrupts = <1 13 0>; interrupts = <1 13 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@650 { // General Purpose Timer timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x650 0x10>; reg = <0x650 0x10>;
interrupts = <1 14 0>; interrupts = <1 14 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
motionpro-led@660 { // Motion-PRO status LED motionpro-led@660 { // Motion-PRO status LED
...@@ -110,7 +105,6 @@ motionpro-led@660 { // Motion-PRO status LED ...@@ -110,7 +105,6 @@ motionpro-led@660 { // Motion-PRO status LED
label = "motionpro-statusled"; label = "motionpro-statusled";
reg = <0x660 0x10>; reg = <0x660 0x10>;
interrupts = <1 15 0>; interrupts = <1 15 0>;
interrupt-parent = <&mpc5200_pic>;
blink-delay = <100>; // 100 msec blink-delay = <100>; // 100 msec
}; };
...@@ -119,49 +113,46 @@ motionpro-led@670 { // Motion-PRO ready LED ...@@ -119,49 +113,46 @@ motionpro-led@670 { // Motion-PRO ready LED
label = "motionpro-readyled"; label = "motionpro-readyled";
reg = <0x670 0x10>; reg = <0x670 0x10>;
interrupts = <1 16 0>; interrupts = <1 16 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
rtc@800 { // Real time clock rtc@800 { // Real time clock
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
reg = <0x800 0x100>; reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>; interrupts = <1 5 0 1 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
can@980 { can@980 {
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
interrupts = <2 18 0>; interrupts = <2 18 0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x980 0x80>; reg = <0x980 0x80>;
}; };
gpio@b00 { gpio_simple: gpio@b00 {
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
reg = <0xb00 0x40>; reg = <0xb00 0x40>;
interrupts = <1 7 0>; interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>; gpio-controller;
#gpio-cells = <2>;
}; };
gpio@c00 { gpio_wkup: gpio@c00 {
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>; reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>; interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>; gpio-controller;
#gpio-cells = <2>;
}; };
spi@f00 { spi@f00 {
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
reg = <0xf00 0x20>; reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>; interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
usb@1000 { usb@1000 {
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>; reg = <0x1000 0xff>;
interrupts = <2 6 0>; interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
dma-controller@1200 { dma-controller@1200 {
...@@ -171,7 +162,6 @@ dma-controller@1200 { ...@@ -171,7 +162,6 @@ dma-controller@1200 {
3 4 0 3 5 0 3 6 0 3 7 0 3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0 3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>; 3 12 0 3 13 0 3 14 0 3 15 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
xlb@1f00 { xlb@1f00 {
...@@ -180,12 +170,9 @@ xlb@1f00 { ...@@ -180,12 +170,9 @@ xlb@1f00 {
}; };
serial@2000 { // PSC1 serial@2000 { // PSC1
device_type = "serial";
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
reg = <0x2000 0x100>; reg = <0x2000 0x100>;
interrupts = <2 1 0>; interrupts = <2 1 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
// PSC2 in spi master mode // PSC2 in spi master mode
...@@ -194,26 +181,20 @@ spi@2200 { // PSC2 ...@@ -194,26 +181,20 @@ spi@2200 { // PSC2
cell-index = <1>; cell-index = <1>;
reg = <0x2200 0x100>; reg = <0x2200 0x100>;
interrupts = <2 2 0>; interrupts = <2 2 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
// PSC5 in uart mode // PSC5 in uart mode
serial@2800 { // PSC5 serial@2800 { // PSC5
device_type = "serial";
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <4>; // Logical port assignment
reg = <0x2800 0x100>; reg = <0x2800 0x100>;
interrupts = <2 12 0>; interrupts = <2 12 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
ethernet@3000 { ethernet@3000 {
device_type = "network";
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
reg = <0x3000 0x400>; reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>; interrupts = <2 5 0>;
interrupt-parent = <&mpc5200_pic>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
}; };
...@@ -223,10 +204,8 @@ mdio@3000 { ...@@ -223,10 +204,8 @@ mdio@3000 {
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
phy0: ethernet-phy@2 { phy0: ethernet-phy@2 {
device_type = "ethernet-phy";
reg = <2>; reg = <2>;
}; };
}; };
...@@ -235,7 +214,6 @@ ata@3a00 { ...@@ -235,7 +214,6 @@ ata@3a00 {
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
reg = <0x3a00 0x100>; reg = <0x3a00 0x100>;
interrupts = <2 7 0>; interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
i2c@3d40 { i2c@3d40 {
...@@ -244,7 +222,6 @@ i2c@3d40 { ...@@ -244,7 +222,6 @@ i2c@3d40 {
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>; reg = <0x3d40 0x40>;
interrupts = <2 16 0>; interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking; fsl5200-clocking;
rtc@68 { rtc@68 {
...@@ -259,8 +236,8 @@ sram@8000 { ...@@ -259,8 +236,8 @@ sram@8000 {
}; };
}; };
lpb { localbus {
compatible = "fsl,lpb"; compatible = "fsl,mpc5200b-lpb","simple-bus";
#address-cells = <2>; #address-cells = <2>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0 0 0xff000000 0x01000000 ranges = <0 0 0xff000000 0x01000000
...@@ -273,7 +250,6 @@ kollmorgen@1,0 { ...@@ -273,7 +250,6 @@ kollmorgen@1,0 {
compatible = "promess,motionpro-kollmorgen"; compatible = "promess,motionpro-kollmorgen";
reg = <1 0 0x10000>; reg = <1 0 0x10000>;
interrupts = <1 1 0>; interrupts = <1 1 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
// 8-bit board CPLD on LocalPlus Bus CS2 // 8-bit board CPLD on LocalPlus Bus CS2
......
...@@ -19,6 +19,7 @@ / { ...@@ -19,6 +19,7 @@ / {
compatible = "phytec,pcm030"; compatible = "phytec,pcm030";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
...@@ -29,26 +30,26 @@ PowerPC,5200@0 { ...@@ -29,26 +30,26 @@ PowerPC,5200@0 {
reg = <0>; reg = <0>;
d-cache-line-size = <32>; d-cache-line-size = <32>;
i-cache-line-size = <32>; i-cache-line-size = <32>;
d-cache-size = <0x4000>; /* L1, 16K */ d-cache-size = <0x4000>; // L1, 16K
i-cache-size = <0x4000>; /* L1, 16K */ i-cache-size = <0x4000>; // L1, 16K
timebase-frequency = <0>; /* From Bootloader */ timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; /* From Bootloader */ bus-frequency = <0>; // from bootloader
clock-frequency = <0>; /* From Bootloader */ clock-frequency = <0>; // from bootloader
}; };
}; };
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <0x00000000 0x04000000>; /* 64MB */ reg = <0x00000000 0x04000000>; // 64MB
}; };
soc5200@f0000000 { soc5200@f0000000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "fsl,mpc5200b-immr"; compatible = "fsl,mpc5200b-immr";
ranges = <0x0 0xf0000000 0x0000c000>; ranges = <0 0xf0000000 0x0000c000>;
bus-frequency = <0>; /* From bootloader */ bus-frequency = <0>; // from bootloader
system-frequency = <0>; /* From bootloader */ system-frequency = <0>; // from bootloader
cdm@200 { cdm@200 {
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
...@@ -56,87 +57,70 @@ cdm@200 { ...@@ -56,87 +57,70 @@ cdm@200 {
}; };
mpc5200_pic: interrupt-controller@500 { mpc5200_pic: interrupt-controller@500 {
/* 5200 interrupts are encoded into two levels; */ // 5200 interrupts are encoded into two levels;
interrupt-controller; interrupt-controller;
#interrupt-cells = <3>; #interrupt-cells = <3>;
device_type = "interrupt-controller";
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
reg = <0x500 0x80>; reg = <0x500 0x80>;
}; };
timer@600 { /* General Purpose Timer */ timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <0>;
reg = <0x600 0x10>; reg = <0x600 0x10>;
interrupts = <0x1 0x9 0x0>; interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,has-wdt; fsl,has-wdt;
}; };
timer@610 { /* General Purpose Timer */ timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <1>;
reg = <0x610 0x10>; reg = <0x610 0x10>;
interrupts = <0x1 0xa 0x0>; interrupts = <1 10 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
gpt2: timer@620 { /* General Purpose Timer in GPIO mode */ gpt2: timer@620 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
cell-index = <2>;
reg = <0x620 0x10>; reg = <0x620 0x10>;
interrupts = <0x1 0xb 0x0>; interrupts = <1 11 0>;
interrupt-parent = <&mpc5200_pic>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
gpt3: timer@630 { /* General Purpose Timer in GPIO mode */ gpt3: timer@630 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
cell-index = <3>;
reg = <0x630 0x10>; reg = <0x630 0x10>;
interrupts = <0x1 0xc 0x0>; interrupts = <1 12 0>;
interrupt-parent = <&mpc5200_pic>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
gpt4: timer@640 { /* General Purpose Timer in GPIO mode */ gpt4: timer@640 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
cell-index = <4>;
reg = <0x640 0x10>; reg = <0x640 0x10>;
interrupts = <0x1 0xd 0x0>; interrupts = <1 13 0>;
interrupt-parent = <&mpc5200_pic>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
gpt5: timer@650 { /* General Purpose Timer in GPIO mode */ gpt5: timer@650 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
cell-index = <5>;
reg = <0x650 0x10>; reg = <0x650 0x10>;
interrupts = <0x1 0xe 0x0>; interrupts = <1 14 0>;
interrupt-parent = <&mpc5200_pic>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
gpt6: timer@660 { /* General Purpose Timer in GPIO mode */ gpt6: timer@660 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
cell-index = <6>;
reg = <0x660 0x10>; reg = <0x660 0x10>;
interrupts = <0x1 0xf 0x0>; interrupts = <1 15 0>;
interrupt-parent = <&mpc5200_pic>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
gpt7: timer@670 { /* General Purpose Timer in GPIO mode */ gpt7: timer@670 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
cell-index = <7>;
reg = <0x670 0x10>; reg = <0x670 0x10>;
interrupts = <0x1 0x10 0x0>; interrupts = <1 16 0>;
interrupt-parent = <&mpc5200_pic>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
...@@ -144,40 +128,33 @@ gpt7: timer@670 { /* General Purpose Timer in GPIO mode */ ...@@ -144,40 +128,33 @@ gpt7: timer@670 { /* General Purpose Timer in GPIO mode */
rtc@800 { // Real time clock rtc@800 { // Real time clock
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
reg = <0x800 0x100>; reg = <0x800 0x100>;
interrupts = <0x1 0x5 0x0 0x1 0x6 0x0>; interrupts = <1 5 0 1 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
can@900 { can@900 {
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
cell-index = <0>; interrupts = <2 17 0>;
interrupts = <0x2 0x11 0x0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x900 0x80>; reg = <0x900 0x80>;
}; };
can@980 { can@980 {
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
cell-index = <1>; interrupts = <2 18 0>;
interrupts = <0x2 0x12 0x0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x980 0x80>; reg = <0x980 0x80>;
}; };
gpio_simple: gpio@b00 { gpio_simple: gpio@b00 {
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
reg = <0xb00 0x40>; reg = <0xb00 0x40>;
interrupts = <0x1 0x7 0x0>; interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
gpio_wkup: gpio-wkup@c00 { gpio_wkup: gpio@c00 {
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>; reg = <0xc00 0x40>;
interrupts = <0x1 0x8 0x0 0x0 0x3 0x0>; interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
...@@ -185,26 +162,22 @@ gpio_wkup: gpio-wkup@c00 { ...@@ -185,26 +162,22 @@ gpio_wkup: gpio-wkup@c00 {
spi@f00 { spi@f00 {
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
reg = <0xf00 0x20>; reg = <0xf00 0x20>;
interrupts = <0x2 0xd 0x0 0x2 0xe 0x0>; interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
usb@1000 { usb@1000 {
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>; reg = <0x1000 0xff>;
interrupts = <0x2 0x6 0x0>; interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
dma-controller@1200 { dma-controller@1200 {
device_type = "dma-controller";
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
reg = <0x1200 0x80>; reg = <0x1200 0x80>;
interrupts = <0x3 0x0 0x0 0x3 0x1 0x0 0x3 0x2 0x0 0x3 0x3 0x0 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
0x3 0x4 0x0 0x3 0x5 0x0 0x3 0x6 0x0 0x3 0x7 0x0 3 4 0 3 5 0 3 6 0 3 7 0
0x3 0x8 0x0 0x3 0x9 0x0 0x3 0xa 0x0 0x3 0xb 0x0 3 8 0 3 9 0 3 10 0 3 11 0
0x3 0xc 0x0 0x3 0xd 0x0 0x3 0xe 0x0 0x3 0xf 0x0>; 3 12 0 3 13 0 3 14 0 3 15 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
xlb@1f00 { xlb@1f00 {
...@@ -213,24 +186,19 @@ xlb@1f00 { ...@@ -213,24 +186,19 @@ xlb@1f00 {
}; };
ac97@2000 { /* PSC1 in ac97 mode */ ac97@2000 { /* PSC1 in ac97 mode */
device_type = "sound";
compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97"; compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
cell-index = <0>; cell-index = <0>;
reg = <0x2000 0x100>; reg = <0x2000 0x100>;
interrupts = <0x2 0x2 0x0>; interrupts = <2 1 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
/* PSC2 port is used by CAN1/2 */ /* PSC2 port is used by CAN1/2 */
serial@2400 { /* PSC3 in UART mode */ serial@2400 { /* PSC3 in UART mode */
device_type = "serial";
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <0>;
cell-index = <2>; cell-index = <2>;
reg = <0x2400 0x100>; reg = <0x2400 0x100>;
interrupts = <0x2 0x3 0x0>; interrupts = <2 3 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
/* PSC4 is ??? */ /* PSC4 is ??? */
...@@ -238,55 +206,44 @@ serial@2400 { /* PSC3 in UART mode */ ...@@ -238,55 +206,44 @@ serial@2400 { /* PSC3 in UART mode */
/* PSC5 is ??? */ /* PSC5 is ??? */
serial@2c00 { /* PSC6 in UART mode */ serial@2c00 { /* PSC6 in UART mode */
device_type = "serial";
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <1>;
cell-index = <5>; cell-index = <5>;
reg = <0x2c00 0x100>; reg = <0x2c00 0x100>;
interrupts = <0x2 0x4 0x0>; interrupts = <2 4 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
ethernet@3000 { ethernet@3000 {
device_type = "network";
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
reg = <0x3000 0x400>; reg = <0x3000 0x400>;
local-mac-address = [00 00 00 00 00 00]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <0x2 0x5 0x0>; interrupts = <2 5 0>;
interrupt-parent = <&mpc5200_pic>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
}; };
mdio@3000 { mdio@3000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio"; compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
reg = <0x3000 0x400>; /* fec range, since we need to setup fec interrupts */ reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <0x2 0x5 0x0>; /* these are for "mii command finished", not link changes & co. */ interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
phy0: ethernet-phy@0 {
phy0:ethernet-phy@0 { reg = <0>;
device_type = "ethernet-phy";
reg = <0x0>;
}; };
}; };
ata@3a00 { ata@3a00 {
device_type = "ata";
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
reg = <0x3a00 0x100>; reg = <0x3a00 0x100>;
interrupts = <0x2 0x7 0x0>; interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
i2c@3d00 { i2c@3d00 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
cell-index = <0>;
reg = <0x3d00 0x40>; reg = <0x3d00 0x40>;
interrupts = <0x2 0xf 0x0>; interrupts = <2 15 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking; fsl5200-clocking;
}; };
...@@ -294,10 +251,8 @@ i2c@3d40 { ...@@ -294,10 +251,8 @@ i2c@3d40 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
cell-index = <1>;
reg = <0x3d40 0x40>; reg = <0x3d40 0x40>;
interrupts = <0x2 0x10 0x0>; interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking; fsl5200-clocking;
rtc@51 { rtc@51 {
compatible = "nxp,pcf8563"; compatible = "nxp,pcf8563";
...@@ -307,7 +262,7 @@ rtc@51 { ...@@ -307,7 +262,7 @@ rtc@51 {
}; };
sram@8000 { sram@8000 {
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram"; compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
reg = <0x8000 0x4000>; reg = <0x8000 0x4000>;
}; };
...@@ -340,22 +295,21 @@ pci@f0000d00 { ...@@ -340,22 +295,21 @@ pci@f0000d00 {
device_type = "pci"; device_type = "pci";
compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
reg = <0xf0000d00 0x100>; reg = <0xf0000d00 0x100>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0xc000 0x0 0x0 0x1 &mpc5200_pic 0x0 0x0 0x3 /* 1st slot */ interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
0xc000 0x0 0x0 0x2 &mpc5200_pic 0x1 0x1 0x3 0xc000 0 0 2 &mpc5200_pic 1 1 3
0xc000 0x0 0x0 0x3 &mpc5200_pic 0x1 0x2 0x3 0xc000 0 0 3 &mpc5200_pic 1 2 3
0xc000 0x0 0x0 0x4 &mpc5200_pic 0x1 0x3 0x3 0xc000 0 0 4 &mpc5200_pic 1 3 3
0xc800 0x0 0x0 0x1 &mpc5200_pic 0x1 0x1 0x3 /* 2nd slot */ 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
0xc800 0x0 0x0 0x2 &mpc5200_pic 0x1 0x2 0x3 0xc800 0 0 2 &mpc5200_pic 1 2 3
0xc800 0x0 0x0 0x3 &mpc5200_pic 0x1 0x3 0x3 0xc800 0 0 3 &mpc5200_pic 1 3 3
0xc800 0x0 0x0 0x4 &mpc5200_pic 0x0 0x0 0x3>; 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader clock-frequency = <0>; // From boot loader
interrupts = <0x2 0x8 0x0 0x2 0x9 0x0 0x2 0xa 0x0>; interrupts = <2 8 0 2 9 0 2 10 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>; bus-range = <0 0>;
ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
0x01000000 0x0 0x00000000 0xb0000000 0x0 0x01000000>; 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
}; };
}; };
...@@ -17,6 +17,7 @@ / { ...@@ -17,6 +17,7 @@ / {
compatible = "tqc,tqm5200"; compatible = "tqc,tqm5200";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
...@@ -66,36 +67,33 @@ timer@600 { // General Purpose Timer ...@@ -66,36 +67,33 @@ timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt"; compatible = "fsl,mpc5200-gpt";
reg = <0x600 0x10>; reg = <0x600 0x10>;
interrupts = <1 9 0>; interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,has-wdt; fsl,has-wdt;
}; };
can@900 { can@900 {
compatible = "fsl,mpc5200-mscan"; compatible = "fsl,mpc5200-mscan";
interrupts = <2 17 0>; interrupts = <2 17 0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x900 0x80>; reg = <0x900 0x80>;
}; };
can@980 { can@980 {
compatible = "fsl,mpc5200-mscan"; compatible = "fsl,mpc5200-mscan";
interrupts = <2 18 0>; interrupts = <2 18 0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x980 0x80>; reg = <0x980 0x80>;
}; };
gpio@b00 { gpio_simple: gpio@b00 {
compatible = "fsl,mpc5200-gpio"; compatible = "fsl,mpc5200-gpio";
reg = <0xb00 0x40>; reg = <0xb00 0x40>;
interrupts = <1 7 0>; interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>; gpio-controller;
#gpio-cells = <2>;
}; };
usb@1000 { usb@1000 {
compatible = "fsl,mpc5200-ohci","ohci-be"; compatible = "fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>; reg = <0x1000 0xff>;
interrupts = <2 6 0>; interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
dma-controller@1200 { dma-controller@1200 {
...@@ -105,7 +103,6 @@ dma-controller@1200 { ...@@ -105,7 +103,6 @@ dma-controller@1200 {
3 4 0 3 5 0 3 6 0 3 7 0 3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0 3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>; 3 12 0 3 13 0 3 14 0 3 15 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
xlb@1f00 { xlb@1f00 {
...@@ -114,39 +111,28 @@ xlb@1f00 { ...@@ -114,39 +111,28 @@ xlb@1f00 {
}; };
serial@2000 { // PSC1 serial@2000 { // PSC1
device_type = "serial";
compatible = "fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
reg = <0x2000 0x100>; reg = <0x2000 0x100>;
interrupts = <2 1 0>; interrupts = <2 1 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
serial@2200 { // PSC2 serial@2200 { // PSC2
device_type = "serial";
compatible = "fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200-psc-uart";
port-number = <1>; // Logical port assignment
reg = <0x2200 0x100>; reg = <0x2200 0x100>;
interrupts = <2 2 0>; interrupts = <2 2 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
serial@2400 { // PSC3 serial@2400 { // PSC3
device_type = "serial";
compatible = "fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200-psc-uart";
port-number = <2>; // Logical port assignment
reg = <0x2400 0x100>; reg = <0x2400 0x100>;
interrupts = <2 3 0>; interrupts = <2 3 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
ethernet@3000 { ethernet@3000 {
device_type = "network";
compatible = "fsl,mpc5200-fec"; compatible = "fsl,mpc5200-fec";
reg = <0x3000 0x400>; reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>; interrupts = <2 5 0>;
interrupt-parent = <&mpc5200_pic>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
}; };
...@@ -156,10 +142,8 @@ mdio@3000 { ...@@ -156,10 +142,8 @@ mdio@3000 {
compatible = "fsl,mpc5200-mdio"; compatible = "fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
device_type = "ethernet-phy";
reg = <0>; reg = <0>;
}; };
}; };
...@@ -168,7 +152,6 @@ ata@3a00 { ...@@ -168,7 +152,6 @@ ata@3a00 {
compatible = "fsl,mpc5200-ata"; compatible = "fsl,mpc5200-ata";
reg = <0x3a00 0x100>; reg = <0x3a00 0x100>;
interrupts = <2 7 0>; interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
i2c@3d40 { i2c@3d40 {
...@@ -177,7 +160,6 @@ i2c@3d40 { ...@@ -177,7 +160,6 @@ i2c@3d40 {
compatible = "fsl,mpc5200-i2c","fsl-i2c"; compatible = "fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>; reg = <0x3d40 0x40>;
interrupts = <2 16 0>; interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking; fsl5200-clocking;
rtc@68 { rtc@68 {
...@@ -192,9 +174,8 @@ sram@8000 { ...@@ -192,9 +174,8 @@ sram@8000 {
}; };
}; };
lpb { localbus {
model = "fsl,lpb"; compatible = "fsl,mpc5200-lpb","simple-bus";
compatible = "fsl,lpb";
#address-cells = <2>; #address-cells = <2>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0 0 0xfc000000 0x02000000>; ranges = <0 0 0xfc000000 0x02000000>;
...@@ -223,7 +204,6 @@ pci@f0000d00 { ...@@ -223,7 +204,6 @@ pci@f0000d00 {
0xc000 0 0 4 &mpc5200_pic 0 0 3>; 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 10 0>; interrupts = <2 8 0 2 9 0 2 10 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>; bus-range = <0 0>;
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
0x02000000 0 0x90000000 0x90000000 0 0x10000000 0x02000000 0 0x90000000 0x90000000 0 0x10000000
......
...@@ -21,7 +21,12 @@ config PPC_MPC5200_SIMPLE ...@@ -21,7 +21,12 @@ config PPC_MPC5200_SIMPLE
and if there is a PCI bus node defined in the device tree. and if there is a PCI bus node defined in the device tree.
Boards that are compatible with this generic platform support Boards that are compatible with this generic platform support
are: 'tqc,tqm5200', 'promess,motionpro', 'schindler,cm5200'. are:
intercontrol,digsy-mtc
phytec,pcm030
promess,motionpro
schindler,cm5200
tqc,tqm5200
config PPC_EFIKA config PPC_EFIKA
bool "bPlan Efika 5k2. MPC5200B based computer" bool "bPlan Efika 5k2. MPC5200B based computer"
...@@ -35,6 +40,11 @@ config PPC_LITE5200 ...@@ -35,6 +40,11 @@ config PPC_LITE5200
depends on PPC_MPC52xx depends on PPC_MPC52xx
select DEFAULT_UIMAGE select DEFAULT_UIMAGE
config PPC_MEDIA5200
bool "Freescale Media5200 Eval Board"
depends on PPC_MPC52xx
select DEFAULT_UIMAGE
config PPC_MPC5200_BUGFIX config PPC_MPC5200_BUGFIX
bool "MPC5200 (L25R) bugfix support" bool "MPC5200 (L25R) bugfix support"
depends on PPC_MPC52xx depends on PPC_MPC52xx
......
# #
# Makefile for 52xx based boards # Makefile for 52xx based boards
# #
obj-y += mpc52xx_pic.o mpc52xx_common.o obj-y += mpc52xx_pic.o mpc52xx_common.o mpc52xx_gpt.o
obj-$(CONFIG_PCI) += mpc52xx_pci.o obj-$(CONFIG_PCI) += mpc52xx_pci.o
obj-$(CONFIG_PPC_MPC5200_SIMPLE) += mpc5200_simple.o obj-$(CONFIG_PPC_MPC5200_SIMPLE) += mpc5200_simple.o
obj-$(CONFIG_PPC_EFIKA) += efika.o obj-$(CONFIG_PPC_EFIKA) += efika.o
obj-$(CONFIG_PPC_LITE5200) += lite5200.o obj-$(CONFIG_PPC_LITE5200) += lite5200.o
obj-$(CONFIG_PPC_MEDIA5200) += media5200.o
obj-$(CONFIG_PM) += mpc52xx_sleep.o mpc52xx_pm.o obj-$(CONFIG_PM) += mpc52xx_sleep.o mpc52xx_pm.o
ifeq ($(CONFIG_PPC_LITE5200),y) ifeq ($(CONFIG_PPC_LITE5200),y)
......
/*
* Support for 'media5200-platform' compatible boards.
*
* Copyright (C) 2008 Secret Lab Technologies Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Description:
* This code implements support for the Freescape Media5200 platform
* (built around the MPC5200 SoC).
*
* Notable characteristic of the Media5200 is the presence of an FPGA
* that has all external IRQ lines routed through it. This file implements
* a cascaded interrupt controller driver which attaches itself to the
* Virtual IRQ subsystem after the primary mpc5200 interrupt controller
* is initialized.
*
*/
#undef DEBUG
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <asm/time.h>
#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/mpc52xx.h>
static struct of_device_id mpc5200_gpio_ids[] __initdata = {
{ .compatible = "fsl,mpc5200-gpio", },
{ .compatible = "mpc5200-gpio", },
{}
};
/* FPGA register set */
#define MEDIA5200_IRQ_ENABLE (0x40c)
#define MEDIA5200_IRQ_STATUS (0x410)
#define MEDIA5200_NUM_IRQS (6)
#define MEDIA5200_IRQ_SHIFT (32 - MEDIA5200_NUM_IRQS)
struct media5200_irq {
void __iomem *regs;
spinlock_t lock;
struct irq_host *irqhost;
};
struct media5200_irq media5200_irq;
static void media5200_irq_unmask(unsigned int virq)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&media5200_irq.lock, flags);
val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
val |= 1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq);
out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
spin_unlock_irqrestore(&media5200_irq.lock, flags);
}
static void media5200_irq_mask(unsigned int virq)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&media5200_irq.lock, flags);
val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq));
out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
spin_unlock_irqrestore(&media5200_irq.lock, flags);
}
static struct irq_chip media5200_irq_chip = {
.typename = "Media5200 FPGA",
.unmask = media5200_irq_unmask,
.mask = media5200_irq_mask,
.mask_ack = media5200_irq_mask,
};
void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
{
int sub_virq, val;
u32 status, enable;
/* Mask off the cascaded IRQ */
spin_lock(&desc->lock);
desc->chip->mask(virq);
spin_unlock(&desc->lock);
/* Ask the FPGA for IRQ status. If 'val' is 0, then no irqs
* are pending. 'ffs()' is 1 based */
status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);
val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT);
if (val) {
sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1);
/* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i subvirq=%i\n",
* __func__, virq, status, enable, val - 1, sub_virq);
*/
generic_handle_irq(sub_virq);
}
/* Processing done; can reenable the cascade now */
spin_lock(&desc->lock);
desc->chip->ack(virq);
if (!(desc->status & IRQ_DISABLED))
desc->chip->unmask(virq);
spin_unlock(&desc->lock);
}
static int media5200_irq_map(struct irq_host *h, unsigned int virq,
irq_hw_number_t hw)
{
struct irq_desc *desc = get_irq_desc(virq);
pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
set_irq_chip_data(virq, &media5200_irq);
set_irq_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
desc->status |= IRQ_TYPE_LEVEL_LOW | IRQ_LEVEL;
return 0;
}
static int media5200_irq_xlate(struct irq_host *h, struct device_node *ct,
u32 *intspec, unsigned int intsize,
irq_hw_number_t *out_hwirq,
unsigned int *out_flags)
{
if (intsize != 2)
return -1;
pr_debug("%s: bank=%i, number=%i\n", __func__, intspec[0], intspec[1]);
*out_hwirq = intspec[1];
*out_flags = IRQ_TYPE_NONE;
return 0;
}
static struct irq_host_ops media5200_irq_ops = {
.map = media5200_irq_map,
.xlate = media5200_irq_xlate,
};
/*
* Setup Media5200 IRQ mapping
*/
static void __init media5200_init_irq(void)
{
struct device_node *fpga_np;
int cascade_virq;
/* First setup the regular MPC5200 interrupt controller */
mpc52xx_init_irq();
/* Now find the FPGA IRQ */
fpga_np = of_find_compatible_node(NULL, NULL, "fsl,media5200-fpga");
if (!fpga_np)
goto out;
pr_debug("%s: found fpga node: %s\n", __func__, fpga_np->full_name);
media5200_irq.regs = of_iomap(fpga_np, 0);
if (!media5200_irq.regs)
goto out;
pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs);
cascade_virq = irq_of_parse_and_map(fpga_np, 0);
if (!cascade_virq)
goto out;
pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq);
/* Disable all FPGA IRQs */
out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0);
spin_lock_init(&media5200_irq.lock);
media5200_irq.irqhost = irq_alloc_host(fpga_np, IRQ_HOST_MAP_LINEAR,
MEDIA5200_NUM_IRQS,
&media5200_irq_ops, -1);
if (!media5200_irq.irqhost)
goto out;
pr_debug("%s: allocated irqhost\n", __func__);
media5200_irq.irqhost->host_data = &media5200_irq;
set_irq_data(cascade_virq, &media5200_irq);
set_irq_chained_handler(cascade_virq, media5200_irq_cascade);
return;
out:
pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n");
}
/*
* Setup the architecture
*/
static void __init media5200_setup_arch(void)
{
struct device_node *np;
struct mpc52xx_gpio __iomem *gpio;
u32 port_config;
if (ppc_md.progress)
ppc_md.progress("media5200_setup_arch()", 0);
/* Map important registers from the internal memory map */
mpc52xx_map_common_devices();
/* Some mpc5200 & mpc5200b related configuration */
mpc5200_setup_xlb_arbiter();
mpc52xx_setup_pci();
np = of_find_matching_node(NULL, mpc5200_gpio_ids);
gpio = of_iomap(np, 0);
of_node_put(np);
if (!gpio) {
printk(KERN_ERR "%s() failed. expect abnormal behavior\n",
__func__);
return;
}
/* Set port config */
port_config = in_be32(&gpio->port_config);
port_config &= ~0x03000000; /* ATA CS is on csb_4/5 */
port_config |= 0x01000000;
out_be32(&gpio->port_config, port_config);
/* Unmap zone */
iounmap(gpio);
}
/* list of the supported boards */
static char *board[] __initdata = {
"fsl,media5200",
NULL
};
/*
* Called very early, MMU is off, device-tree isn't unflattened
*/
static int __init media5200_probe(void)
{
unsigned long node = of_get_flat_dt_root();
int i = 0;
while (board[i]) {
if (of_flat_dt_is_compatible(node, board[i]))
break;
i++;
}
return (board[i] != NULL);
}
define_machine(media5200_platform) {
.name = "media5200-platform",
.probe = media5200_probe,
.setup_arch = media5200_setup_arch,
.init = mpc52xx_declare_of_platform_devices,
.init_IRQ = media5200_init_irq,
.get_irq = mpc52xx_get_irq,
.restart = mpc52xx_restart,
.calibrate_decr = generic_calibrate_decr,
};
...@@ -50,6 +50,7 @@ static void __init mpc5200_simple_setup_arch(void) ...@@ -50,6 +50,7 @@ static void __init mpc5200_simple_setup_arch(void)
/* list of the supported boards */ /* list of the supported boards */
static char *board[] __initdata = { static char *board[] __initdata = {
"intercontrol,digsy-mtc",
"promess,motionpro", "promess,motionpro",
"phytec,pcm030", "phytec,pcm030",
"schindler,cm5200", "schindler,cm5200",
......
...@@ -354,88 +354,6 @@ static struct of_platform_driver mpc52xx_simple_gpiochip_driver = { ...@@ -354,88 +354,6 @@ static struct of_platform_driver mpc52xx_simple_gpiochip_driver = {
.remove = mpc52xx_gpiochip_remove, .remove = mpc52xx_gpiochip_remove,
}; };
/*
* GPIO LIB API implementation for gpt GPIOs.
*
* Each gpt only has a single GPIO.
*/
static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct mpc52xx_gpt __iomem *regs = mm_gc->regs;
return (in_be32(&regs->status) & (1 << (31 - 23))) ? 1 : 0;
}
static void
mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct mpc52xx_gpt __iomem *regs = mm_gc->regs;
if (val)
out_be32(&regs->mode, 0x34);
else
out_be32(&regs->mode, 0x24);
pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
}
static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct mpc52xx_gpt __iomem *regs = mm_gc->regs;
out_be32(&regs->mode, 0x04);
return 0;
}
static int
mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
mpc52xx_gpt_gpio_set(gc, gpio, val);
pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
return 0;
}
static int __devinit mpc52xx_gpt_gpiochip_probe(struct of_device *ofdev,
const struct of_device_id *match)
{
struct of_mm_gpio_chip *mmchip;
struct of_gpio_chip *chip;
mmchip = kzalloc(sizeof(*mmchip), GFP_KERNEL);
if (!mmchip)
return -ENOMEM;
chip = &mmchip->of_gc;
chip->gpio_cells = 2;
chip->gc.ngpio = 1;
chip->gc.direction_input = mpc52xx_gpt_gpio_dir_in;
chip->gc.direction_output = mpc52xx_gpt_gpio_dir_out;
chip->gc.get = mpc52xx_gpt_gpio_get;
chip->gc.set = mpc52xx_gpt_gpio_set;
return of_mm_gpiochip_add(ofdev->node, mmchip);
}
static const struct of_device_id mpc52xx_gpt_gpiochip_match[] = {
{
.compatible = "fsl,mpc5200-gpt-gpio",
},
{}
};
static struct of_platform_driver mpc52xx_gpt_gpiochip_driver = {
.name = "gpio_gpt",
.match_table = mpc52xx_gpt_gpiochip_match,
.probe = mpc52xx_gpt_gpiochip_probe,
.remove = mpc52xx_gpiochip_remove,
};
static int __init mpc52xx_gpio_init(void) static int __init mpc52xx_gpio_init(void)
{ {
if (of_register_platform_driver(&mpc52xx_wkup_gpiochip_driver)) if (of_register_platform_driver(&mpc52xx_wkup_gpiochip_driver))
...@@ -444,9 +362,6 @@ static int __init mpc52xx_gpio_init(void) ...@@ -444,9 +362,6 @@ static int __init mpc52xx_gpio_init(void)
if (of_register_platform_driver(&mpc52xx_simple_gpiochip_driver)) if (of_register_platform_driver(&mpc52xx_simple_gpiochip_driver))
printk(KERN_ERR "Unable to register simple GPIO driver\n"); printk(KERN_ERR "Unable to register simple GPIO driver\n");
if (of_register_platform_driver(&mpc52xx_gpt_gpiochip_driver))
printk(KERN_ERR "Unable to register gpt GPIO driver\n");
return 0; return 0;
} }
......
/*
* MPC5200 General Purpose Timer device driver
*
* Copyright (c) 2009 Secret Lab Technologies Ltd.
* Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This file is a driver for the the General Purpose Timer (gpt) devices
* found on the MPC5200 SoC. Each timer has an IO pin which can be used
* for GPIO or can be used to raise interrupts. The timer function can
* be used independently from the IO pin, or it can be used to control
* output signals or measure input signals.
*
* This driver supports the GPIO and IRQ controller functions of the GPT
* device. Timer functions are not yet supported, nor is the watchdog
* timer.
*
* To use the GPIO function, the following two properties must be added
* to the device tree node for the gpt device (typically in the .dts file
* for the board):
* gpio-controller;
* #gpio-cells = < 2 >;
* This driver will register the GPIO pin if it finds the gpio-controller
* property in the device tree.
*
* To use the IRQ controller function, the following two properties must
* be added to the device tree node for the gpt device:
* interrupt-controller;
* #interrupt-cells = < 1 >;
* The IRQ controller binding only uses one cell to specify the interrupt,
* and the IRQ flags are encoded in the cell. A cell is not used to encode
* the IRQ number because the GPT only has a single IRQ source. For flags,
* a value of '1' means rising edge sensitive and '2' means falling edge.
*
* The GPIO and the IRQ controller functions can be used at the same time,
* but in this use case the IO line will only work as an input. Trying to
* use it as a GPIO output will not work.
*
* When using the GPIO line as an output, it can either be driven as normal
* IO, or it can be an Open Collector (OC) output. At the moment it is the
* responsibility of either the bootloader or the platform setup code to set
* the output mode. This driver does not change the output mode setting.
*/
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/of_gpio.h>
#include <linux/kernel.h>
#include <asm/mpc52xx.h>
MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
MODULE_AUTHOR("Sascha Hauer, Grant Likely");
MODULE_LICENSE("GPL");
/**
* struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver
* @dev: pointer to device structure
* @regs: virtual address of GPT registers
* @lock: spinlock to coordinate between different functions.
* @of_gc: of_gpio_chip instance structure; used when GPIO is enabled
* @irqhost: Pointer to irq_host instance; used when IRQ mode is supported
*/
struct mpc52xx_gpt_priv {
struct device *dev;
struct mpc52xx_gpt __iomem *regs;
spinlock_t lock;
struct irq_host *irqhost;
#if defined(CONFIG_GPIOLIB)
struct of_gpio_chip of_gc;
#endif
};
#define MPC52xx_GPT_MODE_MS_MASK (0x07)
#define MPC52xx_GPT_MODE_MS_IC (0x01)
#define MPC52xx_GPT_MODE_MS_OC (0x02)
#define MPC52xx_GPT_MODE_MS_PWM (0x03)
#define MPC52xx_GPT_MODE_MS_GPIO (0x04)
#define MPC52xx_GPT_MODE_GPIO_MASK (0x30)
#define MPC52xx_GPT_MODE_GPIO_OUT_LOW (0x20)
#define MPC52xx_GPT_MODE_GPIO_OUT_HIGH (0x30)
#define MPC52xx_GPT_MODE_IRQ_EN (0x0100)
#define MPC52xx_GPT_MODE_ICT_MASK (0x030000)
#define MPC52xx_GPT_MODE_ICT_RISING (0x010000)
#define MPC52xx_GPT_MODE_ICT_FALLING (0x020000)
#define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000)
#define MPC52xx_GPT_STATUS_IRQMASK (0x000f)
/* ---------------------------------------------------------------------
* Cascaded interrupt controller hooks
*/
static void mpc52xx_gpt_irq_unmask(unsigned int virq)
{
struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
unsigned long flags;
spin_lock_irqsave(&gpt->lock, flags);
setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
spin_unlock_irqrestore(&gpt->lock, flags);
}
static void mpc52xx_gpt_irq_mask(unsigned int virq)
{
struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
unsigned long flags;
spin_lock_irqsave(&gpt->lock, flags);
clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
spin_unlock_irqrestore(&gpt->lock, flags);
}
static void mpc52xx_gpt_irq_ack(unsigned int virq)
{
struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK);
}
static int mpc52xx_gpt_irq_set_type(unsigned int virq, unsigned int flow_type)
{
struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
unsigned long flags;
u32 reg;
dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, virq, flow_type);
spin_lock_irqsave(&gpt->lock, flags);
reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK;
if (flow_type & IRQF_TRIGGER_RISING)
reg |= MPC52xx_GPT_MODE_ICT_RISING;
if (flow_type & IRQF_TRIGGER_FALLING)
reg |= MPC52xx_GPT_MODE_ICT_FALLING;
out_be32(&gpt->regs->mode, reg);
spin_unlock_irqrestore(&gpt->lock, flags);
return 0;
}
static struct irq_chip mpc52xx_gpt_irq_chip = {
.typename = "MPC52xx GPT",
.unmask = mpc52xx_gpt_irq_unmask,
.mask = mpc52xx_gpt_irq_mask,
.ack = mpc52xx_gpt_irq_ack,
.set_type = mpc52xx_gpt_irq_set_type,
};
void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc)
{
struct mpc52xx_gpt_priv *gpt = get_irq_data(virq);
int sub_virq;
u32 status;
status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK;
if (status) {
sub_virq = irq_linear_revmap(gpt->irqhost, 0);
generic_handle_irq(sub_virq);
}
}
static int mpc52xx_gpt_irq_map(struct irq_host *h, unsigned int virq,
irq_hw_number_t hw)
{
struct mpc52xx_gpt_priv *gpt = h->host_data;
dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq);
set_irq_chip_data(virq, gpt);
set_irq_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq);
return 0;
}
static int mpc52xx_gpt_irq_xlate(struct irq_host *h, struct device_node *ct,
u32 *intspec, unsigned int intsize,
irq_hw_number_t *out_hwirq,
unsigned int *out_flags)
{
struct mpc52xx_gpt_priv *gpt = h->host_data;
dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]);
if ((intsize < 1) || (intspec[0] < 1) || (intspec[0] > 3)) {
dev_err(gpt->dev, "bad irq specifier in %s\n", ct->full_name);
return -EINVAL;
}
*out_hwirq = 0; /* The GPT only has 1 IRQ line */
*out_flags = intspec[0];
return 0;
}
static struct irq_host_ops mpc52xx_gpt_irq_ops = {
.map = mpc52xx_gpt_irq_map,
.xlate = mpc52xx_gpt_irq_xlate,
};
static void
mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
{
int cascade_virq;
unsigned long flags;
/* Only setup cascaded IRQ if device tree claims the GPT is
* an interrupt controller */
if (!of_find_property(node, "interrupt-controller", NULL))
return;
cascade_virq = irq_of_parse_and_map(node, 0);
gpt->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 1,
&mpc52xx_gpt_irq_ops, -1);
if (!gpt->irqhost) {
dev_err(gpt->dev, "irq_alloc_host() failed\n");
return;
}
gpt->irqhost->host_data = gpt;
set_irq_data(cascade_virq, gpt);
set_irq_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
/* Set to Input Capture mode */
spin_lock_irqsave(&gpt->lock, flags);
clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
MPC52xx_GPT_MODE_MS_IC);
spin_unlock_irqrestore(&gpt->lock, flags);
dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq);
}
/* ---------------------------------------------------------------------
* GPIOLIB hooks
*/
#if defined(CONFIG_GPIOLIB)
static inline struct mpc52xx_gpt_priv *gc_to_mpc52xx_gpt(struct gpio_chip *gc)
{
return container_of(to_of_gpio_chip(gc), struct mpc52xx_gpt_priv,of_gc);
}
static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
return (in_be32(&gpt->regs->status) >> 8) & 1;
}
static void
mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v)
{
struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
unsigned long flags;
u32 r;
dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v);
r = v ? MPC52xx_GPT_MODE_GPIO_OUT_HIGH : MPC52xx_GPT_MODE_GPIO_OUT_LOW;
spin_lock_irqsave(&gpt->lock, flags);
clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r);
spin_unlock_irqrestore(&gpt->lock, flags);
}
static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
unsigned long flags;
dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio);
spin_lock_irqsave(&gpt->lock, flags);
clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
spin_unlock_irqrestore(&gpt->lock, flags);
return 0;
}
static int
mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
mpc52xx_gpt_gpio_set(gc, gpio, val);
return 0;
}
static void
mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
{
int rc;
/* Only setup GPIO if the device tree claims the GPT is
* a GPIO controller */
if (!of_find_property(node, "gpio-controller", NULL))
return;
gpt->of_gc.gc.label = kstrdup(node->full_name, GFP_KERNEL);
if (!gpt->of_gc.gc.label) {
dev_err(gpt->dev, "out of memory\n");
return;
}
gpt->of_gc.gpio_cells = 2;
gpt->of_gc.gc.ngpio = 1;
gpt->of_gc.gc.direction_input = mpc52xx_gpt_gpio_dir_in;
gpt->of_gc.gc.direction_output = mpc52xx_gpt_gpio_dir_out;
gpt->of_gc.gc.get = mpc52xx_gpt_gpio_get;
gpt->of_gc.gc.set = mpc52xx_gpt_gpio_set;
gpt->of_gc.gc.base = -1;
gpt->of_gc.xlate = of_gpio_simple_xlate;
node->data = &gpt->of_gc;
of_node_get(node);
/* Setup external pin in GPIO mode */
clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
MPC52xx_GPT_MODE_MS_GPIO);
rc = gpiochip_add(&gpt->of_gc.gc);
if (rc)
dev_err(gpt->dev, "gpiochip_add() failed; rc=%i\n", rc);
dev_dbg(gpt->dev, "%s() complete.\n", __func__);
}
#else /* defined(CONFIG_GPIOLIB) */
static void
mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *p, struct device_node *np) { }
#endif /* defined(CONFIG_GPIOLIB) */
/***********************************************************************
* SYSFS attributes
*/
#if defined(CONFIG_SYSFS)
static ssize_t mpc52xx_gpt_show_regs(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct mpc52xx_gpt_priv *gpt = dev_get_drvdata(dev);
int i, len = 0;
u32 __iomem *regs = (void __iomem *) gpt->regs;
for (i = 0; i < 4; i++)
len += sprintf(buf + len, "%.8x ", in_be32(regs + i));
len += sprintf(buf + len, "\n");
return len;
}
static struct device_attribute mpc52xx_gpt_attrib[] = {
__ATTR(regs, S_IRUGO | S_IWUSR, mpc52xx_gpt_show_regs, NULL),
};
static void mpc52xx_gpt_create_attribs(struct mpc52xx_gpt_priv *gpt)
{
int i, err = 0;
for (i = 0; i < ARRAY_SIZE(mpc52xx_gpt_attrib); i++) {
err = device_create_file(gpt->dev, &mpc52xx_gpt_attrib[i]);
if (err)
dev_err(gpt->dev, "error creating attribute %i\n", i);
}
}
#else /* defined(CONFIG_SYSFS) */
static void mpc52xx_gpt_create_attribs(struct mpc52xx_gpt_priv *) { return 0; }
#endif /* defined(CONFIG_SYSFS) */
/* ---------------------------------------------------------------------
* of_platform bus binding code
*/
static int __devinit mpc52xx_gpt_probe(struct of_device *ofdev,
const struct of_device_id *match)
{
struct mpc52xx_gpt_priv *gpt;
gpt = kzalloc(sizeof *gpt, GFP_KERNEL);
if (!gpt)
return -ENOMEM;
spin_lock_init(&gpt->lock);
gpt->dev = &ofdev->dev;
gpt->regs = of_iomap(ofdev->node, 0);
if (!gpt->regs) {
kfree(gpt);
return -ENOMEM;
}
dev_set_drvdata(&ofdev->dev, gpt);
mpc52xx_gpt_create_attribs(gpt);
mpc52xx_gpt_gpio_setup(gpt, ofdev->node);
mpc52xx_gpt_irq_setup(gpt, ofdev->node);
return 0;
}
static int mpc52xx_gpt_remove(struct of_device *ofdev)
{
return -EBUSY;
}
static const struct of_device_id mpc52xx_gpt_match[] = {
{ .compatible = "fsl,mpc5200-gpt", },
/* Depreciated compatible values; don't use for new dts files */
{ .compatible = "fsl,mpc5200-gpt-gpio", },
{ .compatible = "mpc5200-gpt", },
{}
};
static struct of_platform_driver mpc52xx_gpt_driver = {
.name = "mpc52xx-gpt",
.match_table = mpc52xx_gpt_match,
.probe = mpc52xx_gpt_probe,
.remove = mpc52xx_gpt_remove,
};
static int __init mpc52xx_gpt_init(void)
{
if (of_register_platform_driver(&mpc52xx_gpt_driver))
pr_err("error registering MPC52xx GPT driver\n");
return 0;
}
/* Make sure GPIOs and IRQs get set up before anyone tries to use them */
subsys_initcall(mpc52xx_gpt_init);
...@@ -163,8 +163,6 @@ static void mpc52xx_extirq_mask(unsigned int virq) ...@@ -163,8 +163,6 @@ static void mpc52xx_extirq_mask(unsigned int virq)
irq = irq_map[virq].hwirq; irq = irq_map[virq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK; l2irq = irq & MPC52xx_IRQ_L2_MASK;
pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
io_be_clrbit(&intr->ctrl, 11 - l2irq); io_be_clrbit(&intr->ctrl, 11 - l2irq);
} }
...@@ -176,8 +174,6 @@ static void mpc52xx_extirq_unmask(unsigned int virq) ...@@ -176,8 +174,6 @@ static void mpc52xx_extirq_unmask(unsigned int virq)
irq = irq_map[virq].hwirq; irq = irq_map[virq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK; l2irq = irq & MPC52xx_IRQ_L2_MASK;
pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
io_be_setbit(&intr->ctrl, 11 - l2irq); io_be_setbit(&intr->ctrl, 11 - l2irq);
} }
...@@ -189,17 +185,15 @@ static void mpc52xx_extirq_ack(unsigned int virq) ...@@ -189,17 +185,15 @@ static void mpc52xx_extirq_ack(unsigned int virq)
irq = irq_map[virq].hwirq; irq = irq_map[virq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK; l2irq = irq & MPC52xx_IRQ_L2_MASK;
pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
io_be_setbit(&intr->ctrl, 27-l2irq); io_be_setbit(&intr->ctrl, 27-l2irq);
} }
static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type) static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type)
{ {
struct irq_desc *desc = get_irq_desc(virq);
u32 ctrl_reg, type; u32 ctrl_reg, type;
int irq; int irq;
int l2irq; int l2irq;
void *handler = handle_level_irq;
irq = irq_map[virq].hwirq; irq = irq_map[virq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK; l2irq = irq & MPC52xx_IRQ_L2_MASK;
...@@ -207,32 +201,21 @@ static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type) ...@@ -207,32 +201,21 @@ static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type)
pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__, irq, l2irq, flow_type); pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__, irq, l2irq, flow_type);
switch (flow_type) { switch (flow_type) {
case IRQF_TRIGGER_HIGH: case IRQF_TRIGGER_HIGH: type = 0; break;
type = 0; case IRQF_TRIGGER_RISING: type = 1; handler = handle_edge_irq; break;
break; case IRQF_TRIGGER_FALLING: type = 2; handler = handle_edge_irq; break;
case IRQF_TRIGGER_RISING: case IRQF_TRIGGER_LOW: type = 3; break;
type = 1;
break;
case IRQF_TRIGGER_FALLING:
type = 2;
break;
case IRQF_TRIGGER_LOW:
type = 3;
break;
default: default:
type = 0; type = 0;
} }
desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
desc->status |= IRQ_LEVEL;
ctrl_reg = in_be32(&intr->ctrl); ctrl_reg = in_be32(&intr->ctrl);
ctrl_reg &= ~(0x3 << (22 - (l2irq * 2))); ctrl_reg &= ~(0x3 << (22 - (l2irq * 2)));
ctrl_reg |= (type << (22 - (l2irq * 2))); ctrl_reg |= (type << (22 - (l2irq * 2)));
out_be32(&intr->ctrl, ctrl_reg); out_be32(&intr->ctrl, ctrl_reg);
__set_irq_handler_unlocked(virq, handler);
return 0; return 0;
} }
...@@ -247,6 +230,11 @@ static struct irq_chip mpc52xx_extirq_irqchip = { ...@@ -247,6 +230,11 @@ static struct irq_chip mpc52xx_extirq_irqchip = {
/* /*
* Main interrupt irq_chip * Main interrupt irq_chip
*/ */
static int mpc52xx_null_set_type(unsigned int virq, unsigned int flow_type)
{
return 0; /* Do nothing so that the sense mask will get updated */
}
static void mpc52xx_main_mask(unsigned int virq) static void mpc52xx_main_mask(unsigned int virq)
{ {
int irq; int irq;
...@@ -255,8 +243,6 @@ static void mpc52xx_main_mask(unsigned int virq) ...@@ -255,8 +243,6 @@ static void mpc52xx_main_mask(unsigned int virq)
irq = irq_map[virq].hwirq; irq = irq_map[virq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK; l2irq = irq & MPC52xx_IRQ_L2_MASK;
pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
io_be_setbit(&intr->main_mask, 16 - l2irq); io_be_setbit(&intr->main_mask, 16 - l2irq);
} }
...@@ -268,8 +254,6 @@ static void mpc52xx_main_unmask(unsigned int virq) ...@@ -268,8 +254,6 @@ static void mpc52xx_main_unmask(unsigned int virq)
irq = irq_map[virq].hwirq; irq = irq_map[virq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK; l2irq = irq & MPC52xx_IRQ_L2_MASK;
pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
io_be_clrbit(&intr->main_mask, 16 - l2irq); io_be_clrbit(&intr->main_mask, 16 - l2irq);
} }
...@@ -278,6 +262,7 @@ static struct irq_chip mpc52xx_main_irqchip = { ...@@ -278,6 +262,7 @@ static struct irq_chip mpc52xx_main_irqchip = {
.mask = mpc52xx_main_mask, .mask = mpc52xx_main_mask,
.mask_ack = mpc52xx_main_mask, .mask_ack = mpc52xx_main_mask,
.unmask = mpc52xx_main_unmask, .unmask = mpc52xx_main_unmask,
.set_type = mpc52xx_null_set_type,
}; };
/* /*
...@@ -291,8 +276,6 @@ static void mpc52xx_periph_mask(unsigned int virq) ...@@ -291,8 +276,6 @@ static void mpc52xx_periph_mask(unsigned int virq)
irq = irq_map[virq].hwirq; irq = irq_map[virq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK; l2irq = irq & MPC52xx_IRQ_L2_MASK;
pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
io_be_setbit(&intr->per_mask, 31 - l2irq); io_be_setbit(&intr->per_mask, 31 - l2irq);
} }
...@@ -304,8 +287,6 @@ static void mpc52xx_periph_unmask(unsigned int virq) ...@@ -304,8 +287,6 @@ static void mpc52xx_periph_unmask(unsigned int virq)
irq = irq_map[virq].hwirq; irq = irq_map[virq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK; l2irq = irq & MPC52xx_IRQ_L2_MASK;
pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
io_be_clrbit(&intr->per_mask, 31 - l2irq); io_be_clrbit(&intr->per_mask, 31 - l2irq);
} }
...@@ -314,6 +295,7 @@ static struct irq_chip mpc52xx_periph_irqchip = { ...@@ -314,6 +295,7 @@ static struct irq_chip mpc52xx_periph_irqchip = {
.mask = mpc52xx_periph_mask, .mask = mpc52xx_periph_mask,
.mask_ack = mpc52xx_periph_mask, .mask_ack = mpc52xx_periph_mask,
.unmask = mpc52xx_periph_unmask, .unmask = mpc52xx_periph_unmask,
.set_type = mpc52xx_null_set_type,
}; };
/* /*
...@@ -327,8 +309,6 @@ static void mpc52xx_sdma_mask(unsigned int virq) ...@@ -327,8 +309,6 @@ static void mpc52xx_sdma_mask(unsigned int virq)
irq = irq_map[virq].hwirq; irq = irq_map[virq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK; l2irq = irq & MPC52xx_IRQ_L2_MASK;
pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
io_be_setbit(&sdma->IntMask, l2irq); io_be_setbit(&sdma->IntMask, l2irq);
} }
...@@ -340,8 +320,6 @@ static void mpc52xx_sdma_unmask(unsigned int virq) ...@@ -340,8 +320,6 @@ static void mpc52xx_sdma_unmask(unsigned int virq)
irq = irq_map[virq].hwirq; irq = irq_map[virq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK; l2irq = irq & MPC52xx_IRQ_L2_MASK;
pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
io_be_clrbit(&sdma->IntMask, l2irq); io_be_clrbit(&sdma->IntMask, l2irq);
} }
...@@ -353,8 +331,6 @@ static void mpc52xx_sdma_ack(unsigned int virq) ...@@ -353,8 +331,6 @@ static void mpc52xx_sdma_ack(unsigned int virq)
irq = irq_map[virq].hwirq; irq = irq_map[virq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK; l2irq = irq & MPC52xx_IRQ_L2_MASK;
pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
out_be32(&sdma->IntPend, 1 << l2irq); out_be32(&sdma->IntPend, 1 << l2irq);
} }
...@@ -363,8 +339,18 @@ static struct irq_chip mpc52xx_sdma_irqchip = { ...@@ -363,8 +339,18 @@ static struct irq_chip mpc52xx_sdma_irqchip = {
.mask = mpc52xx_sdma_mask, .mask = mpc52xx_sdma_mask,
.unmask = mpc52xx_sdma_unmask, .unmask = mpc52xx_sdma_unmask,
.ack = mpc52xx_sdma_ack, .ack = mpc52xx_sdma_ack,
.set_type = mpc52xx_null_set_type,
}; };
/**
* mpc52xx_is_extirq - Returns true if hwirq number is for an external IRQ
*/
static int mpc52xx_is_extirq(int l1, int l2)
{
return ((l1 == 0) && (l2 == 0)) ||
((l1 == 1) && (l2 >= 1) && (l2 <= 3));
}
/** /**
* mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property * mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property
*/ */
...@@ -383,37 +369,22 @@ static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct, ...@@ -383,37 +369,22 @@ static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
intrvect_l1 = (int)intspec[0]; intrvect_l1 = (int)intspec[0];
intrvect_l2 = (int)intspec[1]; intrvect_l2 = (int)intspec[1];
intrvect_type = (int)intspec[2]; intrvect_type = (int)intspec[2] & 0x3;
intrvect_linux = (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) & intrvect_linux = (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) &
MPC52xx_IRQ_L1_MASK; MPC52xx_IRQ_L1_MASK;
intrvect_linux |= intrvect_l2 & MPC52xx_IRQ_L2_MASK; intrvect_linux |= intrvect_l2 & MPC52xx_IRQ_L2_MASK;
pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
intrvect_l2);
*out_hwirq = intrvect_linux; *out_hwirq = intrvect_linux;
*out_flags = mpc52xx_map_senses[intrvect_type]; *out_flags = IRQ_TYPE_LEVEL_LOW;
if (mpc52xx_is_extirq(intrvect_l1, intrvect_l2))
*out_flags = mpc52xx_map_senses[intrvect_type];
pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
intrvect_l2);
return 0; return 0;
} }
/**
* mpc52xx_irqx_gettype - determine the IRQ sense type (level/edge)
*
* Only external IRQs need this.
*/
static int mpc52xx_irqx_gettype(int irq)
{
int type;
u32 ctrl_reg;
ctrl_reg = in_be32(&intr->ctrl);
type = (ctrl_reg >> (22 - irq * 2)) & 0x3;
return mpc52xx_map_senses[type];
}
/** /**
* mpc52xx_irqhost_map - Hook to map from virq to an irq_chip structure * mpc52xx_irqhost_map - Hook to map from virq to an irq_chip structure
*/ */
...@@ -422,68 +393,46 @@ static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq, ...@@ -422,68 +393,46 @@ static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
{ {
int l1irq; int l1irq;
int l2irq; int l2irq;
struct irq_chip *good_irqchip; struct irq_chip *irqchip;
void *good_handle; void *hndlr;
int type; int type;
u32 reg;
l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET; l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
l2irq = irq & MPC52xx_IRQ_L2_MASK; l2irq = irq & MPC52xx_IRQ_L2_MASK;
/* /*
* Most of ours IRQs will be level low * External IRQs are handled differently by the hardware so they are
* Only external IRQs on some platform may be others * handled by a dedicated irq_chip structure.
*/ */
type = IRQ_TYPE_LEVEL_LOW; if (mpc52xx_is_extirq(l1irq, l2irq)) {
reg = in_be32(&intr->ctrl);
type = mpc52xx_map_senses[(reg >> (22 - l2irq * 2)) & 0x3];
if ((type == IRQ_TYPE_EDGE_FALLING) ||
(type == IRQ_TYPE_EDGE_RISING))
hndlr = handle_edge_irq;
else
hndlr = handle_level_irq;
set_irq_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr);
pr_debug("%s: External IRQ%i virq=%x, hw=%x. type=%x\n",
__func__, l2irq, virq, (int)irq, type);
return 0;
}
/* It is an internal SOC irq. Choose the correct irq_chip */
switch (l1irq) { switch (l1irq) {
case MPC52xx_IRQ_L1_CRIT: case MPC52xx_IRQ_L1_MAIN: irqchip = &mpc52xx_main_irqchip; break;
pr_debug("%s: Critical. l2=%x\n", __func__, l2irq); case MPC52xx_IRQ_L1_PERP: irqchip = &mpc52xx_periph_irqchip; break;
case MPC52xx_IRQ_L1_SDMA: irqchip = &mpc52xx_sdma_irqchip; break;
BUG_ON(l2irq != 0);
type = mpc52xx_irqx_gettype(l2irq);
good_irqchip = &mpc52xx_extirq_irqchip;
break;
case MPC52xx_IRQ_L1_MAIN:
pr_debug("%s: Main IRQ[1-3] l2=%x\n", __func__, l2irq);
if ((l2irq >= 1) && (l2irq <= 3)) {
type = mpc52xx_irqx_gettype(l2irq);
good_irqchip = &mpc52xx_extirq_irqchip;
} else {
good_irqchip = &mpc52xx_main_irqchip;
}
break;
case MPC52xx_IRQ_L1_PERP:
pr_debug("%s: Peripherals. l2=%x\n", __func__, l2irq);
good_irqchip = &mpc52xx_periph_irqchip;
break;
case MPC52xx_IRQ_L1_SDMA:
pr_debug("%s: SDMA. l2=%x\n", __func__, l2irq);
good_irqchip = &mpc52xx_sdma_irqchip;
break;
default: default:
pr_err("%s: invalid virq requested (0x%x)\n", __func__, virq); pr_err("%s: invalid irq: virq=%i, l1=%i, l2=%i\n",
__func__, virq, l1irq, l2irq);
return -EINVAL; return -EINVAL;
} }
switch (type) { set_irq_chip_and_handler(virq, irqchip, handle_level_irq);
case IRQ_TYPE_EDGE_FALLING: pr_debug("%s: virq=%x, l1=%i, l2=%i\n", __func__, virq, l1irq, l2irq);
case IRQ_TYPE_EDGE_RISING:
good_handle = handle_edge_irq;
break;
default:
good_handle = handle_level_irq;
}
set_irq_chip_and_handler(virq, good_irqchip, good_handle);
pr_debug("%s: virq=%x, hw=%x. type=%x\n", __func__, virq,
(int)irq, type);
return 0; return 0;
} }
...@@ -522,6 +471,8 @@ void __init mpc52xx_init_irq(void) ...@@ -522,6 +471,8 @@ void __init mpc52xx_init_irq(void)
panic(__FILE__ ": find_and_map failed on 'mpc5200-bestcomm'. " panic(__FILE__ ": find_and_map failed on 'mpc5200-bestcomm'. "
"Check node !"); "Check node !");
pr_debug("MPC5200 IRQ controller mapped to 0x%p\n", intr);
/* Disable all interrupt sources. */ /* Disable all interrupt sources. */
out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */ out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */ out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
...@@ -613,8 +564,5 @@ unsigned int mpc52xx_get_irq(void) ...@@ -613,8 +564,5 @@ unsigned int mpc52xx_get_irq(void)
} }
} }
pr_debug("%s: irq=%x. virq=%d\n", __func__, irq,
irq_linear_revmap(mpc52xx_irqhost, irq));
return irq_linear_revmap(mpc52xx_irqhost, irq); return irq_linear_revmap(mpc52xx_irqhost, irq);
} }
...@@ -1123,9 +1123,9 @@ static int mpc52xx_fec_of_resume(struct of_device *op) ...@@ -1123,9 +1123,9 @@ static int mpc52xx_fec_of_resume(struct of_device *op)
#endif #endif
static struct of_device_id mpc52xx_fec_match[] = { static struct of_device_id mpc52xx_fec_match[] = {
{ .type = "network", .compatible = "fsl,mpc5200b-fec", }, { .compatible = "fsl,mpc5200b-fec", },
{ .type = "network", .compatible = "fsl,mpc5200-fec", }, { .compatible = "fsl,mpc5200-fec", },
{ .type = "network", .compatible = "mpc5200-fec", }, { .compatible = "mpc5200-fec", },
{ } { }
}; };
......
...@@ -50,8 +50,8 @@ ...@@ -50,8 +50,8 @@
/* OF Platform device Usage : /* OF Platform device Usage :
* *
* This driver is only used for PSCs configured in uart mode. The device * This driver is only used for PSCs configured in uart mode. The device
* tree will have a node for each PSC in uart mode w/ device_type = "serial" * tree will have a node for each PSC with "mpc52xx-psc-uart" in the compatible
* and "mpc52xx-psc-uart" in the compatible string * list.
* *
* By default, PSC devices are enumerated in the order they are found. However * By default, PSC devices are enumerated in the order they are found. However
* a particular PSC number can be forces by adding 'device_no = <port#>' * a particular PSC number can be forces by adding 'device_no = <port#>'
...@@ -522,7 +522,7 @@ mpc52xx_uart_startup(struct uart_port *port) ...@@ -522,7 +522,7 @@ mpc52xx_uart_startup(struct uart_port *port)
/* Request IRQ */ /* Request IRQ */
ret = request_irq(port->irq, mpc52xx_uart_int, ret = request_irq(port->irq, mpc52xx_uart_int,
IRQF_DISABLED | IRQF_SAMPLE_RANDOM | IRQF_SHARED, IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
"mpc52xx_psc_uart", port); "mpc52xx_psc_uart", port);
if (ret) if (ret)
return ret; return ret;
...@@ -1212,30 +1212,18 @@ mpc52xx_uart_of_resume(struct of_device *op) ...@@ -1212,30 +1212,18 @@ mpc52xx_uart_of_resume(struct of_device *op)
#endif #endif
static void static void
mpc52xx_uart_of_assign(struct device_node *np, int idx) mpc52xx_uart_of_assign(struct device_node *np)
{ {
int free_idx = -1;
int i; int i;
/* Find the first free node */ /* Find the first free PSC number */
for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
if (mpc52xx_uart_nodes[i] == NULL) { if (mpc52xx_uart_nodes[i] == NULL) {
free_idx = i; of_node_get(np);
break; mpc52xx_uart_nodes[i] = np;
return;
} }
} }
if ((idx < 0) || (idx >= MPC52xx_PSC_MAXNUM))
idx = free_idx;
if (idx < 0)
return; /* No free slot; abort */
of_node_get(np);
/* If the slot is already occupied, then swap slots */
if (mpc52xx_uart_nodes[idx] && (free_idx != -1))
mpc52xx_uart_nodes[free_idx] = mpc52xx_uart_nodes[idx];
mpc52xx_uart_nodes[idx] = np;
} }
static void static void
...@@ -1243,23 +1231,17 @@ mpc52xx_uart_of_enumerate(void) ...@@ -1243,23 +1231,17 @@ mpc52xx_uart_of_enumerate(void)
{ {
static int enum_done; static int enum_done;
struct device_node *np; struct device_node *np;
const unsigned int *devno;
const struct of_device_id *match; const struct of_device_id *match;
int i; int i;
if (enum_done) if (enum_done)
return; return;
for_each_node_by_type(np, "serial") { /* Assign index to each PSC in device tree */
for_each_matching_node(np, mpc52xx_uart_of_match) {
match = of_match_node(mpc52xx_uart_of_match, np); match = of_match_node(mpc52xx_uart_of_match, np);
if (!match)
continue;
psc_ops = match->data; psc_ops = match->data;
mpc52xx_uart_of_assign(np);
/* Is a particular device number requested? */
devno = of_get_property(np, "port-number", NULL);
mpc52xx_uart_of_assign(np, devno ? *devno : -1);
} }
enum_done = 1; enum_done = 1;
......
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