Commit 6b9e1233 authored by Vladimir Murzin's avatar Vladimir Murzin Committed by Greg Kroah-Hartman

ARM: 8670/1: V7M: Do not corrupt vector table around v7m_invalidate_l1 call

commit 6d805949 upstream.

We save/restore registers around v7m_invalidate_l1 to address pointed
by r12, which is vector table, so the first eight entries are
overwritten with a garbage. We already have stack setup at that stage,
so use it to save/restore register.

Fixes: 6a8146f4 ("ARM: 8609/1: V7M: Add support for the Cortex-M7 processor")
Signed-off-by: default avatarVladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 3e957020
...@@ -147,10 +147,10 @@ __v7m_setup_cont: ...@@ -147,10 +147,10 @@ __v7m_setup_cont:
@ Configure caches (if implemented) @ Configure caches (if implemented)
teq r8, #0 teq r8, #0
stmneia r12, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6 stmneia sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
blne v7m_invalidate_l1 blne v7m_invalidate_l1
teq r8, #0 @ re-evalutae condition teq r8, #0 @ re-evalutae condition
ldmneia r12, {r0-r6, lr} ldmneia sp, {r0-r6, lr}
@ Configure the System Control Register to ensure 8-byte stack alignment @ Configure the System Control Register to ensure 8-byte stack alignment
@ Note the STKALIGN bit is either RW or RAO. @ Note the STKALIGN bit is either RW or RAO.
......
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