Commit 6bb99d2b authored by Andrew Morton's avatar Andrew Morton Committed by Linus Torvalds

[PATCH] cciss: fix initialization for PCI hotplug

Patch from Stephen Cameron <steve.cameron@hp.com>

* Fix driver to wait for firmware to indicate that it is ready.
  (Needed for PCI hotplug case, but for normal warm/cold reboot, by the
  time driver inits, firmware will already be ready.)
parent c959468f
...@@ -2064,7 +2064,7 @@ static int cciss_pci_init(ctlr_info_t *c, struct pci_dev *pdev) ...@@ -2064,7 +2064,7 @@ static int cciss_pci_init(ctlr_info_t *c, struct pci_dev *pdev)
unchar cache_line_size, latency_timer; unchar cache_line_size, latency_timer;
unchar irq, revision; unchar irq, revision;
uint addr[6]; uint addr[6];
__u32 board_id; __u32 board_id, scratchpad = 0;
int cfg_offset; int cfg_offset;
int cfg_base_addr; int cfg_base_addr;
int cfg_base_addr_index; int cfg_base_addr_index;
...@@ -2156,6 +2156,20 @@ static int cciss_pci_init(ctlr_info_t *c, struct pci_dev *pdev) ...@@ -2156,6 +2156,20 @@ static int cciss_pci_init(ctlr_info_t *c, struct pci_dev *pdev)
#endif /* CCISS_DEBUG */ #endif /* CCISS_DEBUG */
c->vaddr = remap_pci_mem(c->paddr, 200); c->vaddr = remap_pci_mem(c->paddr, 200);
/* Wait for the board to become ready. (PCI hotplug needs this.)
* We poll for up to 120 secs, once per 100ms. */
for (i=0; i < 1200; i++) {
scratchpad = readl(c->vaddr + SA5_SCRATCHPAD_OFFSET);
if (scratchpad == CCISS_FIRMWARE_READY)
break;
set_current_state(TASK_INTERRUPTIBLE);
schedule_timeout(HZ / 10); /* wait 100ms */
}
if (scratchpad != CCISS_FIRMWARE_READY) {
printk(KERN_WARNING "cciss: Board not ready. Timed out.\n");
return -1;
}
/* get the address index number */ /* get the address index number */
cfg_base_addr = readl(c->vaddr + SA5_CTCFG_OFFSET); cfg_base_addr = readl(c->vaddr + SA5_CTCFG_OFFSET);
/* I am not prepared to deal with a 64 bit address value */ /* I am not prepared to deal with a 64 bit address value */
......
...@@ -95,6 +95,7 @@ struct ctlr_info ...@@ -95,6 +95,7 @@ struct ctlr_info
#define SA5_REPLY_INTR_MASK_OFFSET 0x34 #define SA5_REPLY_INTR_MASK_OFFSET 0x34
#define SA5_REPLY_PORT_OFFSET 0x44 #define SA5_REPLY_PORT_OFFSET 0x44
#define SA5_INTR_STATUS 0x30 #define SA5_INTR_STATUS 0x30
#define SA5_SCRATCHPAD_OFFSET 0xB0
#define SA5_CTCFG_OFFSET 0xB4 #define SA5_CTCFG_OFFSET 0xB4
#define SA5_CTMEM_OFFSET 0xB8 #define SA5_CTMEM_OFFSET 0xB8
...@@ -104,6 +105,7 @@ struct ctlr_info ...@@ -104,6 +105,7 @@ struct ctlr_info
#define SA5_INTR_PENDING 0x08 #define SA5_INTR_PENDING 0x08
#define SA5B_INTR_PENDING 0x04 #define SA5B_INTR_PENDING 0x04
#define FIFO_EMPTY 0xffffffff #define FIFO_EMPTY 0xffffffff
#define CCISS_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
#define CISS_ERROR_BIT 0x02 #define CISS_ERROR_BIT 0x02
......
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